riscv-spike: support for Spike emulation of riscv
Spike support: QEMU RISCV is broken, and the maintainers at Berkeley
are working on it, but at the moment spike is the only way to test
on riscv. Add support for spike console output for debugging.
Privileged ISA: Update to privileged ISA in RISCV (machine,
supervisor, hypervisor, user modes) broke exisitng RISCV asm, and
bootblock.S was updated to match the new spec. Clean old assembly
[pg: things build with gcc 4.9 now, but don't expect them to work.
Hardcoding register names into the assembler language may not be the smartest
idea of the RISCV folks.]
Signed-off-by: Thaminda Edirisooriya <firstname.lastname@example.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <email@example.com>
16 files changed