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review.coreboot.org / coreboot / 0141f0d6b899d0f177cce5820a5fc7c6dad0c13d / . / src / southbridge / amd / pi / hudson / pci_devs.h
blob: 7c29380e188b21e0d4b045f761ddf31805b89432 [file] [log] [blame]
Angel Pons182dbde2020-04-02 23:49:05 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]2
3#ifndef _PI_HUDSON_PCI_DEVS_H_
4#define _PI_HUDSON_PCI_DEVS_H_
5
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]6#define BUS0 0
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]7
8/* XHCI */
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]9#define XHCI_DEV 0x10
10#define XHCI_FUNC 0
11#define XHCI_DEVID 0x7814
12#define XHCI_DEVFN PCI_DEVFN(XHCI_DEV,XHCI_FUNC)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]13
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]14#define XHCI2_DEV 0x10
15#define XHCI2_FUNC 1
16#define XHCI2_DEVID 0x7814
17#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV,XHCI2_FUNC)
Dave Frodin9cfa7422015-01-27 07:19:48 -0700[diff] [blame]18
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]19/* SATA */
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]20#define SATA_DEV 0x11
21#define SATA_FUNC 0
22#define SATA_IDE_DEVID 0x7800
23#define AHCI_DEVID_MS 0x7801
24#define AHCI_DEVID_AMD 0x7804
25#define SATA_DEVFN PCI_DEVFN(SATA_DEV,SATA_FUNC)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]26
27/* OHCI */
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]28#define OHCI1_DEV 0x12
29#define OHCI1_FUNC 0
30#define OHCI2_DEV 0x13
31#define OHCI2_FUNC 0
32#define OHCI3_DEV 0x16
33#define OHCI3_FUNC 0
34#define OHCI4_DEV 0x14
35#define OHCI4_FUNC 5
36#define OHCI_DEVID 0x7807
37#define OHCI1_DEVFN PCI_DEVFN(OHCI1_DEV,OHCI1_FUNC)
38#define OHCI2_DEVFN PCI_DEVFN(OHCI2_DEV,OHCI2_FUNC)
39#define OHCI3_DEVFN PCI_DEVFN(OHCI3_DEV,OHCI3_FUNC)
40#define OHCI4_DEVFN PCI_DEVFN(OHCI4_DEV,OHCI4_FUNC)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]41
42/* EHCI */
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]43#define EHCI1_DEV 0x12
44#define EHCI1_FUNC 2
45#define EHCI2_DEV 0x13
46#define EHCI2_FUNC 2
47#define EHCI3_DEV 0x16
48#define EHCI3_FUNC 2
49#define EHCI_DEVID 0x7808
50#define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV,EHCI1_FUNC)
51#define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV,EHCI2_FUNC)
52#define EHCI3_DEVFN PCI_DEVFN(EHCI3_DEV,EHCI3_FUNC)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]53
54/* SMBUS */
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]55#define SMBUS_DEV 0x14
56#define SMBUS_FUNC 0
57#define SMBUS_DEVID 0x780B
58#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]59
Dave Frodin9cfa7422015-01-27 07:19:48 -0700[diff] [blame]60/* IDE */
Julius Wernercd49cce2019-03-05 16:53:33 -0800[diff] [blame]61#if CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON)
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]62#define IDE_DEV 0x14
63#define IDE_FUNC 1
64#define IDE_DEVID 0x780C
65#define IDE_DEVFN PCI_DEVFN(IDE_DEV,IDE_FUNC)
Dave Frodin9cfa7422015-01-27 07:19:48 -0700[diff] [blame]66#endif
67
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]68/* HD Audio */
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]69#define HDA_DEV 0x14
70#define HDA_FUNC 2
71#define HDA_DEVID 0x780D
72#define HDA_DEVFN PCI_DEVFN(HDA_DEV,HDA_FUNC)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]73
74/* LPC BUS */
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]75#define PCU_DEV 0x14
Philipp Deppenwiese30670122017-03-01 02:24:33 +0100[diff] [blame]76#define LPC_DEV PCU_DEV
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]77#define LPC_FUNC 3
78#define LPC_DEVID 0x780E
79#define LPC_DEVFN PCI_DEVFN(LPC_DEV,LPC_FUNC)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]80
81/* PCI Ports */
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]82#define SB_PCI_PORT_DEV 0x14
83#define SB_PCI_PORT_FUNC 4
84#define SB_PCI_PORT_DEVID 0x780F
85#define SB_PCI_PORT_DEVFN PCI_DEVFN(SB_PCI_PORT_DEV,SB_PCI_PORT_FUNC)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]86
87/* SD Controller */
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]88#define SD_DEV 0x14
89#define SD_FUNC 7
90#define SD_DEVID 0x7806
91#define SD_DEVFN PCI_DEVFN(SD_DEV,SD_FUNC)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]92
Dave Frodin9cfa7422015-01-27 07:19:48 -0700[diff] [blame]93/* PCIe Ports */
Julius Wernercd49cce2019-03-05 16:53:33 -0800[diff] [blame]94#if CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON)
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]95#define SB_PCIE_DEV 0x15
96#define SB_PCIE_PORT1_FUNC 0
97#define SB_PCIE_PORT2_FUNC 1
98#define SB_PCIE_PORT3_FUNC 2
99#define SB_PCIE_PORT4_FUNC 3
100#define SB_PCIE_PORT1_DEVID 0x7820
101#define SB_PCIE_PORT2_DEVID 0x7821
102#define SB_PCIE_PORT3_DEVID 0x7822
103#define SB_PCIE_PORT4_DEVID 0x7823
104#define SB_PCIE_PORT1_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT1_FUNC)
105#define SB_PCIE_PORT2_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT2_FUNC)
106#define SB_PCIE_PORT3_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT3_FUNC)
107#define SB_PCIE_PORT4_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT4_FUNC)
Dave Frodin9cfa7422015-01-27 07:19:48 -0700[diff] [blame]108#endif
109
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]110#endif /* _PI_HUDSON_PCI_DEVS_H_ */