Angel Pons | f5627e8 | 2020-04-05 15:46:52 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 2 | |
| 3 | #include <assert.h> |
Christian Walter | b2f8ce7 | 2020-03-11 18:04:58 +0100 | [diff] [blame] | 4 | #include <device/pci_def.h> |
| 5 | #include <device/pci.h> |
Lijian Zhao | 68890b9 | 2019-03-27 17:06:41 -0700 | [diff] [blame] | 6 | #include <cpu/x86/msr.h> |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 7 | #include <console/console.h> |
| 8 | #include <fsp/util.h> |
Michael Niewöhner | 7736bfc | 2019-10-22 23:05:06 +0200 | [diff] [blame] | 9 | #include <intelblocks/cpulib.h> |
Duncan Laurie | 52b5b58 | 2019-01-23 14:55:47 -0800 | [diff] [blame] | 10 | #include <intelblocks/pmclib.h> |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 11 | #include <soc/iomap.h> |
Lijian Zhao | 68890b9 | 2019-03-27 17:06:41 -0700 | [diff] [blame] | 12 | #include <soc/msr.h> |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 13 | #include <soc/pci_devs.h> |
| 14 | #include <soc/romstage.h> |
Angel Pons | 3993d38 | 2021-04-05 11:40:11 +0200 | [diff] [blame] | 15 | #include <types.h> |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 16 | |
Elyes HAOUAS | c338507 | 2019-03-21 15:38:06 +0100 | [diff] [blame] | 17 | #include "../chip.h" |
| 18 | |
Felix Singer | 929b65a | 2021-04-19 01:59:47 +0200 | [diff] [blame] | 19 | void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 20 | { |
Felix Singer | 929b65a | 2021-04-19 01:59:47 +0200 | [diff] [blame] | 21 | const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); |
| 22 | assert(dev != NULL); |
| 23 | const config_t *config = config_of(dev); |
Christian Walter | b2f8ce7 | 2020-03-11 18:04:58 +0100 | [diff] [blame] | 24 | FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; |
| 25 | FSP_M_TEST_CONFIG *tconfig = &mupd->FspmTestConfig; |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 26 | unsigned int i; |
| 27 | uint32_t mask = 0; |
| 28 | |
Christian Walter | b2f8ce7 | 2020-03-11 18:04:58 +0100 | [diff] [blame] | 29 | /* |
| 30 | * Probe for no IGD and disable InternalGfx and panel power to prevent a |
| 31 | * crash in FSP-M. |
| 32 | */ |
Felix Singer | 929b65a | 2021-04-19 01:59:47 +0200 | [diff] [blame] | 33 | dev = pcidev_path_on_root(SA_DEVFN_IGD); |
Angel Pons | 3993d38 | 2021-04-05 11:40:11 +0200 | [diff] [blame] | 34 | const bool igd_on = !CONFIG(SOC_INTEL_DISABLE_IGD) && dev && dev->enabled; |
| 35 | if (igd_on && pci_read_config16(SA_DEV_IGD, PCI_VENDOR_ID) != 0xffff) { |
Christian Walter | b2f8ce7 | 2020-03-11 18:04:58 +0100 | [diff] [blame] | 36 | /* Set IGD stolen size to 64MB. */ |
| 37 | m_cfg->InternalGfx = 1; |
| 38 | m_cfg->IgdDvmt50PreAlloc = 2; |
| 39 | } else { |
| 40 | m_cfg->InternalGfx = 0; |
| 41 | m_cfg->IgdDvmt50PreAlloc = 0; |
| 42 | tconfig->PanelPowerEnable = 0; |
| 43 | } |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 44 | m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; |
| 45 | m_cfg->IedSize = CONFIG_IED_REGION_SIZE; |
| 46 | m_cfg->SaGv = config->SaGv; |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 47 | if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)) |
praveen hodagatta pranesh | e26c4a4 | 2018-09-20 03:49:45 +0800 | [diff] [blame] | 48 | m_cfg->UserBd = BOARD_TYPE_DESKTOP; |
| 49 | else |
| 50 | m_cfg->UserBd = BOARD_TYPE_ULT_ULX; |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 51 | m_cfg->RMT = config->RMT; |
| 52 | |
| 53 | for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { |
| 54 | if (config->PcieRpEnable[i]) |
| 55 | mask |= (1 << i); |
| 56 | } |
| 57 | m_cfg->PcieRpEnableMask = mask; |
Michael Niewöhner | 490546f | 2020-09-15 12:20:08 +0200 | [diff] [blame] | 58 | m_cfg->PrmrrSize = get_valid_prmrr_size(); |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 59 | m_cfg->EnableC6Dram = config->enable_c6dram; |
Aamir Bohra | 2973d1e | 2019-05-17 12:31:51 +0530 | [diff] [blame] | 60 | #if CONFIG(SOC_INTEL_COMETLAKE) |
| 61 | m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; |
Matt DeVillier | 74b85f2 | 2022-01-25 12:16:44 -0600 | [diff] [blame] | 62 | memcpy(tconfig->PcieRpHotPlug, config->PcieRpHotPlug, sizeof(tconfig->PcieRpHotPlug)); |
Aamir Bohra | 2973d1e | 2019-05-17 12:31:51 +0530 | [diff] [blame] | 63 | #else |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 64 | m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE; |
Aamir Bohra | 2973d1e | 2019-05-17 12:31:51 +0530 | [diff] [blame] | 65 | #endif |
Maulik V Vaghela | bfe4a59 | 2019-03-13 18:16:01 +0530 | [diff] [blame] | 66 | /* |
| 67 | * PcdDebugInterfaceFlags |
| 68 | * This config will allow coreboot to pass information to the FSP |
| 69 | * regarding which debug interface is being used. |
| 70 | * Debug Interfaces: |
| 71 | * BIT0-RAM, BIT1-Legacy Uart BIT3-USB3, BIT4-LPSS Uart, BIT5-TraceHub |
| 72 | * BIT2 - Not used. |
| 73 | */ |
| 74 | m_cfg->PcdDebugInterfaceFlags = |
| 75 | CONFIG(DRIVERS_UART_8250IO) ? 0x02 : 0x10; |
| 76 | |
Ronak Kanabar | 250dfc0 | 2019-03-29 13:25:09 +0530 | [diff] [blame] | 77 | /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ |
| 78 | m_cfg->VmxEnable = CONFIG(ENABLE_VMX); |
Subrata Banik | cf32fd1 | 2018-12-19 18:02:17 +0530 | [diff] [blame] | 79 | |
Martin Roth | c25c1eb | 2020-07-24 12:26:21 -0600 | [diff] [blame] | 80 | m_cfg->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT); |
Duncan Laurie | 52b5b58 | 2019-01-23 14:55:47 -0800 | [diff] [blame] | 81 | |
Subrata Banik | e1470ea | 2019-11-18 14:08:08 +0530 | [diff] [blame] | 82 | if (config->cpu_ratio_override) { |
| 83 | m_cfg->CpuRatio = config->cpu_ratio_override; |
| 84 | } else { |
| 85 | /* Set CpuRatio to match existing MSR value */ |
| 86 | msr_t flex_ratio; |
| 87 | flex_ratio = rdmsr(MSR_FLEX_RATIO); |
| 88 | m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; |
| 89 | } |
Duncan Laurie | 52b5b58 | 2019-01-23 14:55:47 -0800 | [diff] [blame] | 90 | |
Christian Walter | b2f8ce7 | 2020-03-11 18:04:58 +0100 | [diff] [blame] | 91 | dev = pcidev_path_on_root(PCH_DEVFN_ISH); |
Lijian Zhao | fe701ee | 2018-10-25 09:29:10 -0700 | [diff] [blame] | 92 | /* If ISH is enabled, enable ISH elements */ |
| 93 | if (!dev) |
| 94 | m_cfg->PchIshEnable = 0; |
| 95 | else |
| 96 | m_cfg->PchIshEnable = dev->enabled; |
Lijian Zhao | 3ef7449 | 2018-12-06 17:29:55 -0800 | [diff] [blame] | 97 | |
| 98 | /* If HDA is enabled, enable HDA elements */ |
Kyösti Mälkki | 903b40a | 2019-07-03 07:25:59 +0300 | [diff] [blame] | 99 | dev = pcidev_path_on_root(PCH_DEVFN_HDA); |
Lijian Zhao | 3ef7449 | 2018-12-06 17:29:55 -0800 | [diff] [blame] | 100 | if (!dev) |
| 101 | m_cfg->PchHdaEnable = 0; |
| 102 | else |
| 103 | m_cfg->PchHdaEnable = dev->enabled; |
| 104 | |
V Sowmya | 0bc3e3d | 2019-01-07 13:11:29 +0530 | [diff] [blame] | 105 | /* Enable IPU only if the device is enabled */ |
| 106 | m_cfg->SaIpuEnable = 0; |
| 107 | dev = pcidev_path_on_root(SA_DEVFN_IPU); |
| 108 | if (dev) |
| 109 | m_cfg->SaIpuEnable = dev->enabled; |
Jamie Chen | c004857da | 2020-01-15 11:17:21 +0800 | [diff] [blame] | 110 | |
| 111 | /* SATA Gen3 strength */ |
| 112 | for (i = 0; i < SOC_INTEL_CML_SATA_DEV_MAX; i++) { |
| 113 | if (config->sata_port[i].RxGen3EqBoostMagEnable) { |
| 114 | m_cfg->PchSataHsioRxGen3EqBoostMagEnable[i] = |
| 115 | config->sata_port[i].RxGen3EqBoostMagEnable; |
| 116 | m_cfg->PchSataHsioRxGen3EqBoostMag[i] = |
| 117 | config->sata_port[i].RxGen3EqBoostMag; |
| 118 | } |
| 119 | if (config->sata_port[i].TxGen3DownscaleAmpEnable) { |
| 120 | m_cfg->PchSataHsioTxGen3DownscaleAmpEnable[i] = |
| 121 | config->sata_port[i].TxGen3DownscaleAmpEnable; |
| 122 | m_cfg->PchSataHsioTxGen3DownscaleAmp[i] = |
| 123 | config->sata_port[i].TxGen3DownscaleAmp; |
| 124 | } |
| 125 | if (config->sata_port[i].TxGen3DeEmphEnable) { |
| 126 | m_cfg->PchSataHsioTxGen3DeEmphEnable[i] = |
| 127 | config->sata_port[i].TxGen3DeEmphEnable; |
| 128 | m_cfg->PchSataHsioTxGen3DeEmph[i] = |
| 129 | config->sata_port[i].TxGen3DeEmph; |
| 130 | } |
| 131 | } |
Christian Walter | e01054d | 2020-04-27 18:11:51 +0200 | [diff] [blame] | 132 | #if !CONFIG(SOC_INTEL_COMETLAKE) |
| 133 | if (config->DisableHeciRetry) |
| 134 | tconfig->DisableHeciRetry = config->DisableHeciRetry; |
| 135 | #endif |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 136 | |
| 137 | /* Enable SMBus controller based on config */ |
Felix Singer | b03e497 | 2021-04-19 01:42:33 +0200 | [diff] [blame] | 138 | dev = pcidev_path_on_root(PCH_DEVFN_SMBUS); |
| 139 | if (!dev) |
Duncan Laurie | 25b387a | 2018-11-08 15:48:14 -0700 | [diff] [blame] | 140 | m_cfg->SmbusEnable = 0; |
| 141 | else |
Felix Singer | b03e497 | 2021-04-19 01:42:33 +0200 | [diff] [blame] | 142 | m_cfg->SmbusEnable = dev->enabled; |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 143 | |
Kane Chen | 3717256 | 2019-04-11 21:55:20 +0800 | [diff] [blame] | 144 | /* Set debug probe type */ |
| 145 | m_cfg->PlatformDebugConsent = |
| 146 | CONFIG_SOC_INTEL_CANNONLAKE_DEBUG_CONSENT; |
John Zhao | 1159a16 | 2019-04-22 10:45:51 -0700 | [diff] [blame] | 147 | |
| 148 | /* Configure VT-d */ |
| 149 | tconfig->VtdDisable = 0; |
| 150 | |
Sridhar Siricilla | a91c919 | 2020-08-05 16:16:52 +0530 | [diff] [blame] | 151 | /* Set HECI1 PCI BAR address */ |
| 152 | m_cfg->Heci1BarAddress = HECI1_BASE_ADDRESS; |
| 153 | |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 154 | mainboard_memory_init_params(mupd); |
| 155 | } |
| 156 | |
| 157 | __weak void mainboard_memory_init_params(FSPM_UPD *mupd) |
| 158 | { |
| 159 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 160 | } |