commit 1159a163cd36318d27f8f3b71617ad4a5b781efb
author John Zhao <john.zhao@intel.com> Mon Apr 22 10:45:51 2019 -0700
committer Nico Huber <nico.h@gmx.de> Sat May 11 11:16:48 2019 +0000
tree 05f00bfd909ae3fb52669596e9e5f23ab096bf8b
parent 4249348735d18cb2d44506090a675a29b0567e7f

soc/intel/cnl: Enable VT-d

Enable VT-d through fsp upd VtdDisable. Update remapping structure
types in numerical order as all remapping structures of type 0 (DRHD)
enumerated before remapping structures of type 1 (RMRR), and so forth.

BUG=b:130351429
TEST=Booted to kernel and verified the DMAR table contents.

Change-Id: I1d20932e417b9d324edd98c8f2195dc228d2e092
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>

src/soc/intel/cannonlake/romstage/fsp_params.c

diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index c71e4b5..6e492bb 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -101,6 +101,7 @@
 	assert(dev != NULL);
 	const config_t *config = dev->chip_info;
 	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
+	FSP_M_TEST_CONFIG *tconfig = &mupd->FspmTestConfig;
 
 	soc_memory_init_params(m_cfg, config);
 
@@ -113,6 +114,10 @@
 	/* Set debug probe type */
 	m_cfg->PlatformDebugConsent =
 		CONFIG_SOC_INTEL_CANNONLAKE_DEBUG_CONSENT;
+
+	/* Configure VT-d */
+	tconfig->VtdDisable = 0;
+
 	mainboard_memory_init_params(mupd);
 }