Praveen hodagatta pranesh | d6e0054 | 2018-11-09 18:15:24 +0800 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
| 3 | # FSP Configuration |
Praveen hodagatta pranesh | d6e0054 | 2018-11-09 18:15:24 +0800 | [diff] [blame] | 4 | register "DspEnable" = "0" |
Praveen hodagatta pranesh | d6e0054 | 2018-11-09 18:15:24 +0800 | [diff] [blame] | 5 | register "ScsEmmcHs400Enabled" = "0" |
Praveen hodagatta pranesh | d6e0054 | 2018-11-09 18:15:24 +0800 | [diff] [blame] | 6 | |
Nico Huber | 44e89af | 2019-02-23 19:24:51 +0100 | [diff] [blame] | 7 | register "serirq_mode" = "SERIRQ_CONTINUOUS" |
Praveen hodagatta pranesh | d6e0054 | 2018-11-09 18:15:24 +0800 | [diff] [blame] | 8 | |
| 9 | # Enable PCIE slot |
| 10 | register "PcieRpEnable[5]" = "1" |
| 11 | register "PcieRpClkReqSupport[5]" = "1" |
| 12 | register "PcieRpClkReqNumber[5]" = "1" #uses SRCCLKREQ1 |
Alexander Goncharov | 893c3ae8 | 2023-02-04 15:20:37 +0400 | [diff] [blame^] | 13 | # RP6, uses CLK SRC 1 |
Praveen hodagatta pranesh | d6e0054 | 2018-11-09 18:15:24 +0800 | [diff] [blame] | 14 | register "PcieRpClkSrcNumber[5]" = "1" |
| 15 | |
| 16 | register "PcieRpEnable[6]" = "1" |
| 17 | register "PcieRpClkReqSupport[6]" = "1" |
| 18 | register "PcieRpClkReqNumber[6]" = "2" #uses SRCCLKREQ2 |
Alexander Goncharov | 893c3ae8 | 2023-02-04 15:20:37 +0400 | [diff] [blame^] | 19 | # RP7, uses CLK SRC 2 |
Praveen hodagatta pranesh | d6e0054 | 2018-11-09 18:15:24 +0800 | [diff] [blame] | 20 | register "PcieRpClkSrcNumber[6]" = "2" |
| 21 | |
| 22 | register "PcieRpEnable[7]" = "1" |
| 23 | register "PcieRpClkReqSupport[7]" = "1" |
| 24 | register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3 |
Alexander Goncharov | 893c3ae8 | 2023-02-04 15:20:37 +0400 | [diff] [blame^] | 25 | # RP8, uses CLK SRC 3 |
Praveen hodagatta pranesh | d6e0054 | 2018-11-09 18:15:24 +0800 | [diff] [blame] | 26 | register "PcieRpClkSrcNumber[7]" = "3" |
| 27 | |
| 28 | register "PcieRpEnable[8]" = "1" |
| 29 | register "PcieRpClkReqSupport[8]" = "1" |
| 30 | register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4 |
Alexander Goncharov | 893c3ae8 | 2023-02-04 15:20:37 +0400 | [diff] [blame^] | 31 | # RP9, uses CLK SRC 4 |
Praveen hodagatta pranesh | d6e0054 | 2018-11-09 18:15:24 +0800 | [diff] [blame] | 32 | register "PcieRpClkSrcNumber[8]" = "4" |
| 33 | |
| 34 | register "PcieRpEnable[13]" = "1" |
| 35 | register "PcieRpClkReqSupport[13]" = "1" |
| 36 | register "PcieRpClkReqNumber[13]" = "5" #uses SRCCLKREQ5 |
Alexander Goncharov | 893c3ae8 | 2023-02-04 15:20:37 +0400 | [diff] [blame^] | 37 | # RP14, uses CLK SRC 5 |
Praveen hodagatta pranesh | d6e0054 | 2018-11-09 18:15:24 +0800 | [diff] [blame] | 38 | register "PcieRpClkSrcNumber[13]" = "5" |
| 39 | |
| 40 | register "PcieRpEnable[16]" = "1" |
| 41 | register "PcieRpClkReqSupport[16]" = "1" |
| 42 | register "PcieRpClkReqNumber[16]" = "7" #uses SRCCLKREQ7 |
Alexander Goncharov | 893c3ae8 | 2023-02-04 15:20:37 +0400 | [diff] [blame^] | 43 | # RP17, uses CLK SRC 7 |
Praveen hodagatta pranesh | d6e0054 | 2018-11-09 18:15:24 +0800 | [diff] [blame] | 44 | register "PcieRpClkSrcNumber[16]" = "7" |
| 45 | |
Praveen hodagatta pranesh | d6e0054 | 2018-11-09 18:15:24 +0800 | [diff] [blame] | 46 | # USB related |
| 47 | register "SsicPortEnable" = "1" |
| 48 | |
| 49 | register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # OTG |
| 50 | register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Touch Pad |
| 51 | register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 BT |
| 52 | register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Touch Panel |
| 53 | register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN |
| 54 | register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Front Panel |
| 55 | register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # Front Panel |
| 56 | register "usb2_ports[7]" = "USB2_PORT_MID(OC2)" # Stacked conn (lan + usb) |
| 57 | register "usb2_ports[8]" = "USB2_PORT_MID(OC2)" # Stacked conn (lan + usb) |
| 58 | register "usb2_ports[9]" = "USB2_PORT_MID(OC1)" # LAN MAGJACK |
| 59 | register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" # LAN MAGJACK |
| 60 | register "usb2_ports[11]" = "USB2_PORT_MID(OC_SKIP)" # Finger print sensor |
| 61 | register "usb2_ports[12]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn |
| 62 | register "usb2_ports[13]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn |
| 63 | |
| 64 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" # OTG |
| 65 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN |
| 66 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Flex |
| 67 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # IVCAM |
| 68 | register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK |
| 69 | register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel |
| 70 | register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel |
| 71 | register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn |
| 72 | register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn |
| 73 | register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK |
| 74 | |
Praveen hodagatta pranesh | d6e0054 | 2018-11-09 18:15:24 +0800 | [diff] [blame] | 75 | register "SataSalpSupport" = "1" |
| 76 | register "SataPortsEnable" = "{ \ |
| 77 | [0] = 1, \ |
| 78 | [1] = 1, \ |
| 79 | [2] = 1, \ |
| 80 | [3] = 1, \ |
| 81 | [4] = 1, \ |
| 82 | [5] = 1, \ |
| 83 | [6] = 1, \ |
| 84 | [7] = 1, \ |
| 85 | }" |
| 86 | register "SerialIoDevMode" = "{ \ |
| 87 | [PchSerialIoIndexI2C0] = PchSerialIoPci, \ |
| 88 | [PchSerialIoIndexI2C1] = PchSerialIoPci, \ |
| 89 | [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ |
| 90 | [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ |
Angel Pons | 9e97021 | 2021-08-29 09:55:43 +0200 | [diff] [blame] | 91 | [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ |
Praveen hodagatta pranesh | d6e0054 | 2018-11-09 18:15:24 +0800 | [diff] [blame] | 92 | [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ |
| 93 | [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ |
| 94 | [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ |
| 95 | [PchSerialIoIndexUart0] = PchSerialIoPci, \ |
| 96 | [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ |
| 97 | [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ |
| 98 | }" |
| 99 | |
| 100 | # PL2 override 60W |
Sumeet R Pawnikar | 97c5464 | 2020-05-10 01:24:11 +0530 | [diff] [blame] | 101 | register "power_limits_config" = "{ |
| 102 | .tdp_pl2_override = 60, |
| 103 | }" |
Praveen hodagatta pranesh | d6e0054 | 2018-11-09 18:15:24 +0800 | [diff] [blame] | 104 | |
Praveen hodagatta pranesh | d6e0054 | 2018-11-09 18:15:24 +0800 | [diff] [blame] | 105 | device domain 0 on |
Felix Singer | 9c1c009 | 2020-07-29 20:48:08 +0200 | [diff] [blame] | 106 | device pci 04.0 off end # SA thermal subsystem |
Angel Pons | a6aaef7 | 2021-08-29 11:10:13 +0200 | [diff] [blame] | 107 | device pci 15.2 off end # I2C #2 |
| 108 | device pci 15.3 off end # I2C #3 |
Praveen hodagatta pranesh | d6e0054 | 2018-11-09 18:15:24 +0800 | [diff] [blame] | 109 | device pci 17.0 on end # SATA |
Angel Pons | 9e97021 | 2021-08-29 09:55:43 +0200 | [diff] [blame] | 110 | device pci 19.2 off end # I2C #4 |
Praveen hodagatta pranesh | d6e0054 | 2018-11-09 18:15:24 +0800 | [diff] [blame] | 111 | device pci 1e.4 off end # eMMC |
| 112 | device pci 1e.6 off end # SDCard |
Felix Singer | 048d9b5 | 2020-07-25 14:31:58 +0200 | [diff] [blame] | 113 | device pci 1f.3 on end # Intel HDA |
Praveen hodagatta pranesh | d6e0054 | 2018-11-09 18:15:24 +0800 | [diff] [blame] | 114 | device pci 1f.6 on end # GbE |
| 115 | end |
| 116 | end |