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review.coreboot.org / coreboot / d6e00546a4cdce308a6a5480887ac03d94c3b826 / . / src / mainboard / intel / kblrvp / variants / rvp11 / overridetree.cb
blob: 119767f48a7598082b2ec934b6c3fe58a498aed1 [file] [log] [blame]
Praveen hodagatta praneshd6e00542018-11-09 18:15:24 +0800[diff] [blame^]1chip soc/intel/skylake
2
3 # FSP Configuration
4 register "EnableAzalia" = "1"
5 register "DspEnable" = "0"
6 register "IoBufferOwnership" = "0"
7 register "ScsEmmcEnabled" = "0"
8 register "ScsEmmcHs400Enabled" = "0"
9 register "ScsSdCardEnabled" = "0"
10 register "Device4Enable" = "0"
11 register "Heci3Enabled" = "0"
12 register "PmTimerDisabled" = "0"
13
14 register "SerialIrqConfigSirqMode" = "0x01"
15
16 # Enable PCIE slot
17 register "PcieRpEnable[5]" = "1"
18 register "PcieRpClkReqSupport[5]" = "1"
19 register "PcieRpClkReqNumber[5]" = "1" #uses SRCCLKREQ1
20 # RP6, uses uses CLK SRC 1
21 register "PcieRpClkSrcNumber[5]" = "1"
22
23 register "PcieRpEnable[6]" = "1"
24 register "PcieRpClkReqSupport[6]" = "1"
25 register "PcieRpClkReqNumber[6]" = "2" #uses SRCCLKREQ2
26 # RP7, uses uses CLK SRC 2
27 register "PcieRpClkSrcNumber[6]" = "2"
28
29 register "PcieRpEnable[7]" = "1"
30 register "PcieRpClkReqSupport[7]" = "1"
31 register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3
32 # RP8, uses uses CLK SRC 3
33 register "PcieRpClkSrcNumber[7]" = "3"
34
35 register "PcieRpEnable[8]" = "1"
36 register "PcieRpClkReqSupport[8]" = "1"
37 register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4
38 # RP9, uses uses CLK SRC 4
39 register "PcieRpClkSrcNumber[8]" = "4"
40
41 register "PcieRpEnable[13]" = "1"
42 register "PcieRpClkReqSupport[13]" = "1"
43 register "PcieRpClkReqNumber[13]" = "5" #uses SRCCLKREQ5
44 # RP14, uses uses CLK SRC 5
45 register "PcieRpClkSrcNumber[13]" = "5"
46
47 register "PcieRpEnable[16]" = "1"
48 register "PcieRpClkReqSupport[16]" = "1"
49 register "PcieRpClkReqNumber[16]" = "7" #uses SRCCLKREQ7
50 # RP17, uses uses CLK SRC 7
51 register "PcieRpClkSrcNumber[16]" = "7"
52
53 register EnableLan = "1"
54
55 # USB related
56 register "SsicPortEnable" = "1"
57
58 register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # OTG
59 register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Touch Pad
60 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 BT
61 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Touch Panel
62 register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
63 register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Front Panel
64 register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # Front Panel
65 register "usb2_ports[7]" = "USB2_PORT_MID(OC2)" # Stacked conn (lan + usb)
66 register "usb2_ports[8]" = "USB2_PORT_MID(OC2)" # Stacked conn (lan + usb)
67 register "usb2_ports[9]" = "USB2_PORT_MID(OC1)" # LAN MAGJACK
68 register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" # LAN MAGJACK
69 register "usb2_ports[11]" = "USB2_PORT_MID(OC_SKIP)" # Finger print sensor
70 register "usb2_ports[12]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn
71 register "usb2_ports[13]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn
72
73 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" # OTG
74 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
75 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Flex
76 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # IVCAM
77 register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK
78 register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel
79 register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel
80 register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn
81 register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn
82 register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK
83
84
85 register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
86
87 register "EnableSata" = "1"
88 register "SataSalpSupport" = "1"
89 register "SataPortsEnable" = "{ \
90 [0] = 1, \
91 [1] = 1, \
92 [2] = 1, \
93 [3] = 1, \
94 [4] = 1, \
95 [5] = 1, \
96 [6] = 1, \
97 [7] = 1, \
98 }"
99 register "SerialIoDevMode" = "{ \
100 [PchSerialIoIndexI2C0] = PchSerialIoPci, \
101 [PchSerialIoIndexI2C1] = PchSerialIoPci, \
102 [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
103 [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
104 [PchSerialIoIndexI2C4] = PchSerialIoPci, \
105 [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
106 [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
107 [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
108 [PchSerialIoIndexUart0] = PchSerialIoPci, \
109 [PchSerialIoIndexUart1] = PchSerialIoDisabled, \
110 [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
111 }"
112
113 # PL2 override 60W
114 register "tdp_pl2_override" = "60"
115
116 # Power Limit Related
117 register "PowerLimit4" = "0"
118
119 # Lock Down
120 register "common_soc_config" = "{
121 .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
122 }"
123
124 device domain 0 on
125 device pci 17.0 on end # SATA
126 device pci 19.1 on end # I2C #5
127 device pci 1e.1 on end # UART #1
128 device pci 1e.2 on end # GSPI #0
129 device pci 1e.3 on end # GSPI #1
130 device pci 1e.4 off end # eMMC
131 device pci 1e.6 off end # SDCard
132 device pci 1f.6 on end # GbE
133 end
134end