Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
Arthur Heymans | 17ad459 | 2018-08-06 15:35:28 +0200 | [diff] [blame] | 17 | #include <cbmem.h> |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 18 | #include <console/console.h> |
| 19 | #include <arch/io.h> |
| 20 | #include <stdint.h> |
| 21 | #include <device/device.h> |
| 22 | #include <device/pci.h> |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 23 | #include <stdlib.h> |
| 24 | #include <string.h> |
| 25 | #include <cpu/cpu.h> |
| 26 | #include <boot/tables.h> |
| 27 | #include <arch/acpi.h> |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 28 | #include <northbridge/intel/pineview/pineview.h> |
Arthur Heymans | de6bda6 | 2018-04-10 13:40:39 +0200 | [diff] [blame] | 29 | #include <cpu/intel/smm/gen1/smi.h> |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 30 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 31 | /* Reserve everything between A segment and 1MB: |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 32 | * |
| 33 | * 0xa0000 - 0xbffff: legacy VGA |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 34 | * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) |
| 35 | * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 36 | */ |
| 37 | static const int legacy_hole_base_k = 0xa0000 / 1024; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 38 | |
Elyes HAOUAS | 6275360 | 2018-02-09 08:46:25 +0100 | [diff] [blame] | 39 | static void add_fixed_resources(struct device *dev, int index) |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 40 | { |
| 41 | struct resource *resource; |
| 42 | |
| 43 | resource = new_resource(dev, index++); |
| 44 | resource->base = (resource_t) 0xfed00000; |
| 45 | resource->size = (resource_t) 0x00100000; |
| 46 | resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | |
| 47 | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; |
| 48 | |
| 49 | mmio_resource(dev, index++, legacy_hole_base_k, |
| 50 | (0xc0000 >> 10) - legacy_hole_base_k); |
| 51 | reserved_ram_resource(dev, index++, 0xc0000 >> 10, |
| 52 | (0x100000 - 0xc0000) >> 10); |
| 53 | } |
| 54 | |
Elyes HAOUAS | 6275360 | 2018-02-09 08:46:25 +0100 | [diff] [blame] | 55 | static void mch_domain_read_resources(struct device *dev) |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 56 | { |
| 57 | u64 tom, touud; |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 58 | u32 tomk, tolud, tseg_sizek; |
Arthur Heymans | 17ad459 | 2018-08-06 15:35:28 +0200 | [diff] [blame] | 59 | u32 pcie_config_base, pcie_config_size, cbmem_topk, delta_cbmem; |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 60 | u16 index; |
| 61 | const u32 top32memk = 4 * (GiB / KiB); |
| 62 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 63 | struct device *mch = pcidev_on_root(0, 0); |
Arthur Heymans | 15e1b39 | 2018-06-26 21:06:13 +0200 | [diff] [blame] | 64 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 65 | index = 3; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 66 | |
| 67 | pci_domain_read_resources(dev); |
| 68 | |
| 69 | /* Top of Upper Usable DRAM, including remap */ |
Arthur Heymans | 15e1b39 | 2018-06-26 21:06:13 +0200 | [diff] [blame] | 70 | touud = pci_read_config16(mch, TOUUD); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 71 | touud <<= 20; |
| 72 | |
| 73 | /* Top of Lower Usable DRAM */ |
Arthur Heymans | 15e1b39 | 2018-06-26 21:06:13 +0200 | [diff] [blame] | 74 | tolud = pci_read_config16(mch, TOLUD) & 0xfff0; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 75 | tolud <<= 16; |
| 76 | |
| 77 | /* Top of Memory - does not account for any UMA */ |
Arthur Heymans | 15e1b39 | 2018-06-26 21:06:13 +0200 | [diff] [blame] | 78 | tom = pci_read_config16(mch, TOM) & 0x1ff; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 79 | tom <<= 27; |
| 80 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 81 | printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx ", |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 82 | touud, tolud, tom); |
| 83 | |
| 84 | tomk = tolud >> 10; |
| 85 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 86 | /* Graphics memory */ |
Arthur Heymans | 15e1b39 | 2018-06-26 21:06:13 +0200 | [diff] [blame] | 87 | const u16 ggc = pci_read_config16(mch, GGC); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 88 | const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf); |
| 89 | printk(BIOS_DEBUG, "%uM UMA", gms_sizek >> 10); |
| 90 | tomk -= gms_sizek; |
| 91 | |
| 92 | /* GTT Graphics Stolen Memory Size (GGMS) */ |
| 93 | const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf); |
| 94 | printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10); |
| 95 | tomk -= gsm_sizek; |
| 96 | |
Arthur Heymans | 15e1b39 | 2018-06-26 21:06:13 +0200 | [diff] [blame] | 97 | const u32 tseg_basek = pci_read_config32(mch, TSEG) >> 10; |
| 98 | const u32 igd_basek = pci_read_config32(mch, GBSM) >> 10; |
| 99 | const u32 gtt_basek = pci_read_config32(mch, BGSM) >> 10; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 100 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 101 | /* Subtract TSEG size */ |
| 102 | tseg_sizek = gtt_basek - tseg_basek; |
| 103 | tomk -= tseg_sizek; |
Arthur Heymans | 17ad459 | 2018-08-06 15:35:28 +0200 | [diff] [blame] | 104 | printk(BIOS_DEBUG, "TSEG decoded, subtracting %dM\n", tseg_sizek >> 10); |
| 105 | |
| 106 | /* cbmem_top can be shifted downwards due to alignment. |
| 107 | Mark the region between cbmem_top and tomk as unusable */ |
| 108 | cbmem_topk = (uint32_t)cbmem_top() >> 10; |
| 109 | delta_cbmem = tomk - cbmem_topk; |
| 110 | tomk -= delta_cbmem; |
| 111 | |
| 112 | printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOMK: 0x%xK\n", |
| 113 | delta_cbmem); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 114 | |
| 115 | /* Report the memory regions */ |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 116 | ram_resource(dev, index++, 0, 640); |
| 117 | ram_resource(dev, index++, 768, tomk - 768); |
| 118 | reserved_ram_resource(dev, index++, tseg_basek, tseg_sizek); |
| 119 | reserved_ram_resource(dev, index++, gtt_basek, gsm_sizek); |
| 120 | reserved_ram_resource(dev, index++, igd_basek, gms_sizek); |
Arthur Heymans | 17ad459 | 2018-08-06 15:35:28 +0200 | [diff] [blame] | 121 | reserved_ram_resource(dev, index++, cbmem_topk, delta_cbmem); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 122 | |
| 123 | /* |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 124 | * If > 4GB installed then memory from TOLUD to 4GB |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 125 | * is remapped above TOM, TOUUD will account for both |
| 126 | */ |
| 127 | touud >>= 10; /* Convert to KB */ |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 128 | if (touud > top32memk) { |
| 129 | ram_resource(dev, index++, top32memk, touud - top32memk); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 130 | printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 131 | (touud - top32memk) >> 10); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 132 | } |
| 133 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 134 | if (decode_pciebar(&pcie_config_base, &pcie_config_size)) { |
| 135 | printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 136 | "size=0x%x\n", pcie_config_base, pcie_config_size); |
| 137 | fixed_mem_resource(dev, index++, pcie_config_base >> 10, |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 138 | pcie_config_size >> 10, IORESOURCE_RESERVE); |
| 139 | } |
| 140 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 141 | add_fixed_resources(dev, index); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 142 | } |
| 143 | |
Arthur Heymans | de6bda6 | 2018-04-10 13:40:39 +0200 | [diff] [blame] | 144 | void northbridge_write_smram(u8 smram) |
| 145 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 146 | struct device *dev = pcidev_on_root(0, 0); |
Arthur Heymans | de6bda6 | 2018-04-10 13:40:39 +0200 | [diff] [blame] | 147 | |
| 148 | if (dev == NULL) |
| 149 | die("could not find pci 00:00.0!\n"); |
| 150 | |
| 151 | pci_write_config8(dev, SMRAM, smram); |
| 152 | } |
| 153 | |
| 154 | /* |
| 155 | * Really doesn't belong here but will go away with parallel mp init, |
| 156 | * so let it be here for a while... |
| 157 | */ |
| 158 | int cpu_get_apic_id_map(int *apic_id_map) |
| 159 | { |
| 160 | unsigned int i; |
| 161 | |
| 162 | /* Logical processors (threads) per core */ |
| 163 | const struct cpuid_result cpuid1 = cpuid(1); |
| 164 | /* Read number of cores. */ |
| 165 | const char cores = (cpuid1.ebx >> 16) & 0xf; |
| 166 | |
| 167 | /* TODO in parallel MP cpuid(1).ebx */ |
| 168 | for (i = 0; i < cores; i++) |
| 169 | apic_id_map[i] = i; |
| 170 | |
| 171 | return cores; |
| 172 | } |
| 173 | |
Elyes HAOUAS | 6275360 | 2018-02-09 08:46:25 +0100 | [diff] [blame] | 174 | static void mch_domain_set_resources(struct device *dev) |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 175 | { |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 176 | struct resource *res; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 177 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 178 | for (res = dev->resource_list; res; res = res->next) |
| 179 | report_resource_stored(dev, res, ""); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 180 | |
| 181 | assign_resources(dev->link_list); |
| 182 | } |
| 183 | |
Elyes HAOUAS | 6275360 | 2018-02-09 08:46:25 +0100 | [diff] [blame] | 184 | static void mch_domain_init(struct device *dev) |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 185 | { |
| 186 | u32 reg32; |
| 187 | |
| 188 | /* Enable SERR */ |
| 189 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 190 | reg32 |= PCI_COMMAND_SERR; |
| 191 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 192 | } |
| 193 | |
Arthur Heymans | a8a9f34 | 2017-12-24 08:11:13 +0100 | [diff] [blame] | 194 | static const char *northbridge_acpi_name(const struct device *dev) |
| 195 | { |
| 196 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 197 | return "PCI0"; |
| 198 | |
| 199 | if (dev->path.type != DEVICE_PATH_PCI || dev->bus->secondary != 0) |
| 200 | return NULL; |
| 201 | |
| 202 | switch (dev->path.pci.devfn) { |
| 203 | case PCI_DEVFN(0, 0): |
| 204 | return "MCHC"; |
| 205 | } |
| 206 | |
| 207 | return NULL; |
| 208 | } |
| 209 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 210 | static struct device_operations pci_domain_ops = { |
| 211 | .read_resources = mch_domain_read_resources, |
| 212 | .set_resources = mch_domain_set_resources, |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 213 | .init = mch_domain_init, |
| 214 | .scan_bus = pci_domain_scan_bus, |
Arthur Heymans | 3b633bb | 2017-04-28 22:36:17 +0200 | [diff] [blame] | 215 | .acpi_fill_ssdt_generator = generate_cpu_entries, |
Arthur Heymans | a8a9f34 | 2017-12-24 08:11:13 +0100 | [diff] [blame] | 216 | .acpi_name = northbridge_acpi_name, |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 217 | }; |
| 218 | |
Elyes HAOUAS | 6275360 | 2018-02-09 08:46:25 +0100 | [diff] [blame] | 219 | static void cpu_bus_init(struct device *dev) |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 220 | { |
| 221 | initialize_cpus(dev->link_list); |
| 222 | } |
| 223 | |
| 224 | static struct device_operations cpu_bus_ops = { |
| 225 | .read_resources = DEVICE_NOOP, |
| 226 | .set_resources = DEVICE_NOOP, |
| 227 | .enable_resources = DEVICE_NOOP, |
| 228 | .init = cpu_bus_init, |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 229 | }; |
| 230 | |
| 231 | |
Elyes HAOUAS | 6275360 | 2018-02-09 08:46:25 +0100 | [diff] [blame] | 232 | static void enable_dev(struct device *dev) |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 233 | { |
| 234 | /* Set the operations if it is a special bus type */ |
| 235 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 236 | dev->ops = &pci_domain_ops; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 237 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 238 | dev->ops = &cpu_bus_ops; |
| 239 | } |
| 240 | } |
| 241 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 242 | struct chip_operations northbridge_intel_pineview_ops = { |
| 243 | CHIP_NAME("Intel Pineview Northbridge") |
| 244 | .enable_dev = enable_dev, |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 245 | }; |