Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; version 2 of the License. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 13 | */ |
| 14 | |
| 15 | #include <console/console.h> |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 16 | #include <commonlib/region.h> |
Kyösti Mälkki | 5687fc9 | 2013-11-28 18:11:49 +0200 | [diff] [blame] | 17 | #include <bootmode.h> |
Elyes HAOUAS | c056729 | 2019-04-28 17:57:47 +0200 | [diff] [blame] | 18 | #include <cf9_reset.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 19 | #include <string.h> |
Subrata Banik | 53b08c3 | 2018-12-10 14:11:35 +0530 | [diff] [blame] | 20 | #include <arch/cpu.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 21 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 22 | #include <device/pci_ops.h> |
Kyösti Mälkki | 1cae454 | 2020-01-06 12:31:34 +0200 | [diff] [blame] | 23 | #include <device/smbus_host.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 24 | #include <cbmem.h> |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 25 | #include <timestamp.h> |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 26 | #include <mrc_cache.h> |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 27 | #include <southbridge/intel/bd82x6x/me.h> |
Patrick Rudolph | da9302a | 2019-03-24 17:01:41 +0100 | [diff] [blame] | 28 | #include <southbridge/intel/bd82x6x/pch.h> |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 29 | #include <cpu/x86/msr.h> |
Elyes HAOUAS | 51401c3 | 2019-05-15 21:09:30 +0200 | [diff] [blame] | 30 | #include <types.h> |
Elyes HAOUAS | bf0970e | 2019-03-21 11:10:03 +0100 | [diff] [blame] | 31 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 32 | #include "raminit_native.h" |
| 33 | #include "raminit_common.h" |
| 34 | #include "sandybridge.h" |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 35 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 36 | /* FIXME: no ECC support */ |
| 37 | /* FIXME: no support for 3-channel chipsets */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 38 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 39 | static void wait_txt_clear(void) |
| 40 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 41 | struct cpuid_result cp = cpuid_ext(1, 0); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 42 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 43 | /* Check if TXT is supported */ |
| 44 | if (!(cp.ecx & (1 << 6))) |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 45 | return; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 46 | |
| 47 | /* Some TXT public bit */ |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 48 | if (!(read32((void *)0xfed30010) & 1)) |
| 49 | return; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 50 | |
| 51 | /* Wait for TXT clear */ |
| 52 | while (!(read8((void *)0xfed40000) & (1 << 7))) |
| 53 | ; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 54 | } |
| 55 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 56 | /* Disable a channel in ramctr_timing */ |
| 57 | static void disable_channel(ramctr_timing *ctrl, int channel) |
| 58 | { |
Patrick Rudolph | 2ccb74b | 2016-03-26 12:16:29 +0100 | [diff] [blame] | 59 | ctrl->rankmap[channel] = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 60 | |
Patrick Rudolph | 2ccb74b | 2016-03-26 12:16:29 +0100 | [diff] [blame] | 61 | memset(&ctrl->rank_mirror[channel][0], 0, sizeof(ctrl->rank_mirror[0])); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 62 | |
Patrick Rudolph | 2ccb74b | 2016-03-26 12:16:29 +0100 | [diff] [blame] | 63 | ctrl->channel_size_mb[channel] = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 64 | ctrl->cmd_stretch[channel] = 0; |
| 65 | ctrl->mad_dimm[channel] = 0; |
| 66 | memset(&ctrl->timings[channel][0], 0, sizeof(ctrl->timings[0])); |
Patrick Rudolph | 74163d6 | 2016-11-17 20:02:43 +0100 | [diff] [blame] | 67 | memset(&ctrl->info.dimm[channel][0], 0, sizeof(ctrl->info.dimm[0])); |
Patrick Rudolph | 2ccb74b | 2016-03-26 12:16:29 +0100 | [diff] [blame] | 68 | } |
| 69 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 70 | /* Fill cbmem with information for SMBIOS type 17 */ |
Patrick Rudolph | 735ecce | 2016-03-26 10:42:27 +0100 | [diff] [blame] | 71 | static void fill_smbios17(ramctr_timing *ctrl) |
Patrick Rudolph | b97009e | 2016-02-28 15:24:04 +0100 | [diff] [blame] | 72 | { |
Patrick Rudolph | b97009e | 2016-02-28 15:24:04 +0100 | [diff] [blame] | 73 | int channel, slot; |
Patrick Rudolph | 24efe73 | 2018-08-19 11:06:06 +0200 | [diff] [blame] | 74 | const u16 ddr_freq = (1000 << 8) / ctrl->tCK; |
Patrick Rudolph | b97009e | 2016-02-28 15:24:04 +0100 | [diff] [blame] | 75 | |
Elyes HAOUAS | 12df950 | 2016-08-23 21:29:48 +0200 | [diff] [blame] | 76 | FOR_ALL_CHANNELS for (slot = 0; slot < NUM_SLOTS; slot++) { |
Patrick Rudolph | 24efe73 | 2018-08-19 11:06:06 +0200 | [diff] [blame] | 77 | enum cb_err ret = spd_add_smbios17(channel, slot, ddr_freq, |
| 78 | &ctrl->info.dimm[channel][slot]); |
| 79 | if (ret != CB_SUCCESS) |
| 80 | printk(BIOS_ERR, "RAMINIT: Failed to add SMBIOS17\n"); |
Patrick Rudolph | b97009e | 2016-02-28 15:24:04 +0100 | [diff] [blame] | 81 | } |
| 82 | } |
| 83 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 84 | /* Return CRC16 match for all SPDs */ |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 85 | static int verify_crc16_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) |
| 86 | { |
| 87 | int channel, slot, spd_slot; |
| 88 | int match = 1; |
| 89 | |
| 90 | FOR_ALL_CHANNELS { |
| 91 | for (slot = 0; slot < NUM_SLOTS; slot++) { |
| 92 | spd_slot = 2 * channel + slot; |
| 93 | match &= ctrl->spd_crc[channel][slot] == |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 94 | spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data)); |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 95 | } |
| 96 | } |
| 97 | return match; |
| 98 | } |
| 99 | |
Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 100 | void read_spd(spd_raw_data * spd, u8 addr, bool id_only) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 101 | { |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 102 | int j; |
Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 103 | if (id_only) { |
| 104 | for (j = 117; j < 128; j++) |
| 105 | (*spd)[j] = do_smbus_read_byte(SMBUS_IO_BASE, addr, j); |
| 106 | } else { |
| 107 | for (j = 0; j < 256; j++) |
| 108 | (*spd)[j] = do_smbus_read_byte(SMBUS_IO_BASE, addr, j); |
| 109 | } |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 110 | } |
| 111 | |
Patrick Rudolph | 735ecce | 2016-03-26 10:42:27 +0100 | [diff] [blame] | 112 | static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 113 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 114 | int dimms = 0, ch_dimms; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 115 | int channel, slot, spd_slot; |
Patrick Rudolph | 735ecce | 2016-03-26 10:42:27 +0100 | [diff] [blame] | 116 | dimm_info *dimm = &ctrl->info; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 117 | |
Elyes HAOUAS | 0d4b11a | 2016-10-03 21:57:21 +0200 | [diff] [blame] | 118 | memset (ctrl->rankmap, 0, sizeof(ctrl->rankmap)); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 119 | |
| 120 | ctrl->extended_temperature_range = 1; |
| 121 | ctrl->auto_self_refresh = 1; |
| 122 | |
| 123 | FOR_ALL_CHANNELS { |
| 124 | ctrl->channel_size_mb[channel] = 0; |
| 125 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 126 | ch_dimms = 0; |
| 127 | /* Count dimms on channel */ |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 128 | for (slot = 0; slot < NUM_SLOTS; slot++) { |
| 129 | spd_slot = 2 * channel + slot; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 130 | printk(BIOS_DEBUG, "SPD probe channel%d, slot%d\n", channel, slot); |
Patrick Rudolph | 5a06185 | 2017-09-22 15:19:26 +0200 | [diff] [blame] | 131 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 132 | spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]); |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 133 | if (dimm->dimm[channel][slot].dram_type == SPD_MEMORY_TYPE_SDRAM_DDR3) |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 134 | ch_dimms++; |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 135 | } |
| 136 | |
| 137 | for (slot = 0; slot < NUM_SLOTS; slot++) { |
| 138 | spd_slot = 2 * channel + slot; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 139 | printk(BIOS_DEBUG, "SPD probe channel%d, slot%d\n", channel, slot); |
Patrick Rudolph | 5a06185 | 2017-09-22 15:19:26 +0200 | [diff] [blame] | 140 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 141 | /* Search for XMP profile */ |
| 142 | spd_xmp_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot], |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 143 | DDR3_XMP_PROFILE_1); |
| 144 | |
| 145 | if (dimm->dimm[channel][slot].dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) { |
| 146 | printram("No valid XMP profile found.\n"); |
| 147 | spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 148 | |
| 149 | } else if (ch_dimms > dimm->dimm[channel][slot].dimms_per_channel) { |
| 150 | printram( |
| 151 | "XMP profile supports %u DIMMs, but %u DIMMs are installed.\n", |
| 152 | dimm->dimm[channel][slot].dimms_per_channel, ch_dimms); |
| 153 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 154 | if (CONFIG(NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS)) |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 155 | printk(BIOS_WARNING, |
| 156 | "XMP maximum DIMMs will be ignored.\n"); |
Vagiz Trakhanov | 771be48 | 2017-10-02 10:02:35 +0000 | [diff] [blame] | 157 | else |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 158 | spd_decode_ddr3(&dimm->dimm[channel][slot], |
| 159 | spd[spd_slot]); |
| 160 | |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 161 | } else if (dimm->dimm[channel][slot].voltage != 1500) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 162 | /* TODO: Support DDR3 voltages other than 1500mV */ |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 163 | printram("XMP profile's requested %u mV is unsupported.\n", |
| 164 | dimm->dimm[channel][slot].voltage); |
| 165 | spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]); |
| 166 | } |
| 167 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 168 | /* Fill in CRC16 for MRC cache */ |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 169 | ctrl->spd_crc[channel][slot] = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 170 | spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data)); |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 171 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 172 | if (dimm->dimm[channel][slot].dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 173 | /* Mark DIMM as invalid */ |
| 174 | dimm->dimm[channel][slot].ranks = 0; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 175 | dimm->dimm[channel][slot].size_mb = 0; |
| 176 | continue; |
| 177 | } |
| 178 | |
| 179 | dram_print_spd_ddr3(&dimm->dimm[channel][slot]); |
| 180 | dimms++; |
| 181 | ctrl->rank_mirror[channel][slot * 2] = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 182 | ctrl->rank_mirror[channel][slot * 2 + 1] = |
| 183 | dimm->dimm[channel][slot].flags.pins_mirrored; |
| 184 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 185 | ctrl->channel_size_mb[channel] += dimm->dimm[channel][slot].size_mb; |
| 186 | |
| 187 | ctrl->auto_self_refresh &= dimm->dimm[channel][slot].flags.asr; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 188 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 189 | ctrl->extended_temperature_range &= |
| 190 | dimm->dimm[channel][slot].flags.ext_temp_refresh; |
| 191 | |
| 192 | ctrl->rankmap[channel] |= |
| 193 | ((1 << dimm->dimm[channel][slot].ranks) - 1) << (2 * slot); |
| 194 | |
| 195 | printk(BIOS_DEBUG, "channel[%d] rankmap = 0x%x\n", channel, |
| 196 | ctrl->rankmap[channel]); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 197 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 198 | if ((ctrl->rankmap[channel] & 0x03) && (ctrl->rankmap[channel] & 0x0c) |
| 199 | && dimm->dimm[channel][0].reference_card <= 5 |
| 200 | && dimm->dimm[channel][1].reference_card <= 5) { |
| 201 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 202 | const int ref_card_offset_table[6][6] = { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 203 | { 0, 0, 0, 0, 2, 2 }, |
| 204 | { 0, 0, 0, 0, 2, 2 }, |
| 205 | { 0, 0, 0, 0, 2, 2 }, |
| 206 | { 0, 0, 0, 0, 1, 1 }, |
| 207 | { 2, 2, 2, 1, 0, 0 }, |
| 208 | { 2, 2, 2, 1, 0, 0 }, |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 209 | }; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 210 | ctrl->ref_card_offset[channel] = ref_card_offset_table |
| 211 | [dimm->dimm[channel][0].reference_card] |
| 212 | [dimm->dimm[channel][1].reference_card]; |
| 213 | } else { |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 214 | ctrl->ref_card_offset[channel] = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 215 | } |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 216 | } |
| 217 | |
| 218 | if (!dimms) |
| 219 | die("No DIMMs were found"); |
| 220 | } |
| 221 | |
Patrick Rudolph | bb9c90a | 2016-05-29 17:05:06 +0200 | [diff] [blame] | 222 | static void save_timings(ramctr_timing *ctrl) |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 223 | { |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 224 | /* Save the MRC S3 restore data to cbmem */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 225 | mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, ctrl, sizeof(*ctrl)); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 226 | } |
| 227 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 228 | static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_uma_size) |
Patrick Rudolph | 27e085a | 2016-03-26 10:59:02 +0100 | [diff] [blame] | 229 | { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 230 | if (ctrl->sandybridge) |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 231 | return try_init_dram_ddr3_snb(ctrl, fast_boot, s3resume, me_uma_size); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 232 | else |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 233 | return try_init_dram_ddr3_ivb(ctrl, fast_boot, s3resume, me_uma_size); |
Patrick Rudolph | 27e085a | 2016-03-26 10:59:02 +0100 | [diff] [blame] | 234 | } |
| 235 | |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 236 | static void init_dram_ddr3(int min_tck, int s3resume) |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 237 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 238 | int me_uma_size, cbmem_was_inited, fast_boot, err; |
Patrick Rudolph | 735ecce | 2016-03-26 10:42:27 +0100 | [diff] [blame] | 239 | ramctr_timing ctrl; |
Kyösti Mälkki | 4cb44e5 | 2016-11-18 19:11:24 +0200 | [diff] [blame] | 240 | spd_raw_data spds[4]; |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 241 | struct region_device rdev; |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 242 | ramctr_timing *ctrl_cached; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 243 | u32 cpu; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 244 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 245 | MCHBAR32(SAPMCTL) |= 1; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 246 | |
| 247 | /* Wait for ME to be ready */ |
| 248 | intel_early_me_init(); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 249 | me_uma_size = intel_early_me_uma_size(); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 250 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 251 | printk(BIOS_DEBUG, "Starting native Platform init\n"); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 252 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 253 | wait_txt_clear(); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 254 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 255 | wrmsr(0x000002e6, (msr_t) { .lo = 0, .hi = 0 }); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 256 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 257 | const u32 sskpd = MCHBAR32(SSKPD); // !!! = 0x00000000 |
| 258 | if ((pci_read_config16(SOUTHBRIDGE, 0xa2) & 0xa0) == 0x20 && sskpd && !s3resume) { |
| 259 | MCHBAR32(SSKPD) = 0; |
| 260 | /* Need reset */ |
Elyes HAOUAS | c056729 | 2019-04-28 17:57:47 +0200 | [diff] [blame] | 261 | system_reset(); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 262 | } |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 263 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 264 | early_pch_init_native(); |
Patrick Rudolph | 6aca7e6 | 2019-03-26 18:22:36 +0100 | [diff] [blame] | 265 | early_init_dmi(); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 266 | early_thermal_init(); |
| 267 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 268 | /* Try to find timings in MRC cache */ |
| 269 | err = mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION, &rdev); |
| 270 | if (err || (region_device_sz(&rdev) < sizeof(ctrl))) { |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 271 | if (s3resume) { |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 272 | /* Failed S3 resume, reset to come up cleanly */ |
Elyes HAOUAS | c056729 | 2019-04-28 17:57:47 +0200 | [diff] [blame] | 273 | system_reset(); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 274 | } |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 275 | ctrl_cached = NULL; |
Patrick Rudolph | 27e085a | 2016-03-26 10:59:02 +0100 | [diff] [blame] | 276 | } else { |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 277 | ctrl_cached = rdev_mmap_full(&rdev); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 278 | } |
| 279 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 280 | /* Verify MRC cache for fast boot */ |
Kyösti Mälkki | 38cb822 | 2016-11-18 19:25:52 +0200 | [diff] [blame] | 281 | if (!s3resume && ctrl_cached) { |
Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 282 | /* Load SPD unique information data. */ |
| 283 | memset(spds, 0, sizeof(spds)); |
| 284 | mainboard_get_spd(spds, 1); |
| 285 | |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 286 | /* check SPD CRC16 to make sure the DIMMs haven't been replaced */ |
| 287 | fast_boot = verify_crc16_spds_ddr3(spds, ctrl_cached); |
| 288 | if (!fast_boot) |
| 289 | printk(BIOS_DEBUG, "Stored timings CRC16 mismatch.\n"); |
Kyösti Mälkki | 38cb822 | 2016-11-18 19:25:52 +0200 | [diff] [blame] | 290 | } else { |
| 291 | fast_boot = s3resume; |
| 292 | } |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 293 | |
| 294 | if (fast_boot) { |
| 295 | printk(BIOS_DEBUG, "Trying stored timings.\n"); |
| 296 | memcpy(&ctrl, ctrl_cached, sizeof(ctrl)); |
| 297 | |
Patrick Rudolph | 588ccaa | 2016-04-20 18:00:27 +0200 | [diff] [blame] | 298 | err = try_init_dram_ddr3(&ctrl, fast_boot, s3resume, me_uma_size); |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 299 | if (err) { |
Patrick Rudolph | 588ccaa | 2016-04-20 18:00:27 +0200 | [diff] [blame] | 300 | if (s3resume) { |
| 301 | /* Failed S3 resume, reset to come up cleanly */ |
Elyes HAOUAS | c056729 | 2019-04-28 17:57:47 +0200 | [diff] [blame] | 302 | system_reset(); |
Patrick Rudolph | 588ccaa | 2016-04-20 18:00:27 +0200 | [diff] [blame] | 303 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 304 | /* No need to erase bad MRC cache here, it gets overwritten on a |
| 305 | successful boot */ |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 306 | printk(BIOS_ERR, "Stored timings are invalid !\n"); |
| 307 | fast_boot = 0; |
| 308 | } |
| 309 | } |
| 310 | if (!fast_boot) { |
Patrick Rudolph | e74ad21 | 2016-11-16 18:06:50 +0100 | [diff] [blame] | 311 | /* Reset internal state */ |
| 312 | memset(&ctrl, 0, sizeof(ctrl)); |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 313 | ctrl.tCK = min_tck; |
| 314 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 315 | /* Get architecture */ |
Subrata Banik | 53b08c3 | 2018-12-10 14:11:35 +0530 | [diff] [blame] | 316 | cpu = cpu_get_cpuid(); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 317 | ctrl.sandybridge = IS_SANDY_CPU(cpu); |
| 318 | |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 319 | /* Get DDR3 SPD data */ |
Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 320 | memset(spds, 0, sizeof(spds)); |
| 321 | mainboard_get_spd(spds, 0); |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 322 | dram_find_spds_ddr3(spds, &ctrl); |
| 323 | |
Patrick Rudolph | 588ccaa | 2016-04-20 18:00:27 +0200 | [diff] [blame] | 324 | err = try_init_dram_ddr3(&ctrl, fast_boot, s3resume, me_uma_size); |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 325 | } |
Patrick Rudolph | 2ccb74b | 2016-03-26 12:16:29 +0100 | [diff] [blame] | 326 | |
Patrick Rudolph | 2ccb74b | 2016-03-26 12:16:29 +0100 | [diff] [blame] | 327 | if (err) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 328 | /* Fallback: disable failing channel */ |
Patrick Rudolph | 2ccb74b | 2016-03-26 12:16:29 +0100 | [diff] [blame] | 329 | printk(BIOS_ERR, "RAM training failed, trying fallback.\n"); |
| 330 | printram("Disable failing channel.\n"); |
| 331 | |
Patrick Rudolph | e74ad21 | 2016-11-16 18:06:50 +0100 | [diff] [blame] | 332 | /* Reset internal state */ |
| 333 | memset(&ctrl, 0, sizeof(ctrl)); |
Patrick Rudolph | e74ad21 | 2016-11-16 18:06:50 +0100 | [diff] [blame] | 334 | ctrl.tCK = min_tck; |
| 335 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 336 | /* Get architecture */ |
Subrata Banik | 53b08c3 | 2018-12-10 14:11:35 +0530 | [diff] [blame] | 337 | cpu = cpu_get_cpuid(); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 338 | ctrl.sandybridge = IS_SANDY_CPU(cpu); |
| 339 | |
Patrick Rudolph | 2ccb74b | 2016-03-26 12:16:29 +0100 | [diff] [blame] | 340 | /* Reset DDR3 frequency */ |
| 341 | dram_find_spds_ddr3(spds, &ctrl); |
| 342 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 343 | /* Disable failing channel */ |
Patrick Rudolph | 2ccb74b | 2016-03-26 12:16:29 +0100 | [diff] [blame] | 344 | disable_channel(&ctrl, GET_ERR_CHANNEL(err)); |
| 345 | |
| 346 | err = try_init_dram_ddr3(&ctrl, fast_boot, s3resume, me_uma_size); |
| 347 | } |
| 348 | |
Patrick Rudolph | 31d1959 | 2016-03-26 12:22:34 +0100 | [diff] [blame] | 349 | if (err) |
| 350 | die("raminit failed"); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 351 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 352 | /* FIXME: should be hardware revision-dependent. The register only exists on IVB. */ |
| 353 | MCHBAR32(CHANNEL_HASH) = 0x00a030ce; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 354 | |
| 355 | set_scrambling_seed(&ctrl); |
| 356 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 357 | set_normal_operation(&ctrl); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 358 | |
| 359 | final_registers(&ctrl); |
| 360 | |
| 361 | /* Zone config */ |
| 362 | dram_zones(&ctrl, 0); |
| 363 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 364 | intel_early_me_status(); |
| 365 | intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); |
| 366 | intel_early_me_status(); |
| 367 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 368 | report_memory_config(); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 369 | |
| 370 | cbmem_was_inited = !cbmem_recovery(s3resume); |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 371 | if (!fast_boot) |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 372 | save_timings(&ctrl); |
| 373 | if (s3resume && !cbmem_was_inited) { |
| 374 | /* Failed S3 resume, reset to come up cleanly */ |
Elyes HAOUAS | c056729 | 2019-04-28 17:57:47 +0200 | [diff] [blame] | 375 | system_reset(); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 376 | } |
Patrick Rudolph | b97009e | 2016-02-28 15:24:04 +0100 | [diff] [blame] | 377 | |
Nico Huber | 9ce5974 | 2018-09-13 10:52:44 +0200 | [diff] [blame] | 378 | if (!s3resume) |
| 379 | fill_smbios17(&ctrl); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 380 | } |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 381 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 382 | void perform_raminit(int s3resume) |
| 383 | { |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 384 | post_code(0x3a); |
| 385 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 386 | timestamp_add_now(TS_BEFORE_INITRAM); |
| 387 | |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 388 | init_dram_ddr3(get_mem_min_tck(), s3resume); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 389 | } |