Elyes HAOUAS | f7b2fe6 | 2020-05-07 12:38:15 +0200 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 2 | |
| 3 | config SOC_INTEL_DENVERTON_NS |
| 4 | bool |
| 5 | help |
| 6 | Intel Denverton-NS SoC support |
| 7 | |
| 8 | if SOC_INTEL_DENVERTON_NS |
| 9 | |
Julien Viard de Galbert | 1c33f74 | 2020-11-07 23:40:43 +0100 | [diff] [blame] | 10 | config CPU_INTEL_NUM_FIT_ENTRIES |
| 11 | int |
| 12 | default 1 |
| 13 | |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 14 | config CPU_SPECIFIC_OPTIONS |
| 15 | def_bool y |
Angel Pons | 8e035e3 | 2021-06-22 12:58:20 +0200 | [diff] [blame] | 16 | select ARCH_X86 |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 17 | select BOOT_DEVICE_SUPPORTS_WRITES |
Subrata Banik | 34f26b2 | 2022-02-10 12:38:02 +0530 | [diff] [blame] | 18 | select CACHE_MRC_SETTINGS |
| 19 | select CPU_INTEL_COMMON |
| 20 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Michael Niewöhner | 9c19bf0 | 2021-09-26 14:23:12 +0200 | [diff] [blame] | 21 | select CPU_SUPPORTS_PM_TIMER_EMULATION |
Nico Huber | 371a667 | 2018-11-13 22:06:40 +0100 | [diff] [blame] | 22 | select DEBUG_GPIO |
Sean Rhodes | 7bbc9a5 | 2022-07-18 11:31:00 +0100 | [diff] [blame] | 23 | select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 |
Subrata Banik | 34f26b2 | 2022-02-10 12:38:02 +0530 | [diff] [blame] | 24 | select FSP_M_XIP |
| 25 | select FSP_T_XIP if FSP_CAR |
Johanna Schander | 8a6e036 | 2019-12-08 15:54:09 +0100 | [diff] [blame] | 26 | select HAVE_INTEL_FSP_REPO |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 27 | select HAVE_SMI_HANDLER |
Stefan Tauner | ef8b957 | 2018-09-06 00:34:28 +0200 | [diff] [blame] | 28 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
Subrata Banik | 34f26b2 | 2022-02-10 12:38:02 +0530 | [diff] [blame] | 29 | select PCR_COMMON_IOSF_1_0 |
| 30 | select PLATFORM_USES_FSP2_0 |
| 31 | select SOC_INTEL_COMMON |
| 32 | select SOC_INTEL_COMMON_RESET |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 33 | select SOC_INTEL_COMMON_BLOCK |
Julien Viard de Galbert | 5a1f540 | 2018-02-08 14:03:28 +0100 | [diff] [blame] | 34 | select SOC_INTEL_COMMON_BLOCK_CPU |
Julien Viard de Galbert | cf2b72f | 2018-04-05 11:24:45 +0200 | [diff] [blame] | 35 | select SOC_INTEL_COMMON_BLOCK_ACPI |
Julien Viard de Galbert | 2912e8e | 2018-08-14 16:15:26 +0200 | [diff] [blame] | 36 | select SOC_INTEL_COMMON_BLOCK_PMC |
| 37 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Jeff Daly | e5ac300 | 2022-01-10 23:47:35 -0500 | [diff] [blame] | 38 | select SOC_INTEL_COMMON_BLOCK_SPI |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 39 | select SOC_INTEL_COMMON_BLOCK_FAST_SPI |
Julien Viard de Galbert | 3ac3a68 | 2018-03-29 11:36:21 +0200 | [diff] [blame] | 40 | select SOC_INTEL_COMMON_BLOCK_GPIO |
Julien Viard de Galbert | 3ac3a68 | 2018-03-29 11:36:21 +0200 | [diff] [blame] | 41 | select SOC_INTEL_COMMON_BLOCK_PCR |
Subrata Banik | fac11d0 | 2022-02-17 20:40:55 +0530 | [diff] [blame] | 42 | select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE |
Kyösti Mälkki | fd13fb5 | 2021-11-18 14:09:36 +0200 | [diff] [blame] | 43 | select SOC_INTEL_COMMON_BLOCK_SMBUS |
Subrata Banik | 34f26b2 | 2022-02-10 12:38:02 +0530 | [diff] [blame] | 44 | select SUPPORT_CPU_UCODE_IN_CBFS |
Kyösti Mälkki | fd13fb5 | 2021-11-18 14:09:36 +0200 | [diff] [blame] | 45 | select SOUTHBRIDGE_INTEL_COMMON_SMBUS |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 46 | select TSC_MONOTONIC_TIMER |
| 47 | select TSC_SYNC_MFENCE |
| 48 | select UDELAY_TSC |
Patrick Rudolph | 05ca054 | 2022-03-22 08:33:40 +0100 | [diff] [blame] | 49 | select UDK_2017_BINDING |
Subrata Banik | 34f26b2 | 2022-02-10 12:38:02 +0530 | [diff] [blame] | 50 | select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM |
| 51 | select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT |
| 52 | select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 53 | |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 54 | config ECAM_MMCONF_BASE_ADDRESS |
Andrey Petrov | dafd514 | 2019-12-30 09:58:47 -0800 | [diff] [blame] | 55 | default 0xe0000000 |
| 56 | |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 57 | config ECAM_MMCONF_BUS_NUMBER |
Kyösti Mälkki | 6fcee75 | 2021-02-14 15:06:50 +0200 | [diff] [blame] | 58 | int |
| 59 | default 256 |
| 60 | |
Felix Singer | fdccfc6 | 2019-01-15 07:29:57 +0100 | [diff] [blame] | 61 | config FSP_HEADER_PATH |
Felix Singer | fdccfc6 | 2019-01-15 07:29:57 +0100 | [diff] [blame] | 62 | default "3rdparty/fsp/DenvertonNSFspBinPkg/Include/" |
| 63 | |
| 64 | config FSP_FD_PATH |
Felix Singer | fdccfc6 | 2019-01-15 07:29:57 +0100 | [diff] [blame] | 65 | default "3rdparty/fsp/DenvertonNSFspBinPkg/FspBin/DenvertonNSFsp.fd" |
| 66 | |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 67 | # CAR memory layout on DENVERTON_NS hardware: |
| 68 | ## CAR base address - 0xfef00000 |
| 69 | ## CAR size 1MB - 0x100 (0xfff00) |
| 70 | ## coreboot usage: |
| 71 | ## DCACHE base - 0xfef00000 |
| 72 | ## DCACHE size - 0xb0000 |
| 73 | ## FSP usage: |
| 74 | ## FSP base - 0xfefb0000 |
| 75 | ## FSP size - 0x50000 - 0x100 (0x4ff00) |
| 76 | config MAX_CPUS |
| 77 | int |
| 78 | default 16 |
| 79 | |
Julien Viard de Galbert | 3ac3a68 | 2018-03-29 11:36:21 +0200 | [diff] [blame] | 80 | config PCR_BASE_ADDRESS |
| 81 | hex |
| 82 | default 0xfd000000 |
| 83 | help |
| 84 | This option allows you to select MMIO Base Address of sideband bus. |
| 85 | |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 86 | config DCACHE_RAM_BASE |
| 87 | hex |
| 88 | default 0xfef00000 |
| 89 | |
| 90 | config DCACHE_RAM_SIZE |
| 91 | hex |
| 92 | default 0xb0000 if FSP_CAR |
| 93 | default 0x100000 if !FSP_CAR |
| 94 | |
| 95 | config DCACHE_BSP_STACK_SIZE |
| 96 | hex |
| 97 | default 0x10000 |
| 98 | |
Julien Viard de Galbert | 5a1f540 | 2018-02-08 14:03:28 +0100 | [diff] [blame] | 99 | config CPU_BCLK_MHZ |
| 100 | int |
| 101 | default 100 |
| 102 | |
Michael Niewöhner | ef353e0 | 2021-09-26 15:28:06 +0200 | [diff] [blame] | 103 | config CPU_XTAL_HZ |
| 104 | default 24000000 |
| 105 | |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 106 | config SMM_TSEG_SIZE |
| 107 | hex |
| 108 | default 0x200000 |
| 109 | |
| 110 | config SMM_RESERVED_SIZE |
| 111 | hex |
| 112 | default 0x000000 |
| 113 | |
| 114 | config IQAT_ENABLE |
| 115 | bool "Enable IQAT" |
| 116 | default y |
| 117 | |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 118 | config HSUART_DEV |
| 119 | hex |
| 120 | default 0x1a |
| 121 | |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 122 | choice |
| 123 | prompt "UART mode selection" |
| 124 | default NON_LEGACY_UART_MODE |
| 125 | |
| 126 | config NON_LEGACY_UART_MODE |
| 127 | bool "Non Legacy Mode" |
| 128 | help |
| 129 | Disable legacy UART mode |
| 130 | |
| 131 | config LEGACY_UART_MODE |
| 132 | bool "Legacy Mode" |
| 133 | help |
| 134 | Enable legacy UART mode |
Julien Viard de Galbert | 1c33f74 | 2020-11-07 23:40:43 +0100 | [diff] [blame] | 135 | select CONSOLE_SERIAL |
| 136 | select DRIVERS_UART |
| 137 | select DRIVERS_UART_8250IO |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 138 | endchoice |
| 139 | |
| 140 | config ENABLE_HSUART |
Nico Huber | 3eb720c | 2018-11-11 00:27:41 +0100 | [diff] [blame] | 141 | depends on NON_LEGACY_UART_MODE |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 142 | bool "Enable High-speed UART debug port selected by UART_FOR_CONSOLE." |
| 143 | default n |
| 144 | select CONSOLE_SERIAL |
| 145 | select DRIVERS_UART |
| 146 | select DRIVERS_UART_8250MEM |
| 147 | |
| 148 | config CONSOLE_UART_BASE_ADDRESS |
| 149 | depends on ENABLE_HSUART |
| 150 | hex "MMIO base address for UART" |
| 151 | default 0xd4000000 |
| 152 | |
Julien Viard de Galbert | 1c33f74 | 2020-11-07 23:40:43 +0100 | [diff] [blame] | 153 | choice |
| 154 | prompt "Cache-as-ram implementation" |
| 155 | default USE_DENVERTON_NS_CAR_NEM_ENHANCED |
| 156 | help |
| 157 | This option allows you to select how cache-as-ram (CAR) is set up. |
| 158 | |
| 159 | config USE_DENVERTON_NS_CAR_NEM_ENHANCED |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 160 | bool "Enhanced Non-evict mode" |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 161 | select SOC_INTEL_COMMON_BLOCK_CAR |
Shreesh Chhabbi | 87c7ec7 | 2020-12-03 14:07:15 -0800 | [diff] [blame] | 162 | select INTEL_CAR_NEM_ENHANCED |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 163 | help |
| 164 | A current limitation of NEM (Non-Evict mode) is that code and data sizes |
| 165 | are derived from the requirement to not write out any modified cache line. |
| 166 | With NEM, if there is no physical memory behind the cached area, |
| 167 | the modified data will be lost and NEM results will be inconsistent. |
| 168 | ENHANCED NEM guarantees that modified data is always |
| 169 | kept in cache while clean data is replaced. |
| 170 | |
Julien Viard de Galbert | 1c33f74 | 2020-11-07 23:40:43 +0100 | [diff] [blame] | 171 | config USE_DENVERTON_NS_FSP_CAR |
| 172 | bool "Use FSP CAR" |
| 173 | select FSP_CAR |
| 174 | help |
| 175 | Use FSP APIs to initialize and tear down the Cache-As-Ram. |
| 176 | |
| 177 | endchoice |
| 178 | |
Jeff Daly | abd4b96 | 2022-01-06 00:52:30 -0500 | [diff] [blame] | 179 | config IFD_CHIPSET |
| 180 | string |
| 181 | default "dnv" |
| 182 | |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 183 | endif ## SOC_INTEL_DENVERTON_NS |