commit 1c33f740c444c27e61e025a74ed99955f2ea0288
author Julien Viard de Galbert <julien@vdg.name> Sat Nov 07 23:40:43 2020 +0100
committer Angel Pons <th3fanbus@gmail.com> Fri Nov 20 00:42:38 2020 +0000
tree f828dfb4fcef3adc59be0ccc9a0824cf3a564c29
parent 50a6fe73c6304077a959c483d0d31054ce7177b2

src/soc/intel/denverton_ns: Use improvement in coreboot since 4.9

 - enable microcode in cbfs (won't boot without microcode)
 - force num fit entry to 1 to avoid crash in cbfstool/fit.c
 - re-enable FSP-CAR (tested to boot, while I couldn't boot with NEM)
 - enable io driver for uart in legacy mode (ie emulating legacy port by
   configuring the pci to legacy io address and hiding the pci device)

Signed-off-by: Julien Viard de Galbert <julien@vdg.name>
Change-Id: Ibc5ce91118c6052af23642fb3461f574cd888dea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>

src/soc/intel/denverton_ns/Kconfig

diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig
index 89bbbb0..4981205 100644
--- a/src/soc/intel/denverton_ns/Kconfig
+++ b/src/soc/intel/denverton_ns/Kconfig
@@ -7,6 +7,10 @@
 
 if SOC_INTEL_DENVERTON_NS
 
+config CPU_INTEL_NUM_FIT_ENTRIES
+	int
+	default 1
+
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select ARCH_ALL_STAGES_X86_32
@@ -21,6 +25,7 @@
 	select CACHE_MRC_SETTINGS
 	select PARALLEL_MP
 	select PCR_COMMON_IOSF_1_0
+	select SUPPORT_CPU_UCODE_IN_CBFS
 	select INTEL_DESCRIPTOR_MODE_CAPABLE
 	select SOC_INTEL_COMMON_BLOCK
 	select SOC_INTEL_COMMON_BLOCK_CPU
@@ -134,6 +139,9 @@
 	bool "Legacy Mode"
 	help
 	  Enable legacy UART mode
+	select CONSOLE_SERIAL
+	select DRIVERS_UART
+	select DRIVERS_UART_8250IO
 endchoice
 
 config ENABLE_HSUART
@@ -153,10 +161,14 @@
 	hex
 	default 0x8000
 
-config DENVERTON_NS_CAR_NEM_ENHANCED
+choice
+	prompt "Cache-as-ram implementation"
+	default USE_DENVERTON_NS_CAR_NEM_ENHANCED
+	help
+	  This option allows you to select how cache-as-ram (CAR) is set up.
+
+config USE_DENVERTON_NS_CAR_NEM_ENHANCED
 	bool "Enhanced Non-evict mode"
-	depends on !FSP_CAR
-	default y
 	select SOC_INTEL_COMMON_BLOCK_CAR
 	select USE_CAR_NEM_ENHANCED_V1
 	help
@@ -167,4 +179,12 @@
 	  ENHANCED NEM guarantees that modified data is always
 	  kept in cache while clean data is replaced.
 
+config USE_DENVERTON_NS_FSP_CAR
+	bool "Use FSP CAR"
+	select FSP_CAR
+	help
+	  Use FSP APIs to initialize and tear down the Cache-As-Ram.
+
+endchoice
+
 endif ## SOC_INTEL_DENVERTON_NS