Elyes HAOUAS | f7b2fe6 | 2020-05-07 12:38:15 +0200 | [diff] [blame^] | 1 | # This file is part of the coreboot project. |
| 2 | # SPDX-License-Identifier: GPL-2.0-only |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 3 | |
| 4 | config SOC_INTEL_DENVERTON_NS |
| 5 | bool |
| 6 | help |
| 7 | Intel Denverton-NS SoC support |
| 8 | |
| 9 | if SOC_INTEL_DENVERTON_NS |
| 10 | |
| 11 | config CPU_SPECIFIC_OPTIONS |
| 12 | def_bool y |
| 13 | select ARCH_BOOTBLOCK_X86_32 |
| 14 | select ARCH_RAMSTAGE_X86_32 |
| 15 | select ARCH_ROMSTAGE_X86_32 |
| 16 | select ARCH_VERSTAGE_X86_32 |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 17 | select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH |
| 18 | select BOOT_DEVICE_SUPPORTS_WRITES |
Nico Huber | 371a667 | 2018-11-13 22:06:40 +0100 | [diff] [blame] | 19 | select DEBUG_GPIO |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 20 | select SOC_INTEL_COMMON |
| 21 | select SOC_INTEL_COMMON_RESET |
| 22 | select PLATFORM_USES_FSP2_0 |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 23 | select IOAPIC |
Johanna Schander | 8a6e036 | 2019-12-08 15:54:09 +0100 | [diff] [blame] | 24 | select HAVE_INTEL_FSP_REPO |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 25 | select HAVE_SMI_HANDLER |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 26 | select CACHE_MRC_SETTINGS |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 27 | select PARALLEL_MP |
Julien Viard de Galbert | 3ac3a68 | 2018-03-29 11:36:21 +0200 | [diff] [blame] | 28 | select PCR_COMMON_IOSF_1_0 |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 29 | select SMP |
Stefan Tauner | ef8b957 | 2018-09-06 00:34:28 +0200 | [diff] [blame] | 30 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
Julien Viard de Galbert | cf2b72f | 2018-04-05 11:24:45 +0200 | [diff] [blame] | 31 | select COMMON_FADT |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 32 | select SOC_INTEL_COMMON_BLOCK |
Julien Viard de Galbert | 5a1f540 | 2018-02-08 14:03:28 +0100 | [diff] [blame] | 33 | select SOC_INTEL_COMMON_BLOCK_CPU |
Julien Viard de Galbert | cf2b72f | 2018-04-05 11:24:45 +0200 | [diff] [blame] | 34 | select SOC_INTEL_COMMON_BLOCK_ACPI |
Julien Viard de Galbert | 2912e8e | 2018-08-14 16:15:26 +0200 | [diff] [blame] | 35 | select SOC_INTEL_COMMON_BLOCK_PMC |
| 36 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 37 | select SOC_INTEL_COMMON_BLOCK_FAST_SPI |
Julien Viard de Galbert | 3ac3a68 | 2018-03-29 11:36:21 +0200 | [diff] [blame] | 38 | select SOC_INTEL_COMMON_BLOCK_GPIO |
Julien Viard de Galbert | 3ac3a68 | 2018-03-29 11:36:21 +0200 | [diff] [blame] | 39 | select SOC_INTEL_COMMON_BLOCK_PCR |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 40 | select TSC_MONOTONIC_TIMER |
| 41 | select TSC_SYNC_MFENCE |
| 42 | select UDELAY_TSC |
Subrata Banik | 7455881 | 2018-01-25 11:41:04 +0530 | [diff] [blame] | 43 | select UDK_2015_BINDING |
Vanessa Eusebio | cd97982 | 2018-06-06 13:12:53 -0700 | [diff] [blame] | 44 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Felix Singer | e0b74a1 | 2020-03-03 22:39:02 +0100 | [diff] [blame] | 45 | select SUPPORT_CPU_UCODE_IN_CBFS |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 46 | |
Andrey Petrov | dafd514 | 2019-12-30 09:58:47 -0800 | [diff] [blame] | 47 | config MMCONF_BASE_ADDRESS |
| 48 | hex |
| 49 | default 0xe0000000 |
| 50 | |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 51 | config FSP_T_ADDR |
Elyes HAOUAS | ef90609 | 2020-02-20 19:41:17 +0100 | [diff] [blame] | 52 | hex "Intel FSP-T (temp RAM init) binary location" |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 53 | depends on ADD_FSP_BINARIES && FSP_CAR |
| 54 | default 0xfff30000 |
| 55 | help |
| 56 | The memory location of the Intel FSP-T binary for this platform. |
| 57 | |
| 58 | config FSP_M_ADDR |
| 59 | hex "Intel FSP-M (memory init) binary location" |
| 60 | depends on ADD_FSP_BINARIES |
| 61 | default 0xfff32000 |
| 62 | help |
| 63 | The memory location of the Intel FSP-M binary for this platform. |
| 64 | |
| 65 | config FSP_S_ADDR |
| 66 | hex "Intel FSP-S (silicon init) binary location" |
| 67 | depends on ADD_FSP_BINARIES |
| 68 | default 0xfffc3000 |
| 69 | help |
| 70 | The memory location of the Intel FSP-S binary for this platform. |
| 71 | |
Felix Singer | fdccfc6 | 2019-01-15 07:29:57 +0100 | [diff] [blame] | 72 | config FSP_HEADER_PATH |
Felix Singer | fdccfc6 | 2019-01-15 07:29:57 +0100 | [diff] [blame] | 73 | default "3rdparty/fsp/DenvertonNSFspBinPkg/Include/" |
| 74 | |
| 75 | config FSP_FD_PATH |
Felix Singer | fdccfc6 | 2019-01-15 07:29:57 +0100 | [diff] [blame] | 76 | default "3rdparty/fsp/DenvertonNSFspBinPkg/FspBin/DenvertonNSFsp.fd" |
| 77 | |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 78 | # CAR memory layout on DENVERTON_NS hardware: |
| 79 | ## CAR base address - 0xfef00000 |
| 80 | ## CAR size 1MB - 0x100 (0xfff00) |
| 81 | ## coreboot usage: |
| 82 | ## DCACHE base - 0xfef00000 |
| 83 | ## DCACHE size - 0xb0000 |
| 84 | ## FSP usage: |
| 85 | ## FSP base - 0xfefb0000 |
| 86 | ## FSP size - 0x50000 - 0x100 (0x4ff00) |
| 87 | config MAX_CPUS |
| 88 | int |
| 89 | default 16 |
| 90 | |
Julien Viard de Galbert | 3ac3a68 | 2018-03-29 11:36:21 +0200 | [diff] [blame] | 91 | config PCR_BASE_ADDRESS |
| 92 | hex |
| 93 | default 0xfd000000 |
| 94 | help |
| 95 | This option allows you to select MMIO Base Address of sideband bus. |
| 96 | |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 97 | config DCACHE_RAM_BASE |
| 98 | hex |
| 99 | default 0xfef00000 |
| 100 | |
| 101 | config DCACHE_RAM_SIZE |
| 102 | hex |
| 103 | default 0xb0000 if FSP_CAR |
| 104 | default 0x100000 if !FSP_CAR |
| 105 | |
| 106 | config DCACHE_BSP_STACK_SIZE |
| 107 | hex |
| 108 | default 0x10000 |
| 109 | |
Julien Viard de Galbert | 5a1f540 | 2018-02-08 14:03:28 +0100 | [diff] [blame] | 110 | config CPU_BCLK_MHZ |
| 111 | int |
| 112 | default 100 |
| 113 | |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 114 | config SMM_TSEG_SIZE |
| 115 | hex |
| 116 | default 0x200000 |
| 117 | |
| 118 | config SMM_RESERVED_SIZE |
| 119 | hex |
| 120 | default 0x000000 |
| 121 | |
| 122 | config IQAT_ENABLE |
| 123 | bool "Enable IQAT" |
| 124 | default y |
| 125 | |
| 126 | config IQAT_MEMORY_REGION_SIZE |
| 127 | depends on IQAT_ENABLE |
| 128 | hex |
| 129 | default 0x100000 |
| 130 | help |
| 131 | Do not change this value |
| 132 | |
| 133 | config HSUART_DEV |
| 134 | hex |
| 135 | default 0x1a |
| 136 | |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 137 | choice |
| 138 | prompt "UART mode selection" |
| 139 | default NON_LEGACY_UART_MODE |
| 140 | |
| 141 | config NON_LEGACY_UART_MODE |
| 142 | bool "Non Legacy Mode" |
| 143 | help |
| 144 | Disable legacy UART mode |
| 145 | |
| 146 | config LEGACY_UART_MODE |
| 147 | bool "Legacy Mode" |
| 148 | help |
| 149 | Enable legacy UART mode |
| 150 | endchoice |
| 151 | |
| 152 | config ENABLE_HSUART |
Nico Huber | 3eb720c | 2018-11-11 00:27:41 +0100 | [diff] [blame] | 153 | depends on NON_LEGACY_UART_MODE |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 154 | bool "Enable High-speed UART debug port selected by UART_FOR_CONSOLE." |
| 155 | default n |
| 156 | select CONSOLE_SERIAL |
| 157 | select DRIVERS_UART |
| 158 | select DRIVERS_UART_8250MEM |
| 159 | |
| 160 | config CONSOLE_UART_BASE_ADDRESS |
| 161 | depends on ENABLE_HSUART |
| 162 | hex "MMIO base address for UART" |
| 163 | default 0xd4000000 |
| 164 | |
| 165 | config C_ENV_BOOTBLOCK_SIZE |
| 166 | hex |
| 167 | default 0x8000 |
| 168 | |
| 169 | config DENVERTON_NS_CAR_NEM_ENHANCED |
| 170 | bool "Enhanced Non-evict mode" |
| 171 | depends on !FSP_CAR |
| 172 | default y |
| 173 | select SOC_INTEL_COMMON_BLOCK_CAR |
| 174 | select INTEL_CAR_NEM_ENHANCED |
| 175 | help |
| 176 | A current limitation of NEM (Non-Evict mode) is that code and data sizes |
| 177 | are derived from the requirement to not write out any modified cache line. |
| 178 | With NEM, if there is no physical memory behind the cached area, |
| 179 | the modified data will be lost and NEM results will be inconsistent. |
| 180 | ENHANCED NEM guarantees that modified data is always |
| 181 | kept in cache while clean data is replaced. |
| 182 | |
| 183 | endif ## SOC_INTEL_DENVERTON_NS |