Angel Pons | f94ac9a | 2020-04-05 15:46:48 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 2 | |
Angel Pons | 9d733de | 2020-11-23 13:15:19 +0100 | [diff] [blame] | 3 | #include <cpu/intel/haswell/haswell.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 4 | #include <delay.h> |
| 5 | #include <device/device.h> |
| 6 | #include <device/pci.h> |
| 7 | #include <device/pci_ids.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 8 | #include <acpi/acpi.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 9 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 10 | #include <device/pci_ops.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 11 | #include <soc/xhci.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 12 | |
Kyösti Mälkki | 21d6a27 | 2019-11-05 18:50:38 +0200 | [diff] [blame] | 13 | #ifdef __SIMPLE_DEVICE__ |
Elyes HAOUAS | 4658a98 | 2018-09-20 08:46:35 +0200 | [diff] [blame] | 14 | static u8 *usb_xhci_mem_base(pci_devfn_t dev) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 15 | { |
| 16 | u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); |
| 17 | |
| 18 | /* Check if the controller is disabled or not present */ |
| 19 | if (mem_base == 0 || mem_base == 0xffffffff) |
| 20 | return 0; |
| 21 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 22 | return (u8 *)(mem_base & ~0xf); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 23 | } |
| 24 | |
Elyes HAOUAS | 4658a98 | 2018-09-20 08:46:35 +0200 | [diff] [blame] | 25 | static int usb_xhci_port_count_usb3(pci_devfn_t dev) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 26 | { |
| 27 | /* PCH-LP has 4 SS ports */ |
| 28 | return 4; |
| 29 | } |
| 30 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 31 | static void usb_xhci_reset_status_usb3(u8 *mem_base, int port) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 32 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 33 | u8 *portsc = mem_base + XHCI_USB3_PORTSC(port); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 34 | u32 status = read32(portsc); |
| 35 | /* Do not set Port Enabled/Disabled field */ |
| 36 | status &= ~XHCI_USB3_PORTSC_PED; |
| 37 | /* Clear all change status bits */ |
| 38 | status |= XHCI_USB3_PORTSC_CHST; |
| 39 | write32(portsc, status); |
| 40 | } |
| 41 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 42 | static void usb_xhci_reset_port_usb3(u8 *mem_base, int port) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 43 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 44 | u8 *portsc = mem_base + XHCI_USB3_PORTSC(port); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 45 | write32(portsc, read32(portsc) | XHCI_USB3_PORTSC_WPR); |
| 46 | } |
| 47 | |
| 48 | #define XHCI_RESET_DELAY_US 1000 /* 1ms */ |
| 49 | #define XHCI_RESET_TIMEOUT 100 /* 100ms */ |
| 50 | |
| 51 | /* |
| 52 | * 1) Wait until port is done polling |
| 53 | * 2) If port is disconnected |
| 54 | * a) Issue warm port reset |
| 55 | * b) Poll for warm reset complete |
| 56 | * c) Write 1 to port change status bits |
| 57 | */ |
Elyes HAOUAS | 4658a98 | 2018-09-20 08:46:35 +0200 | [diff] [blame] | 58 | static void usb_xhci_reset_usb3(pci_devfn_t dev, int all) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 59 | { |
| 60 | u32 status, port_disabled; |
| 61 | int timeout, port; |
| 62 | int port_count = usb_xhci_port_count_usb3(dev); |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 63 | u8 *mem_base = usb_xhci_mem_base(dev); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 64 | |
| 65 | if (!mem_base || !port_count) |
| 66 | return; |
| 67 | |
| 68 | /* Get mask of disabled ports */ |
| 69 | port_disabled = pci_read_config32(dev, XHCI_USB3PDO); |
| 70 | |
| 71 | /* Wait until all enabled ports are done polling */ |
| 72 | for (timeout = XHCI_RESET_TIMEOUT; timeout; timeout--) { |
| 73 | int complete = 1; |
| 74 | for (port = 0; port < port_count; port++) { |
| 75 | /* Skip disabled ports */ |
| 76 | if (port_disabled & (1 << port)) |
| 77 | continue; |
| 78 | /* Read port link status field */ |
| 79 | status = read32(mem_base + XHCI_USB3_PORTSC(port)); |
| 80 | status &= XHCI_USB3_PORTSC_PLS; |
| 81 | if (status == XHCI_PLSR_POLLING) |
| 82 | complete = 0; |
| 83 | } |
| 84 | /* Exit if all ports not polling */ |
| 85 | if (complete) |
| 86 | break; |
| 87 | udelay(XHCI_RESET_DELAY_US); |
| 88 | } |
| 89 | |
| 90 | /* Reset all requested ports */ |
| 91 | for (port = 0; port < port_count; port++) { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 92 | u8 *portsc = mem_base + XHCI_USB3_PORTSC(port); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 93 | /* Skip disabled ports */ |
| 94 | if (port_disabled & (1 << port)) |
| 95 | continue; |
| 96 | status = read32(portsc) & XHCI_USB3_PORTSC_PLS; |
| 97 | /* Reset all or only disconnected ports */ |
| 98 | if (all || (status == XHCI_PLSR_RXDETECT || |
| 99 | status == XHCI_PLSR_POLLING)) |
| 100 | usb_xhci_reset_port_usb3(mem_base, port); |
| 101 | else |
| 102 | port_disabled |= 1 << port; |
| 103 | } |
| 104 | |
| 105 | /* Wait for warm reset complete on all reset ports */ |
| 106 | for (timeout = XHCI_RESET_TIMEOUT; timeout; timeout--) { |
| 107 | int complete = 1; |
| 108 | for (port = 0; port < port_count; port++) { |
| 109 | /* Only check ports that were reset */ |
| 110 | if (port_disabled & (1 << port)) |
| 111 | continue; |
| 112 | /* Check if warm reset is complete */ |
| 113 | status = read32(mem_base + XHCI_USB3_PORTSC(port)); |
| 114 | if (!(status & XHCI_USB3_PORTSC_WRC)) |
| 115 | complete = 0; |
| 116 | } |
| 117 | /* Check for warm reset complete in any port */ |
| 118 | if (complete) |
| 119 | break; |
| 120 | udelay(XHCI_RESET_DELAY_US); |
| 121 | } |
| 122 | |
| 123 | /* Clear port change status bits */ |
| 124 | for (port = 0; port < port_count; port++) |
| 125 | usb_xhci_reset_status_usb3(mem_base, port); |
| 126 | } |
| 127 | |
| 128 | /* Handler for XHCI controller on entry to S3/S4/S5 */ |
Elyes HAOUAS | 4658a98 | 2018-09-20 08:46:35 +0200 | [diff] [blame] | 129 | void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 130 | { |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 131 | u32 reg32; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 132 | u8 *mem_base = usb_xhci_mem_base(dev); |
Kane Chen | 4613472 | 2014-08-28 17:05:06 -0700 | [diff] [blame] | 133 | u8 is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 134 | |
Aaron Durbin | 9e6d143 | 2016-07-13 23:21:41 -0500 | [diff] [blame] | 135 | if (!mem_base || slp_typ < ACPI_S3) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 136 | return; |
| 137 | |
| 138 | /* Set D0 state */ |
Angel Pons | 8b8b271 | 2020-09-25 01:04:51 +0200 | [diff] [blame] | 139 | pci_update_config16(dev, XHCI_PWR_CTL_STS, ~XHCI_PWR_CTL_SET_MASK, XHCI_PWR_CTL_SET_D0); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 140 | |
Kane Chen | 4613472 | 2014-08-28 17:05:06 -0700 | [diff] [blame] | 141 | if (!is_broadwell) { |
| 142 | /* This WA is only for lpt */ |
| 143 | |
Patrick Georgi | 46d3ac1 | 2015-04-20 10:27:59 +0200 | [diff] [blame] | 144 | /* Clear PCI 0xB0[14:13] */ |
Angel Pons | 8b8b271 | 2020-09-25 01:04:51 +0200 | [diff] [blame] | 145 | pci_and_config32(dev, 0xb0, ~((1 << 14) | (1 << 13))); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 146 | |
Patrick Georgi | 46d3ac1 | 2015-04-20 10:27:59 +0200 | [diff] [blame] | 147 | /* Clear MMIO 0x816c[14,2] */ |
| 148 | reg32 = read32(mem_base + 0x816c); |
| 149 | reg32 &= ~((1 << 14) | (1 << 2)); |
| 150 | write32(mem_base + 0x816c, reg32); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 151 | |
Patrick Georgi | 46d3ac1 | 2015-04-20 10:27:59 +0200 | [diff] [blame] | 152 | /* Reset disconnected USB3 ports */ |
| 153 | usb_xhci_reset_usb3(dev, 0); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 154 | |
Patrick Georgi | 46d3ac1 | 2015-04-20 10:27:59 +0200 | [diff] [blame] | 155 | /* Set MMIO 0x80e0[15] */ |
| 156 | reg32 = read32(mem_base + 0x80e0); |
| 157 | reg32 |= (1 << 15); |
| 158 | write32(mem_base + 0x80e0, reg32); |
Todd Broch | df4081e | 2015-02-06 17:13:53 -0800 | [diff] [blame] | 159 | } else { |
| 160 | /* |
| 161 | * Clear port change status bits. Clearing CSC alone seemed to |
| 162 | * fix wakeup from S3 if entering USB compliance state even if |
| 163 | * bit wasn't set on the port. |
| 164 | */ |
| 165 | int port; |
| 166 | for (port = 0; port < usb_xhci_port_count_usb3(dev); port++) |
| 167 | usb_xhci_reset_status_usb3(mem_base, port); |
Kane Chen | 4613472 | 2014-08-28 17:05:06 -0700 | [diff] [blame] | 168 | } |
| 169 | |
| 170 | reg32 = read32(mem_base + 0x8154); |
| 171 | reg32 &= ~(1 << 31); |
| 172 | write32(mem_base + 0x8154, reg32); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 173 | |
| 174 | /* Set D3Hot state and enable PME */ |
| 175 | pci_or_config16(dev, XHCI_PWR_CTL_STS, XHCI_PWR_CTL_SET_D3); |
| 176 | pci_or_config16(dev, XHCI_PWR_CTL_STS, XHCI_PWR_CTL_STATUS_PME); |
| 177 | pci_or_config16(dev, XHCI_PWR_CTL_STS, XHCI_PWR_CTL_ENABLE_PME); |
| 178 | } |
Kyösti Mälkki | 21d6a27 | 2019-11-05 18:50:38 +0200 | [diff] [blame] | 179 | #else /* !__SIMPLE_DEVICE__ */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 180 | |
Duncan Laurie | aafdddf | 2015-02-19 16:21:10 -0800 | [diff] [blame] | 181 | static void xhci_init(struct device *dev) |
| 182 | { |
| 183 | struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 184 | u16 reg16; |
| 185 | u32 reg32; |
| 186 | |
| 187 | /* Ensure controller is in D0 state */ |
| 188 | reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS); |
| 189 | reg16 &= ~XHCI_PWR_CTL_SET_MASK; |
| 190 | reg16 |= XHCI_PWR_CTL_SET_D0; |
| 191 | pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16); |
| 192 | |
| 193 | /* Disable Compliance Mode Entry */ |
| 194 | reg32 = read32(res2mmio(res, 0x80ec, 0)); |
| 195 | reg32 |= (1 << 0); |
| 196 | write32(res2mmio(res, 0x80ec, 0), reg32); |
| 197 | } |
| 198 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 199 | static struct device_operations usb_xhci_ops = { |
Elyes HAOUAS | 1d19127 | 2018-11-27 12:23:48 +0100 | [diff] [blame] | 200 | .read_resources = pci_dev_read_resources, |
| 201 | .set_resources = pci_dev_set_resources, |
| 202 | .enable_resources = pci_dev_enable_resources, |
Angel Pons | cb2080f | 2020-10-23 15:45:44 +0200 | [diff] [blame] | 203 | .ops_pci = &pci_dev_ops_pci, |
Elyes HAOUAS | 1d19127 | 2018-11-27 12:23:48 +0100 | [diff] [blame] | 204 | .init = xhci_init, |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 205 | }; |
| 206 | |
| 207 | static const unsigned short pci_device_ids[] = { |
| 208 | 0x9c31, /* LynxPoint-LP */ |
| 209 | 0x9cb1, /* WildcatPoint */ |
| 210 | 0 |
| 211 | }; |
| 212 | |
| 213 | static const struct pci_driver pch_usb_xhci __pci_driver = { |
| 214 | .ops = &usb_xhci_ops, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 215 | .vendor = PCI_VID_INTEL, |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 216 | .devices = pci_device_ids, |
| 217 | }; |
Kyösti Mälkki | 21d6a27 | 2019-11-05 18:50:38 +0200 | [diff] [blame] | 218 | #endif /* !__SIMPLE_DEVICE__ */ |