commit 4658a98a63b36b376de1de228c293b5ef6dbb132
author Elyes HAOUAS <ehaouas@noos.fr> Thu Sep 20 08:46:35 2018 +0200
committer Martin Roth <martinroth@google.com> Fri Sep 21 14:05:04 2018 +0000
tree fc4ec091b022d96fa43a94ca97993db44f6f82ac
parent e2d76a15d1b16040ec2122ddb393c675c2293f1f

soc/broadwell: Don't use device_t

Use of device_t is deprecated.

Change-Id: Ifdf3d1870500812a417eaa5e93fcc168629c094f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>

src/soc/intel/broadwell/xhci.c

diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c
index 75a63cf..8b4c7b1 100644
--- a/src/soc/intel/broadwell/xhci.c
+++ b/src/soc/intel/broadwell/xhci.c
@@ -25,7 +25,7 @@
 #include <soc/cpu.h>
 
 #ifdef __SMM__
-static u8 *usb_xhci_mem_base(device_t dev)
+static u8 *usb_xhci_mem_base(pci_devfn_t dev)
 {
 	u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
 
@@ -36,7 +36,7 @@
 	return (u8 *)(mem_base & ~0xf);
 }
 
-static int usb_xhci_port_count_usb3(device_t dev)
+static int usb_xhci_port_count_usb3(pci_devfn_t dev)
 {
 	/* PCH-LP has 4 SS ports */
 	return 4;
@@ -69,7 +69,7 @@
  *  b) Poll for warm reset complete
  *  c) Write 1 to port change status bits
  */
-static void usb_xhci_reset_usb3(device_t dev, int all)
+static void usb_xhci_reset_usb3(pci_devfn_t dev, int all)
 {
 	u32 status, port_disabled;
 	int timeout, port;
@@ -140,7 +140,7 @@
 }
 
 /* Handler for XHCI controller on entry to S3/S4/S5 */
-void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ)
+void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ)
 {
 	u16 reg16;
 	u32 reg32;