commit 46d3ac1cbb76b721132e792c9e1a9d0e201d55d5
author Patrick Georgi <pgeorgi@chromium.org> Mon Apr 20 10:27:59 2015 +0200
committer Patrick Georgi <pgeorgi@google.com> Tue Apr 21 08:09:24 2015 +0200
tree f2a2e975205f54b44328590c90f5861eec0b4408
parent 1e6b5915ce0e78cad0d31708423bf7a01589268a

broadwell: indent xhci code

Change-Id: I97920e7eb64c05034184f9a4e1c8f2dfa44d3fdd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9813
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/soc/intel/broadwell/xhci.c

diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c
index fde8bf7..cfd0c56 100644
--- a/src/soc/intel/broadwell/xhci.c
+++ b/src/soc/intel/broadwell/xhci.c
@@ -162,23 +162,23 @@
 	if (!is_broadwell) {
 		/* This WA is only for lpt */
 
-	/* Clear PCI 0xB0[14:13] */
-	reg32 = pci_read_config32(dev, 0xb0);
-	reg32 &= ~((1 << 14) | (1 << 13));
-	pci_write_config32(dev, 0xb0, reg32);
+		/* Clear PCI 0xB0[14:13] */
+		reg32 = pci_read_config32(dev, 0xb0);
+		reg32 &= ~((1 << 14) | (1 << 13));
+		pci_write_config32(dev, 0xb0, reg32);
 
-	/* Clear MMIO 0x816c[14,2] */
-	reg32 = read32(mem_base + 0x816c);
-	reg32 &= ~((1 << 14) | (1 << 2));
-	write32(mem_base + 0x816c, reg32);
+		/* Clear MMIO 0x816c[14,2] */
+		reg32 = read32(mem_base + 0x816c);
+		reg32 &= ~((1 << 14) | (1 << 2));
+		write32(mem_base + 0x816c, reg32);
 
-	/* Reset disconnected USB3 ports */
-	usb_xhci_reset_usb3(dev, 0);
+		/* Reset disconnected USB3 ports */
+		usb_xhci_reset_usb3(dev, 0);
 
-	/* Set MMIO 0x80e0[15] */
-	reg32 = read32(mem_base + 0x80e0);
-	reg32 |= (1 << 15);
-	write32(mem_base + 0x80e0, reg32);
+		/* Set MMIO 0x80e0[15] */
+		reg32 = read32(mem_base + 0x80e0);
+		reg32 |= (1 << 15);
+		write32(mem_base + 0x80e0, reg32);
 	}
 
 	reg32 = read32(mem_base + 0x8154);