Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2011 The Chromium OS Authors. |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 3 | * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger |
| 4 | * Copyright (C) 2011 Stefan Tauner |
Werner Zeh | f13a6f9 | 2018-11-14 10:55:52 +0100 | [diff] [blame] | 5 | * Copyright (C) 2018 Siemens AG |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 6 | * |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but without any warranty; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | /* This file is derived from the flashrom project. */ |
| 19 | #include <stdint.h> |
| 20 | #include <stdlib.h> |
| 21 | #include <string.h> |
David Hendricks | f2612a1 | 2014-04-13 16:27:02 -0700 | [diff] [blame] | 22 | #include <bootstate.h> |
Furquan Shaikh | de705fa | 2017-04-19 19:27:28 -0700 | [diff] [blame] | 23 | #include <commonlib/helpers.h> |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 24 | #include <delay.h> |
| 25 | #include <arch/io.h> |
| 26 | #include <console/console.h> |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 27 | #include <device/pci.h> |
| 28 | #include <spi_flash.h> |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 29 | |
Zheng Bao | 600784e | 2013-02-07 17:30:23 +0800 | [diff] [blame] | 30 | #include <spi-generic.h> |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 31 | |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 32 | #define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */ |
| 33 | #define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF) |
| 34 | #define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */ |
| 35 | #define HSFC_FDBC (0x3f << HSFC_FDBC_OFF) |
| 36 | |
| 37 | |
Duncan Laurie | 181bbdd | 2012-06-23 16:53:57 -0700 | [diff] [blame] | 38 | #ifdef __SMM__ |
Duncan Laurie | 181bbdd | 2012-06-23 16:53:57 -0700 | [diff] [blame] | 39 | #define pci_read_config_byte(dev, reg, targ)\ |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 40 | *(targ) = pci_read_config8(dev, reg) |
Duncan Laurie | 181bbdd | 2012-06-23 16:53:57 -0700 | [diff] [blame] | 41 | #define pci_read_config_word(dev, reg, targ)\ |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 42 | *(targ) = pci_read_config16(dev, reg) |
Duncan Laurie | 181bbdd | 2012-06-23 16:53:57 -0700 | [diff] [blame] | 43 | #define pci_read_config_dword(dev, reg, targ)\ |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 44 | *(targ) = pci_read_config32(dev, reg) |
Duncan Laurie | 181bbdd | 2012-06-23 16:53:57 -0700 | [diff] [blame] | 45 | #define pci_write_config_byte(dev, reg, val)\ |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 46 | pci_write_config8(dev, reg, val) |
Duncan Laurie | 181bbdd | 2012-06-23 16:53:57 -0700 | [diff] [blame] | 47 | #define pci_write_config_word(dev, reg, val)\ |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 48 | pci_write_config16(dev, reg, val) |
Duncan Laurie | 181bbdd | 2012-06-23 16:53:57 -0700 | [diff] [blame] | 49 | #define pci_write_config_dword(dev, reg, val)\ |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 50 | pci_write_config32(dev, reg, val) |
Duncan Laurie | 181bbdd | 2012-06-23 16:53:57 -0700 | [diff] [blame] | 51 | #else /* !__SMM__ */ |
| 52 | #include <device/device.h> |
Duncan Laurie | 181bbdd | 2012-06-23 16:53:57 -0700 | [diff] [blame] | 53 | #define pci_read_config_byte(dev, reg, targ)\ |
| 54 | *(targ) = pci_read_config8(dev, reg) |
| 55 | #define pci_read_config_word(dev, reg, targ)\ |
| 56 | *(targ) = pci_read_config16(dev, reg) |
| 57 | #define pci_read_config_dword(dev, reg, targ)\ |
| 58 | *(targ) = pci_read_config32(dev, reg) |
| 59 | #define pci_write_config_byte(dev, reg, val)\ |
| 60 | pci_write_config8(dev, reg, val) |
| 61 | #define pci_write_config_word(dev, reg, val)\ |
| 62 | pci_write_config16(dev, reg, val) |
| 63 | #define pci_write_config_dword(dev, reg, val)\ |
| 64 | pci_write_config32(dev, reg, val) |
| 65 | #endif /* !__SMM__ */ |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 66 | |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 67 | static int spi_is_multichip(void); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 68 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 69 | typedef struct spi_slave ich_spi_slave; |
| 70 | |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 71 | static int g_ichspi_lock = 0; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 72 | |
| 73 | typedef struct ich7_spi_regs { |
| 74 | uint16_t spis; |
| 75 | uint16_t spic; |
| 76 | uint32_t spia; |
| 77 | uint64_t spid[8]; |
| 78 | uint64_t _pad; |
| 79 | uint32_t bbar; |
| 80 | uint16_t preop; |
| 81 | uint16_t optype; |
| 82 | uint8_t opmenu[8]; |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 83 | uint32_t pbr[3]; |
Stefan Reinauer | 6a00113 | 2017-07-13 02:20:27 +0200 | [diff] [blame] | 84 | } __packed ich7_spi_regs; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 85 | |
| 86 | typedef struct ich9_spi_regs { |
| 87 | uint32_t bfpr; |
| 88 | uint16_t hsfs; |
| 89 | uint16_t hsfc; |
| 90 | uint32_t faddr; |
| 91 | uint32_t _reserved0; |
| 92 | uint32_t fdata[16]; |
| 93 | uint32_t frap; |
| 94 | uint32_t freg[5]; |
| 95 | uint32_t _reserved1[3]; |
| 96 | uint32_t pr[5]; |
| 97 | uint32_t _reserved2[2]; |
| 98 | uint8_t ssfs; |
| 99 | uint8_t ssfc[3]; |
| 100 | uint16_t preop; |
| 101 | uint16_t optype; |
| 102 | uint8_t opmenu[8]; |
| 103 | uint32_t bbar; |
| 104 | uint8_t _reserved3[12]; |
| 105 | uint32_t fdoc; |
| 106 | uint32_t fdod; |
| 107 | uint8_t _reserved4[8]; |
| 108 | uint32_t afc; |
| 109 | uint32_t lvscc; |
| 110 | uint32_t uvscc; |
| 111 | uint8_t _reserved5[4]; |
| 112 | uint32_t fpb; |
| 113 | uint8_t _reserved6[28]; |
| 114 | uint32_t srdl; |
| 115 | uint32_t srdc; |
| 116 | uint32_t srd; |
Stefan Reinauer | 6a00113 | 2017-07-13 02:20:27 +0200 | [diff] [blame] | 117 | } __packed ich9_spi_regs; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 118 | |
| 119 | typedef struct ich_spi_controller { |
| 120 | int locked; |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 121 | uint32_t flmap0; |
Stefan Tauner | 327205d | 2018-08-26 13:53:16 +0200 | [diff] [blame] | 122 | uint32_t flcomp; |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 123 | uint32_t hsfs; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 124 | |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 125 | ich9_spi_regs *ich9_spi; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 126 | uint8_t *opmenu; |
| 127 | int menubytes; |
| 128 | uint16_t *preop; |
| 129 | uint16_t *optype; |
| 130 | uint32_t *addr; |
| 131 | uint8_t *data; |
| 132 | unsigned databytes; |
| 133 | uint8_t *status; |
| 134 | uint16_t *control; |
| 135 | uint32_t *bbar; |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 136 | uint32_t *fpr; |
| 137 | uint8_t fpr_max; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 138 | } ich_spi_controller; |
| 139 | |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 140 | static ich_spi_controller g_cntlr; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 141 | |
| 142 | enum { |
| 143 | SPIS_SCIP = 0x0001, |
| 144 | SPIS_GRANT = 0x0002, |
| 145 | SPIS_CDS = 0x0004, |
| 146 | SPIS_FCERR = 0x0008, |
| 147 | SSFS_AEL = 0x0010, |
| 148 | SPIS_LOCK = 0x8000, |
| 149 | SPIS_RESERVED_MASK = 0x7ff0, |
| 150 | SSFS_RESERVED_MASK = 0x7fe2 |
| 151 | }; |
| 152 | |
| 153 | enum { |
| 154 | SPIC_SCGO = 0x000002, |
| 155 | SPIC_ACS = 0x000004, |
| 156 | SPIC_SPOP = 0x000008, |
| 157 | SPIC_DBC = 0x003f00, |
| 158 | SPIC_DS = 0x004000, |
| 159 | SPIC_SME = 0x008000, |
| 160 | SSFC_SCF_MASK = 0x070000, |
| 161 | SSFC_RESERVED = 0xf80000 |
| 162 | }; |
| 163 | |
| 164 | enum { |
| 165 | HSFS_FDONE = 0x0001, |
| 166 | HSFS_FCERR = 0x0002, |
| 167 | HSFS_AEL = 0x0004, |
| 168 | HSFS_BERASE_MASK = 0x0018, |
| 169 | HSFS_BERASE_SHIFT = 3, |
| 170 | HSFS_SCIP = 0x0020, |
| 171 | HSFS_FDOPSS = 0x2000, |
| 172 | HSFS_FDV = 0x4000, |
| 173 | HSFS_FLOCKDN = 0x8000 |
| 174 | }; |
| 175 | |
| 176 | enum { |
| 177 | HSFC_FGO = 0x0001, |
| 178 | HSFC_FCYCLE_MASK = 0x0006, |
| 179 | HSFC_FCYCLE_SHIFT = 1, |
| 180 | HSFC_FDBC_MASK = 0x3f00, |
| 181 | HSFC_FDBC_SHIFT = 8, |
| 182 | HSFC_FSMIE = 0x8000 |
| 183 | }; |
| 184 | |
| 185 | enum { |
| 186 | SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0, |
| 187 | SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1, |
| 188 | SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2, |
| 189 | SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 |
| 190 | }; |
| 191 | |
Martin Roth | 7a1a3ad | 2017-06-24 21:29:38 -0600 | [diff] [blame] | 192 | #if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 193 | |
| 194 | static u8 readb_(const void *addr) |
| 195 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 196 | u8 v = read8(addr); |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 197 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 198 | printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", |
| 199 | v, ((unsigned) addr & 0xffff) - 0xf020); |
| 200 | return v; |
| 201 | } |
| 202 | |
| 203 | static u16 readw_(const void *addr) |
| 204 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 205 | u16 v = read16(addr); |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 206 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 207 | printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", |
| 208 | v, ((unsigned) addr & 0xffff) - 0xf020); |
| 209 | return v; |
| 210 | } |
| 211 | |
| 212 | static u32 readl_(const void *addr) |
| 213 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 214 | u32 v = read32(addr); |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 215 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 216 | printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", |
| 217 | v, ((unsigned) addr & 0xffff) - 0xf020); |
| 218 | return v; |
| 219 | } |
| 220 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 221 | static void writeb_(u8 b, void *addr) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 222 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 223 | write8(addr, b); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 224 | printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", |
| 225 | b, ((unsigned) addr & 0xffff) - 0xf020); |
| 226 | } |
| 227 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 228 | static void writew_(u16 b, void *addr) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 229 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 230 | write16(addr, b); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 231 | printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", |
| 232 | b, ((unsigned) addr & 0xffff) - 0xf020); |
| 233 | } |
| 234 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 235 | static void writel_(u32 b, void *addr) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 236 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 237 | write32(addr, b); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 238 | printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", |
| 239 | b, ((unsigned) addr & 0xffff) - 0xf020); |
| 240 | } |
| 241 | |
| 242 | #else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ |
| 243 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 244 | #define readb_(a) read8(a) |
| 245 | #define readw_(a) read16(a) |
| 246 | #define readl_(a) read32(a) |
| 247 | #define writeb_(val, addr) write8(addr, val) |
| 248 | #define writew_(val, addr) write16(addr, val) |
| 249 | #define writel_(val, addr) write32(addr, val) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 250 | |
| 251 | #endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */ |
| 252 | |
| 253 | static void write_reg(const void *value, void *dest, uint32_t size) |
| 254 | { |
| 255 | const uint8_t *bvalue = value; |
| 256 | uint8_t *bdest = dest; |
| 257 | |
| 258 | while (size >= 4) { |
| 259 | writel_(*(const uint32_t *)bvalue, bdest); |
| 260 | bdest += 4; bvalue += 4; size -= 4; |
| 261 | } |
| 262 | while (size) { |
| 263 | writeb_(*bvalue, bdest); |
| 264 | bdest++; bvalue++; size--; |
| 265 | } |
| 266 | } |
| 267 | |
| 268 | static void read_reg(const void *src, void *value, uint32_t size) |
| 269 | { |
| 270 | const uint8_t *bsrc = src; |
| 271 | uint8_t *bvalue = value; |
| 272 | |
| 273 | while (size >= 4) { |
| 274 | *(uint32_t *)bvalue = readl_(bsrc); |
| 275 | bsrc += 4; bvalue += 4; size -= 4; |
| 276 | } |
| 277 | while (size) { |
| 278 | *bvalue = readb_(bsrc); |
| 279 | bsrc++; bvalue++; size--; |
| 280 | } |
| 281 | } |
| 282 | |
| 283 | static void ich_set_bbar(uint32_t minaddr) |
| 284 | { |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 285 | ich_spi_controller *cntlr = &g_cntlr; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 286 | const uint32_t bbar_mask = 0x00ffff00; |
| 287 | uint32_t ichspi_bbar; |
| 288 | |
| 289 | minaddr &= bbar_mask; |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 290 | ichspi_bbar = readl_(cntlr->bbar) & ~bbar_mask; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 291 | ichspi_bbar |= minaddr; |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 292 | writel_(ichspi_bbar, cntlr->bbar); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 293 | } |
| 294 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 295 | void spi_init(void) |
| 296 | { |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 297 | ich_spi_controller *cntlr = &g_cntlr; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 298 | uint8_t *rcrb; /* Root Complex Register Block */ |
| 299 | uint32_t rcba; /* Root Complex Base Address */ |
| 300 | uint8_t bios_cntl; |
Vladimir Serbinenko | 42c4a9d | 2014-02-16 17:13:19 +0100 | [diff] [blame] | 301 | ich9_spi_regs *ich9_spi; |
Arthur Heymans | c88e370 | 2017-08-20 20:50:17 +0200 | [diff] [blame] | 302 | ich7_spi_regs *ich7_spi; |
Vladimir Serbinenko | 42c4a9d | 2014-02-16 17:13:19 +0100 | [diff] [blame] | 303 | uint16_t hsfs; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 304 | |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 305 | #ifdef __SIMPLE_DEVICE__ |
Elyes HAOUAS | 68c851b | 2018-06-12 22:06:09 +0200 | [diff] [blame] | 306 | pci_devfn_t dev = PCI_DEV(0, 31, 0); |
Duncan Laurie | 181bbdd | 2012-06-23 16:53:57 -0700 | [diff] [blame] | 307 | #else |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 308 | struct device *dev = pcidev_on_root(31, 0); |
Duncan Laurie | 181bbdd | 2012-06-23 16:53:57 -0700 | [diff] [blame] | 309 | #endif |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 310 | |
| 311 | pci_read_config_dword(dev, 0xf0, &rcba); |
| 312 | /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ |
| 313 | rcrb = (uint8_t *)(rcba & 0xffffc000); |
Arthur Heymans | c88e370 | 2017-08-20 20:50:17 +0200 | [diff] [blame] | 314 | if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)) { |
| 315 | ich7_spi = (ich7_spi_regs *)(rcrb + 0x3020); |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 316 | cntlr->opmenu = ich7_spi->opmenu; |
| 317 | cntlr->menubytes = sizeof(ich7_spi->opmenu); |
| 318 | cntlr->optype = &ich7_spi->optype; |
| 319 | cntlr->addr = &ich7_spi->spia; |
| 320 | cntlr->data = (uint8_t *)ich7_spi->spid; |
| 321 | cntlr->databytes = sizeof(ich7_spi->spid); |
| 322 | cntlr->status = (uint8_t *)&ich7_spi->spis; |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 323 | g_ichspi_lock = readw_(&ich7_spi->spis) & HSFS_FLOCKDN; |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 324 | cntlr->control = &ich7_spi->spic; |
| 325 | cntlr->bbar = &ich7_spi->bbar; |
| 326 | cntlr->preop = &ich7_spi->preop; |
| 327 | cntlr->fpr = &ich7_spi->pbr[0]; |
| 328 | cntlr->fpr_max = 3; |
Arthur Heymans | c88e370 | 2017-08-20 20:50:17 +0200 | [diff] [blame] | 329 | } else { |
| 330 | ich9_spi = (ich9_spi_regs *)(rcrb + 0x3800); |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 331 | cntlr->ich9_spi = ich9_spi; |
Arthur Heymans | c88e370 | 2017-08-20 20:50:17 +0200 | [diff] [blame] | 332 | hsfs = readw_(&ich9_spi->hsfs); |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 333 | g_ichspi_lock = hsfs & HSFS_FLOCKDN; |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 334 | cntlr->hsfs = hsfs; |
| 335 | cntlr->opmenu = ich9_spi->opmenu; |
| 336 | cntlr->menubytes = sizeof(ich9_spi->opmenu); |
| 337 | cntlr->optype = &ich9_spi->optype; |
| 338 | cntlr->addr = &ich9_spi->faddr; |
| 339 | cntlr->data = (uint8_t *)ich9_spi->fdata; |
| 340 | cntlr->databytes = sizeof(ich9_spi->fdata); |
| 341 | cntlr->status = &ich9_spi->ssfs; |
| 342 | cntlr->control = (uint16_t *)ich9_spi->ssfc; |
| 343 | cntlr->bbar = &ich9_spi->bbar; |
| 344 | cntlr->preop = &ich9_spi->preop; |
| 345 | cntlr->fpr = &ich9_spi->pr[0]; |
| 346 | cntlr->fpr_max = 5; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 347 | |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 348 | if (cntlr->hsfs & HSFS_FDV) { |
Patrick Georgi | c88828d | 2018-11-26 10:42:59 +0100 | [diff] [blame] | 349 | writel_(4, &ich9_spi->fdoc); |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 350 | cntlr->flmap0 = readl_(&ich9_spi->fdod); |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 351 | writel_(0x1000, &ich9_spi->fdoc); |
Stefan Tauner | 327205d | 2018-08-26 13:53:16 +0200 | [diff] [blame] | 352 | cntlr->flcomp = readl_(&ich9_spi->fdod); |
Arthur Heymans | c88e370 | 2017-08-20 20:50:17 +0200 | [diff] [blame] | 353 | } |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 354 | } |
| 355 | |
| 356 | ich_set_bbar(0); |
| 357 | |
| 358 | /* Disable the BIOS write protect so write commands are allowed. */ |
| 359 | pci_read_config_byte(dev, 0xdc, &bios_cntl); |
Vladimir Serbinenko | 42c4a9d | 2014-02-16 17:13:19 +0100 | [diff] [blame] | 360 | /* Deassert SMM BIOS Write Protect Disable. */ |
| 361 | bios_cntl &= ~(1 << 5); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 362 | pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1); |
| 363 | } |
Aaron Durbin | 4d3de7e | 2015-09-02 17:34:04 -0500 | [diff] [blame] | 364 | |
David Hendricks | f2612a1 | 2014-04-13 16:27:02 -0700 | [diff] [blame] | 365 | static void spi_init_cb(void *unused) |
| 366 | { |
| 367 | spi_init(); |
| 368 | } |
| 369 | |
Aaron Durbin | 9ef9d85 | 2015-03-16 17:30:09 -0500 | [diff] [blame] | 370 | BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 371 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 372 | typedef struct spi_transaction { |
| 373 | const uint8_t *out; |
| 374 | uint32_t bytesout; |
| 375 | uint8_t *in; |
| 376 | uint32_t bytesin; |
| 377 | uint8_t type; |
| 378 | uint8_t opcode; |
| 379 | uint32_t offset; |
| 380 | } spi_transaction; |
| 381 | |
| 382 | static inline void spi_use_out(spi_transaction *trans, unsigned bytes) |
| 383 | { |
| 384 | trans->out += bytes; |
| 385 | trans->bytesout -= bytes; |
| 386 | } |
| 387 | |
| 388 | static inline void spi_use_in(spi_transaction *trans, unsigned bytes) |
| 389 | { |
| 390 | trans->in += bytes; |
| 391 | trans->bytesin -= bytes; |
| 392 | } |
| 393 | |
| 394 | static void spi_setup_type(spi_transaction *trans) |
| 395 | { |
| 396 | trans->type = 0xFF; |
| 397 | |
| 398 | /* Try to guess spi type from read/write sizes. */ |
| 399 | if (trans->bytesin == 0) { |
| 400 | if (trans->bytesout > 4) |
| 401 | /* |
| 402 | * If bytesin = 0 and bytesout > 4, we presume this is |
| 403 | * a write data operation, which is accompanied by an |
| 404 | * address. |
| 405 | */ |
| 406 | trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; |
| 407 | else |
| 408 | trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; |
| 409 | return; |
| 410 | } |
| 411 | |
| 412 | if (trans->bytesout == 1) { /* and bytesin is > 0 */ |
| 413 | trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; |
| 414 | return; |
| 415 | } |
| 416 | |
| 417 | if (trans->bytesout == 4) { /* and bytesin is > 0 */ |
| 418 | trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; |
| 419 | } |
Duncan Laurie | 23b0053 | 2012-10-10 14:21:23 -0700 | [diff] [blame] | 420 | |
| 421 | /* Fast read command is called with 5 bytes instead of 4 */ |
| 422 | if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { |
| 423 | trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; |
| 424 | --trans->bytesout; |
| 425 | } |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 426 | } |
| 427 | |
| 428 | static int spi_setup_opcode(spi_transaction *trans) |
| 429 | { |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 430 | ich_spi_controller *cntlr = &g_cntlr; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 431 | uint16_t optypes; |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 432 | uint8_t opmenu[cntlr->menubytes]; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 433 | |
| 434 | trans->opcode = trans->out[0]; |
| 435 | spi_use_out(trans, 1); |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 436 | if (!g_ichspi_lock) { |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 437 | /* The lock is off, so just use index 0. */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 438 | writeb_(trans->opcode, cntlr->opmenu); |
| 439 | optypes = readw_(cntlr->optype); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 440 | optypes = (optypes & 0xfffc) | (trans->type & 0x3); |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 441 | writew_(optypes, cntlr->optype); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 442 | return 0; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 443 | } |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 444 | |
| 445 | /* The lock is on. See if what we need is on the menu. */ |
| 446 | uint8_t optype; |
| 447 | uint16_t opcode_index; |
| 448 | |
| 449 | /* Write Enable is handled as atomic prefix */ |
| 450 | if (trans->opcode == SPI_OPCODE_WREN) |
| 451 | return 0; |
| 452 | |
| 453 | read_reg(cntlr->opmenu, opmenu, sizeof(opmenu)); |
| 454 | for (opcode_index = 0; opcode_index < cntlr->menubytes; |
| 455 | opcode_index++) { |
| 456 | if (opmenu[opcode_index] == trans->opcode) |
| 457 | break; |
| 458 | } |
| 459 | |
| 460 | if (opcode_index == cntlr->menubytes) { |
| 461 | printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", |
| 462 | trans->opcode); |
| 463 | return -1; |
| 464 | } |
| 465 | |
| 466 | optypes = readw_(cntlr->optype); |
| 467 | optype = (optypes >> (opcode_index * 2)) & 0x3; |
| 468 | if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && |
| 469 | optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && |
| 470 | trans->bytesout >= 3) { |
| 471 | /* We guessed wrong earlier. Fix it up. */ |
| 472 | trans->type = optype; |
| 473 | } |
| 474 | if (optype != trans->type) { |
| 475 | printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n", |
| 476 | optype); |
| 477 | return -1; |
| 478 | } |
| 479 | return opcode_index; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 480 | } |
| 481 | |
| 482 | static int spi_setup_offset(spi_transaction *trans) |
| 483 | { |
| 484 | /* Separate the SPI address and data. */ |
| 485 | switch (trans->type) { |
| 486 | case SPI_OPCODE_TYPE_READ_NO_ADDRESS: |
| 487 | case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: |
| 488 | return 0; |
| 489 | case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: |
| 490 | case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: |
| 491 | trans->offset = ((uint32_t)trans->out[0] << 16) | |
| 492 | ((uint32_t)trans->out[1] << 8) | |
| 493 | ((uint32_t)trans->out[2] << 0); |
| 494 | spi_use_out(trans, 3); |
| 495 | return 1; |
| 496 | default: |
| 497 | printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", trans->type); |
| 498 | return -1; |
| 499 | } |
| 500 | } |
| 501 | |
| 502 | /* |
Philipp Deppenwiese | 93643e3 | 2014-10-17 16:10:32 +0200 | [diff] [blame] | 503 | * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 504 | * below is True) or 0. In case the wait was for the bit(s) to set - write |
| 505 | * those bits back, which would cause resetting them. |
| 506 | * |
| 507 | * Return the last read status value on success or -1 on failure. |
| 508 | */ |
| 509 | static int ich_status_poll(u16 bitmask, int wait_til_set) |
| 510 | { |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 511 | ich_spi_controller *cntlr = &g_cntlr; |
Philipp Deppenwiese | 93643e3 | 2014-10-17 16:10:32 +0200 | [diff] [blame] | 512 | int timeout = 600000; /* This will result in 6 seconds */ |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 513 | u16 status = 0; |
| 514 | |
| 515 | while (timeout--) { |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 516 | status = readw_(cntlr->status); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 517 | if (wait_til_set ^ ((status & bitmask) == 0)) { |
| 518 | if (wait_til_set) |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 519 | writew_((status & bitmask), cntlr->status); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 520 | return status; |
| 521 | } |
| 522 | udelay(10); |
| 523 | } |
| 524 | |
Philipp Deppenwiese | 93643e3 | 2014-10-17 16:10:32 +0200 | [diff] [blame] | 525 | printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, bitmask %x\n", |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 526 | status, bitmask); |
| 527 | return -1; |
| 528 | } |
| 529 | |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 530 | static int spi_is_multichip(void) |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 531 | { |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 532 | ich_spi_controller *cntlr = &g_cntlr; |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 533 | if (!(cntlr->hsfs & HSFS_FDV)) |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 534 | return 0; |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 535 | return !!((cntlr->flmap0 >> 8) & 3); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 536 | } |
| 537 | |
Furquan Shaikh | 94f8699 | 2016-12-01 07:12:32 -0800 | [diff] [blame] | 538 | static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, |
Furquan Shaikh | 0dba025 | 2016-11-30 04:34:22 -0800 | [diff] [blame] | 539 | size_t bytesout, void *din, size_t bytesin) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 540 | { |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 541 | ich_spi_controller *cntlr = &g_cntlr; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 542 | uint16_t control; |
| 543 | int16_t opcode_index; |
| 544 | int with_address; |
| 545 | int status; |
| 546 | |
| 547 | spi_transaction trans = { |
Gabe Black | 93d9f92 | 2014-03-27 21:52:43 -0700 | [diff] [blame] | 548 | dout, bytesout, |
| 549 | din, bytesin, |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 550 | 0xff, 0xff, 0 |
| 551 | }; |
| 552 | |
| 553 | /* There has to always at least be an opcode. */ |
Gabe Black | 93d9f92 | 2014-03-27 21:52:43 -0700 | [diff] [blame] | 554 | if (!bytesout || !dout) { |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 555 | printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n"); |
| 556 | return -1; |
| 557 | } |
| 558 | /* Make sure if we read something we have a place to put it. */ |
Gabe Black | 93d9f92 | 2014-03-27 21:52:43 -0700 | [diff] [blame] | 559 | if (bytesin != 0 && !din) { |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 560 | printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n"); |
| 561 | return -1; |
| 562 | } |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 563 | |
| 564 | if (ich_status_poll(SPIS_SCIP, 0) == -1) |
| 565 | return -1; |
| 566 | |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 567 | writew_(SPIS_CDS | SPIS_FCERR, cntlr->status); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 568 | |
| 569 | spi_setup_type(&trans); |
| 570 | if ((opcode_index = spi_setup_opcode(&trans)) < 0) |
| 571 | return -1; |
| 572 | if ((with_address = spi_setup_offset(&trans)) < 0) |
| 573 | return -1; |
| 574 | |
Duncan Laurie | 3beb6db | 2012-09-01 13:44:17 -0700 | [diff] [blame] | 575 | if (trans.opcode == SPI_OPCODE_WREN) { |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 576 | /* |
| 577 | * Treat Write Enable as Atomic Pre-Op if possible |
| 578 | * in order to prevent the Management Engine from |
| 579 | * issuing a transaction between WREN and DATA. |
| 580 | */ |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 581 | if (!g_ichspi_lock) |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 582 | writew_(trans.opcode, cntlr->preop); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 583 | return 0; |
| 584 | } |
| 585 | |
| 586 | /* Preset control fields */ |
| 587 | control = SPIC_SCGO | ((opcode_index & 0x07) << 4); |
| 588 | |
| 589 | /* Issue atomic preop cycle if needed */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 590 | if (readw_(cntlr->preop)) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 591 | control |= SPIC_ACS; |
| 592 | |
| 593 | if (!trans.bytesout && !trans.bytesin) { |
Duncan Laurie | 3beb6db | 2012-09-01 13:44:17 -0700 | [diff] [blame] | 594 | /* SPI addresses are 24 bit only */ |
| 595 | if (with_address) |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 596 | writel_(trans.offset & 0x00FFFFFF, cntlr->addr); |
Duncan Laurie | 3beb6db | 2012-09-01 13:44:17 -0700 | [diff] [blame] | 597 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 598 | /* |
| 599 | * This is a 'no data' command (like Write Enable), its |
| 600 | * bitesout size was 1, decremented to zero while executing |
| 601 | * spi_setup_opcode() above. Tell the chip to send the |
| 602 | * command. |
| 603 | */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 604 | writew_(control, cntlr->control); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 605 | |
| 606 | /* wait for the result */ |
| 607 | status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); |
| 608 | if (status == -1) |
| 609 | return -1; |
| 610 | |
| 611 | if (status & SPIS_FCERR) { |
| 612 | printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n"); |
| 613 | return -1; |
| 614 | } |
| 615 | |
Werner Zeh | f13a6f9 | 2018-11-14 10:55:52 +0100 | [diff] [blame] | 616 | goto spi_xfer_exit; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 617 | } |
| 618 | |
| 619 | /* |
Paul Menzel | 9478297 | 2013-06-29 11:41:27 +0200 | [diff] [blame] | 620 | * Check if this is a write command attempting to transfer more bytes |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 621 | * than the controller can handle. Iterations for writes are not |
| 622 | * supported here because each SPI write command needs to be preceded |
| 623 | * and followed by other SPI commands, and this sequence is controlled |
| 624 | * by the SPI chip driver. |
| 625 | */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 626 | if (trans.bytesout > cntlr->databytes) { |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 627 | printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" |
Kyösti Mälkki | 1110495 | 2014-06-29 16:17:33 +0300 | [diff] [blame] | 628 | " spi_crop_chunk()?\n"); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 629 | return -1; |
| 630 | } |
| 631 | |
| 632 | /* |
| 633 | * Read or write up to databytes bytes at a time until everything has |
| 634 | * been sent. |
| 635 | */ |
| 636 | while (trans.bytesout || trans.bytesin) { |
| 637 | uint32_t data_length; |
| 638 | |
| 639 | /* SPI addresses are 24 bit only */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 640 | writel_(trans.offset & 0x00FFFFFF, cntlr->addr); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 641 | |
| 642 | if (trans.bytesout) |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 643 | data_length = min(trans.bytesout, cntlr->databytes); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 644 | else |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 645 | data_length = min(trans.bytesin, cntlr->databytes); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 646 | |
| 647 | /* Program data into FDATA0 to N */ |
| 648 | if (trans.bytesout) { |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 649 | write_reg(trans.out, cntlr->data, data_length); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 650 | spi_use_out(&trans, data_length); |
| 651 | if (with_address) |
| 652 | trans.offset += data_length; |
| 653 | } |
| 654 | |
| 655 | /* Add proper control fields' values */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 656 | control &= ~((cntlr->databytes - 1) << 8); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 657 | control |= SPIC_DS; |
| 658 | control |= (data_length - 1) << 8; |
| 659 | |
| 660 | /* write it */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 661 | writew_(control, cntlr->control); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 662 | |
| 663 | /* Wait for Cycle Done Status or Flash Cycle Error. */ |
| 664 | status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); |
| 665 | if (status == -1) |
| 666 | return -1; |
| 667 | |
| 668 | if (status & SPIS_FCERR) { |
| 669 | printk(BIOS_DEBUG, "ICH SPI: Data transaction error\n"); |
| 670 | return -1; |
| 671 | } |
| 672 | |
| 673 | if (trans.bytesin) { |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 674 | read_reg(cntlr->data, trans.in, data_length); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 675 | spi_use_in(&trans, data_length); |
| 676 | if (with_address) |
| 677 | trans.offset += data_length; |
| 678 | } |
| 679 | } |
| 680 | |
Werner Zeh | f13a6f9 | 2018-11-14 10:55:52 +0100 | [diff] [blame] | 681 | spi_xfer_exit: |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 682 | /* Clear atomic preop now that xfer is done */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 683 | writew_(0, cntlr->preop); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 684 | |
| 685 | return 0; |
| 686 | } |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 687 | |
| 688 | /* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */ |
| 689 | static void ich_hwseq_set_addr(uint32_t addr) |
| 690 | { |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 691 | ich_spi_controller *cntlr = &g_cntlr; |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 692 | uint32_t addr_old = readl_(&cntlr->ich9_spi->faddr) & ~0x01FFFFFF; |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 693 | |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 694 | writel_((addr & 0x01FFFFFF) | addr_old, &cntlr->ich9_spi->faddr); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 695 | } |
| 696 | |
| 697 | /* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals. |
| 698 | Resets all error flags in HSFS. |
| 699 | Returns 0 if the cycle completes successfully without errors within |
| 700 | timeout us, 1 on errors. */ |
| 701 | static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, |
| 702 | unsigned int len) |
| 703 | { |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 704 | ich_spi_controller *cntlr = &g_cntlr; |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 705 | uint16_t hsfs; |
| 706 | uint32_t addr; |
| 707 | |
| 708 | timeout /= 8; /* scale timeout duration to counter */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 709 | while ((((hsfs = readw_(&cntlr->ich9_spi->hsfs)) & |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 710 | (HSFS_FDONE | HSFS_FCERR)) == 0) && |
| 711 | --timeout) { |
| 712 | udelay(8); |
| 713 | } |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 714 | writew_(readw_(&cntlr->ich9_spi->hsfs), &cntlr->ich9_spi->hsfs); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 715 | |
| 716 | if (!timeout) { |
| 717 | uint16_t hsfc; |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 718 | addr = readl_(&cntlr->ich9_spi->faddr) & 0x01FFFFFF; |
| 719 | hsfc = readw_(&cntlr->ich9_spi->hsfc); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 720 | printk(BIOS_ERR, "Transaction timeout between offset 0x%08x and " |
| 721 | "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n", |
| 722 | addr, addr + len - 1, addr, len - 1, |
| 723 | hsfc, hsfs); |
| 724 | return 1; |
| 725 | } |
| 726 | |
| 727 | if (hsfs & HSFS_FCERR) { |
| 728 | uint16_t hsfc; |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 729 | addr = readl_(&cntlr->ich9_spi->faddr) & 0x01FFFFFF; |
| 730 | hsfc = readw_(&cntlr->ich9_spi->hsfc); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 731 | printk(BIOS_ERR, "Transaction error between offset 0x%08x and " |
| 732 | "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n", |
| 733 | addr, addr + len - 1, addr, len - 1, |
| 734 | hsfc, hsfs); |
| 735 | return 1; |
| 736 | } |
| 737 | return 0; |
| 738 | } |
| 739 | |
| 740 | |
Furquan Shaikh | c28984d | 2016-11-20 21:04:00 -0800 | [diff] [blame] | 741 | static int ich_hwseq_erase(const struct spi_flash *flash, u32 offset, |
| 742 | size_t len) |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 743 | { |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 744 | ich_spi_controller *cntlr = &g_cntlr; |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 745 | u32 start, end, erase_size; |
| 746 | int ret; |
| 747 | uint16_t hsfc; |
| 748 | uint16_t timeout = 1000 * 60; |
| 749 | |
| 750 | erase_size = flash->sector_size; |
| 751 | if (offset % erase_size || len % erase_size) { |
| 752 | printk(BIOS_ERR, "SF: Erase offset/length not multiple of erase size\n"); |
| 753 | return -1; |
| 754 | } |
| 755 | |
Furquan Shaikh | 810e2cd | 2016-12-05 20:32:24 -0800 | [diff] [blame] | 756 | ret = spi_claim_bus(&flash->spi); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 757 | if (ret) { |
| 758 | printk(BIOS_ERR, "SF: Unable to claim SPI bus\n"); |
| 759 | return ret; |
| 760 | } |
| 761 | |
| 762 | start = offset; |
| 763 | end = start + len; |
| 764 | |
| 765 | while (offset < end) { |
| 766 | /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 767 | writew_(readw_(&cntlr->ich9_spi->hsfs), &cntlr->ich9_spi->hsfs); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 768 | |
| 769 | ich_hwseq_set_addr(offset); |
| 770 | |
| 771 | offset += erase_size; |
| 772 | |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 773 | hsfc = readw_(&cntlr->ich9_spi->hsfc); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 774 | hsfc &= ~HSFC_FCYCLE; /* clear operation */ |
| 775 | hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ |
| 776 | hsfc |= HSFC_FGO; /* start */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 777 | writew_(hsfc, &cntlr->ich9_spi->hsfc); |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 778 | if (ich_hwseq_wait_for_cycle_complete(timeout, len)) { |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 779 | printk(BIOS_ERR, "SF: Erase failed at %x\n", offset - erase_size); |
| 780 | ret = -1; |
| 781 | goto out; |
| 782 | } |
| 783 | } |
| 784 | |
| 785 | printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x\n", len, start); |
| 786 | |
| 787 | out: |
Furquan Shaikh | 810e2cd | 2016-12-05 20:32:24 -0800 | [diff] [blame] | 788 | spi_release_bus(&flash->spi); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 789 | return ret; |
| 790 | } |
| 791 | |
| 792 | static void ich_read_data(uint8_t *data, int len) |
| 793 | { |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 794 | ich_spi_controller *cntlr = &g_cntlr; |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 795 | int i; |
| 796 | uint32_t temp32 = 0; |
| 797 | |
| 798 | for (i = 0; i < len; i++) { |
| 799 | if ((i % 4) == 0) |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 800 | temp32 = readl_(cntlr->data + i); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 801 | |
| 802 | data[i] = (temp32 >> ((i % 4) * 8)) & 0xff; |
| 803 | } |
| 804 | } |
| 805 | |
Furquan Shaikh | c28984d | 2016-11-20 21:04:00 -0800 | [diff] [blame] | 806 | static int ich_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len, |
| 807 | void *buf) |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 808 | { |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 809 | ich_spi_controller *cntlr = &g_cntlr; |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 810 | uint16_t hsfc; |
| 811 | uint16_t timeout = 100 * 60; |
| 812 | uint8_t block_len; |
| 813 | |
| 814 | if (addr + len > flash->size) { |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 815 | printk(BIOS_ERR, |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 816 | "Attempt to read %x-%x which is out of chip\n", |
| 817 | (unsigned) addr, |
| 818 | (unsigned) addr+(unsigned) len); |
| 819 | return -1; |
| 820 | } |
| 821 | |
| 822 | /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 823 | writew_(readw_(&cntlr->ich9_spi->hsfs), &cntlr->ich9_spi->hsfs); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 824 | |
| 825 | while (len > 0) { |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 826 | block_len = min(len, cntlr->databytes); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 827 | if (block_len > (~addr & 0xff)) |
| 828 | block_len = (~addr & 0xff) + 1; |
| 829 | ich_hwseq_set_addr(addr); |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 830 | hsfc = readw_(&cntlr->ich9_spi->hsfc); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 831 | hsfc &= ~HSFC_FCYCLE; /* set read operation */ |
| 832 | hsfc &= ~HSFC_FDBC; /* clear byte count */ |
| 833 | /* set byte count */ |
| 834 | hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); |
| 835 | hsfc |= HSFC_FGO; /* start */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 836 | writew_(hsfc, &cntlr->ich9_spi->hsfc); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 837 | |
| 838 | if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) |
| 839 | return 1; |
| 840 | ich_read_data(buf, block_len); |
| 841 | addr += block_len; |
| 842 | buf += block_len; |
| 843 | len -= block_len; |
| 844 | } |
| 845 | return 0; |
| 846 | } |
| 847 | |
| 848 | /* Fill len bytes from the data array into the fdata/spid registers. |
| 849 | * |
| 850 | * Note that using len > flash->pgm->spi.max_data_write will trash the registers |
| 851 | * following the data registers. |
| 852 | */ |
| 853 | static void ich_fill_data(const uint8_t *data, int len) |
| 854 | { |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 855 | ich_spi_controller *cntlr = &g_cntlr; |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 856 | uint32_t temp32 = 0; |
| 857 | int i; |
| 858 | |
| 859 | if (len <= 0) |
| 860 | return; |
| 861 | |
| 862 | for (i = 0; i < len; i++) { |
| 863 | if ((i % 4) == 0) |
| 864 | temp32 = 0; |
| 865 | |
| 866 | temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8); |
| 867 | |
| 868 | if ((i % 4) == 3) /* 32 bits are full, write them to regs. */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 869 | writel_(temp32, cntlr->data + (i - (i % 4))); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 870 | } |
| 871 | i--; |
| 872 | if ((i % 4) != 3) /* Write remaining data to regs. */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 873 | writel_(temp32, cntlr->data + (i - (i % 4))); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 874 | } |
| 875 | |
Furquan Shaikh | c28984d | 2016-11-20 21:04:00 -0800 | [diff] [blame] | 876 | static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len, |
| 877 | const void *buf) |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 878 | { |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 879 | ich_spi_controller *cntlr = &g_cntlr; |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 880 | uint16_t hsfc; |
| 881 | uint16_t timeout = 100 * 60; |
| 882 | uint8_t block_len; |
| 883 | uint32_t start = addr; |
| 884 | |
| 885 | if (addr + len > flash->size) { |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 886 | printk(BIOS_ERR, |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 887 | "Attempt to write 0x%x-0x%x which is out of chip\n", |
| 888 | (unsigned)addr, (unsigned) (addr+len)); |
| 889 | return -1; |
| 890 | } |
| 891 | |
| 892 | /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 893 | writew_(readw_(&cntlr->ich9_spi->hsfs), &cntlr->ich9_spi->hsfs); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 894 | |
| 895 | while (len > 0) { |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 896 | block_len = min(len, cntlr->databytes); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 897 | if (block_len > (~addr & 0xff)) |
| 898 | block_len = (~addr & 0xff) + 1; |
| 899 | |
| 900 | ich_hwseq_set_addr(addr); |
| 901 | |
| 902 | ich_fill_data(buf, block_len); |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 903 | hsfc = readw_(&cntlr->ich9_spi->hsfc); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 904 | hsfc &= ~HSFC_FCYCLE; /* clear operation */ |
| 905 | hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */ |
| 906 | hsfc &= ~HSFC_FDBC; /* clear byte count */ |
| 907 | /* set byte count */ |
| 908 | hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); |
| 909 | hsfc |= HSFC_FGO; /* start */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 910 | writew_(hsfc, &cntlr->ich9_spi->hsfc); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 911 | |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 912 | if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) { |
| 913 | printk(BIOS_ERR, "SF: write failure at %x\n", |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 914 | addr); |
| 915 | return -1; |
| 916 | } |
| 917 | addr += block_len; |
| 918 | buf += block_len; |
| 919 | len -= block_len; |
| 920 | } |
| 921 | printk(BIOS_DEBUG, "SF: Successfully written %u bytes @ %#x\n", |
| 922 | (unsigned) (addr - start), start); |
| 923 | return 0; |
| 924 | } |
| 925 | |
Furquan Shaikh | e2fc5e2 | 2017-05-17 17:26:01 -0700 | [diff] [blame] | 926 | static const struct spi_flash_ops spi_flash_ops = { |
| 927 | .read = ich_hwseq_read, |
| 928 | .write = ich_hwseq_write, |
| 929 | .erase = ich_hwseq_erase, |
| 930 | }; |
| 931 | |
Furquan Shaikh | a149157 | 2017-05-17 19:14:06 -0700 | [diff] [blame] | 932 | static int spi_flash_programmer_probe(const struct spi_slave *spi, |
| 933 | struct spi_flash *flash) |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 934 | { |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 935 | ich_spi_controller *cntlr = &g_cntlr; |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 936 | |
Arthur Heymans | c88e370 | 2017-08-20 20:50:17 +0200 | [diff] [blame] | 937 | if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)) |
| 938 | return spi_flash_generic_probe(spi, flash); |
| 939 | |
Furquan Shaikh | a149157 | 2017-05-17 19:14:06 -0700 | [diff] [blame] | 940 | /* Try generic probing first if spi_is_multichip returns 0. */ |
| 941 | if (!spi_is_multichip() && !spi_flash_generic_probe(spi, flash)) |
| 942 | return 0; |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 943 | |
Furquan Shaikh | 810e2cd | 2016-12-05 20:32:24 -0800 | [diff] [blame] | 944 | memcpy(&flash->spi, spi, sizeof(*spi)); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 945 | flash->name = "Opaque HW-sequencing"; |
| 946 | |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 947 | ich_hwseq_set_addr(0); |
| 948 | switch ((cntlr->hsfs >> 3) & 3) { |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 949 | case 0: |
| 950 | flash->sector_size = 256; |
| 951 | break; |
| 952 | case 1: |
| 953 | flash->sector_size = 4096; |
| 954 | break; |
| 955 | case 2: |
| 956 | flash->sector_size = 8192; |
| 957 | break; |
| 958 | case 3: |
| 959 | flash->sector_size = 65536; |
| 960 | break; |
| 961 | } |
| 962 | |
Stefan Tauner | 327205d | 2018-08-26 13:53:16 +0200 | [diff] [blame] | 963 | flash->size = 1 << (19 + (cntlr->flcomp & 7)); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 964 | |
Furquan Shaikh | e2fc5e2 | 2017-05-17 17:26:01 -0700 | [diff] [blame] | 965 | flash->ops = &spi_flash_ops; |
| 966 | |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 967 | if ((cntlr->hsfs & HSFS_FDV) && ((cntlr->flmap0 >> 8) & 3)) |
Stefan Tauner | 327205d | 2018-08-26 13:53:16 +0200 | [diff] [blame] | 968 | flash->size += 1 << (19 + ((cntlr->flcomp >> 3) & 7)); |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 969 | printk(BIOS_DEBUG, "flash size 0x%x bytes\n", flash->size); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 970 | |
Furquan Shaikh | 30221b4 | 2017-05-15 14:35:15 -0700 | [diff] [blame] | 971 | return 0; |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 972 | } |
Furquan Shaikh | a149157 | 2017-05-17 19:14:06 -0700 | [diff] [blame] | 973 | |
Aaron Durbin | 851dde8 | 2018-04-19 21:15:25 -0600 | [diff] [blame] | 974 | static int xfer_vectors(const struct spi_slave *slave, |
| 975 | struct spi_op vectors[], size_t count) |
| 976 | { |
| 977 | return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); |
| 978 | } |
| 979 | |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 980 | #define SPI_FPR_SHIFT 12 |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 981 | #define ICH7_SPI_FPR_MASK 0xfff |
| 982 | #define ICH9_SPI_FPR_MASK 0x1fff |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 983 | #define SPI_FPR_BASE_SHIFT 0 |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 984 | #define ICH7_SPI_FPR_LIMIT_SHIFT 12 |
| 985 | #define ICH9_SPI_FPR_LIMIT_SHIFT 16 |
| 986 | #define ICH9_SPI_FPR_RPE (1 << 15) /* Read Protect */ |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 987 | #define SPI_FPR_WPE (1 << 31) /* Write Protect */ |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 988 | |
| 989 | static u32 spi_fpr(u32 base, u32 limit) |
| 990 | { |
| 991 | u32 ret; |
| 992 | u32 mask, limit_shift; |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 993 | |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 994 | if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)) { |
| 995 | mask = ICH7_SPI_FPR_MASK; |
| 996 | limit_shift = ICH7_SPI_FPR_LIMIT_SHIFT; |
| 997 | } else { |
| 998 | mask = ICH9_SPI_FPR_MASK; |
| 999 | limit_shift = ICH9_SPI_FPR_LIMIT_SHIFT; |
| 1000 | } |
| 1001 | ret = ((limit >> SPI_FPR_SHIFT) & mask) << limit_shift; |
| 1002 | ret |= ((base >> SPI_FPR_SHIFT) & mask) << SPI_FPR_BASE_SHIFT; |
| 1003 | return ret; |
| 1004 | } |
| 1005 | |
| 1006 | /* |
| 1007 | * Protect range of SPI flash defined by [start, start+size-1] using Flash |
| 1008 | * Protected Range (FPR) register if available. |
| 1009 | * Returns 0 on success, -1 on failure of programming fpr registers. |
| 1010 | */ |
| 1011 | static int spi_flash_protect(const struct spi_flash *flash, |
Rizwan Qureshi | f9f5093 | 2018-12-31 15:19:16 +0530 | [diff] [blame] | 1012 | const struct region *region, |
| 1013 | const enum ctrlr_prot_type type) |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 1014 | { |
Arthur Heymans | f751aee | 2018-12-29 13:35:26 +0100 | [diff] [blame] | 1015 | ich_spi_controller *cntlr = &g_cntlr; |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 1016 | u32 start = region_offset(region); |
| 1017 | u32 end = start + region_sz(region) - 1; |
| 1018 | u32 reg; |
Rizwan Qureshi | f9f5093 | 2018-12-31 15:19:16 +0530 | [diff] [blame] | 1019 | u32 protect_mask = 0; |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 1020 | int fpr; |
| 1021 | uint32_t *fpr_base; |
| 1022 | |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 1023 | fpr_base = cntlr->fpr; |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 1024 | |
| 1025 | /* Find first empty FPR */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 1026 | for (fpr = 0; fpr < cntlr->fpr_max; fpr++) { |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 1027 | reg = read32(&fpr_base[fpr]); |
| 1028 | if (reg == 0) |
| 1029 | break; |
| 1030 | } |
| 1031 | |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 1032 | if (fpr == cntlr->fpr_max) { |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 1033 | printk(BIOS_ERR, "ERROR: No SPI FPR free!\n"); |
| 1034 | return -1; |
| 1035 | } |
| 1036 | |
Rizwan Qureshi | f9f5093 | 2018-12-31 15:19:16 +0530 | [diff] [blame] | 1037 | switch (type) { |
| 1038 | case WRITE_PROTECT: |
| 1039 | protect_mask |= SPI_FPR_WPE; |
| 1040 | break; |
| 1041 | case READ_PROTECT: |
| 1042 | if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)) |
| 1043 | return -1; |
| 1044 | protect_mask |= ICH9_SPI_FPR_RPE; |
| 1045 | break; |
| 1046 | case READ_WRITE_PROTECT: |
| 1047 | if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)) |
| 1048 | return -1; |
| 1049 | protect_mask |= (ICH9_SPI_FPR_RPE | SPI_FPR_WPE); |
| 1050 | break; |
| 1051 | default: |
| 1052 | printk(BIOS_ERR, "ERROR: Seeking invalid protection!\n"); |
| 1053 | return -1; |
| 1054 | } |
| 1055 | |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 1056 | /* Set protected range base and limit */ |
Rizwan Qureshi | f9f5093 | 2018-12-31 15:19:16 +0530 | [diff] [blame] | 1057 | reg = spi_fpr(start, end) | protect_mask; |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 1058 | |
| 1059 | /* Set the FPR register and verify it is protected */ |
| 1060 | write32(&fpr_base[fpr], reg); |
| 1061 | reg = read32(&fpr_base[fpr]); |
Rizwan Qureshi | f9f5093 | 2018-12-31 15:19:16 +0530 | [diff] [blame] | 1062 | if (!(reg & protect_mask)) { |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 1063 | printk(BIOS_ERR, "ERROR: Unable to set SPI FPR %d\n", fpr); |
| 1064 | return -1; |
| 1065 | } |
| 1066 | |
| 1067 | printk(BIOS_INFO, "%s: FPR %d is enabled for range 0x%08x-0x%08x\n", |
| 1068 | __func__, fpr, start, end); |
| 1069 | return 0; |
| 1070 | } |
| 1071 | |
Furquan Shaikh | a149157 | 2017-05-17 19:14:06 -0700 | [diff] [blame] | 1072 | static const struct spi_ctrlr spi_ctrlr = { |
Aaron Durbin | 851dde8 | 2018-04-19 21:15:25 -0600 | [diff] [blame] | 1073 | .xfer_vector = xfer_vectors, |
Furquan Shaikh | a149157 | 2017-05-17 19:14:06 -0700 | [diff] [blame] | 1074 | .max_xfer_size = member_size(ich9_spi_regs, fdata), |
| 1075 | .flash_probe = spi_flash_programmer_probe, |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 1076 | .flash_protect = spi_flash_protect, |
Furquan Shaikh | a149157 | 2017-05-17 19:14:06 -0700 | [diff] [blame] | 1077 | }; |
| 1078 | |
Furquan Shaikh | 2cd03f1 | 2017-05-18 14:58:32 -0700 | [diff] [blame] | 1079 | const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { |
| 1080 | { |
| 1081 | .ctrlr = &spi_ctrlr, |
| 1082 | .bus_start = 0, |
| 1083 | .bus_end = 0, |
| 1084 | }, |
| 1085 | }; |
| 1086 | |
| 1087 | const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); |