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Patrick Georgiafd4c872020-05-05 23:43:18 +02001/* Memory information */
Patrick Georgiac959032020-05-05 22:49:26 +02002/* SPDX-License-Identifier: GPL-2.0-only */
Kane Chen33faac62014-07-27 12:54:44 -07003
4#ifndef _MEMORY_INFO_H_
5#define _MEMORY_INFO_H_
6
Barnali Sarkarc16d3892017-02-23 16:56:54 +05307#include <stdint.h>
8
Raul E Rangel99f54a62018-04-11 10:58:14 -06009#define DIMM_INFO_SERIAL_SIZE 4
Aaron Durbin4b6f2622018-10-09 07:31:24 -060010#define DIMM_INFO_PART_NUMBER_SIZE 33
Johnny Lind8740c32022-05-04 15:16:16 +080011#define DIMM_INFO_TOTAL 32
Richard Spiegelbd654802018-02-22 10:03:39 -070012
Raul E Rangel5041e9b2018-03-20 12:37:27 -060013/**
Kane Chen33faac62014-07-27 12:54:44 -070014 * If this table is filled and put in CBMEM,
15 * then these info in CBMEM will be used to generate smbios type 17 table
Raul E Rangel5041e9b2018-03-20 12:37:27 -060016 *
17 * Values are specified according to the JEDEC SPD Standard.
Kane Chen33faac62014-07-27 12:54:44 -070018 */
19struct dimm_info {
Raul E Rangel5041e9b2018-03-20 12:37:27 -060020 /*
21 * Size of the module in MiB.
22 */
Kane Chen33faac62014-07-27 12:54:44 -070023 uint32_t dimm_size;
Raul E Rangel5041e9b2018-03-20 12:37:27 -060024 /*
25 * SMBIOS (not SPD) device type.
26 *
Elyes HAOUAS28114ae2018-11-14 17:51:00 +010027 * See the smbios.h smbios_memory_type enum.
Raul E Rangel5041e9b2018-03-20 12:37:27 -060028 */
Kane Chen33faac62014-07-27 12:54:44 -070029 uint16_t ddr_type;
Rob Barnes327f1052020-09-01 10:26:57 -060030 /*
31 * ddr_frequency is deprecated.
32 * Use max_speed_mts and configured_speed_mts instead.
33 */
Kane Chen33faac62014-07-27 12:54:44 -070034 uint16_t ddr_frequency;
35 uint8_t rank_per_dimm;
David Milosevic6be82a42022-10-18 19:17:19 +020036 /*
37 * Memory-Controller-ID
38 */
39 uint8_t ctrlr_num;
40 /*
41 * Channel-ID
42 */
Kane Chen33faac62014-07-27 12:54:44 -070043 uint8_t channel_num;
David Milosevic6be82a42022-10-18 19:17:19 +020044 /*
45 * DIMM-ID
46 */
Kane Chen33faac62014-07-27 12:54:44 -070047 uint8_t dimm_num;
48 uint8_t bank_locator;
Raul E Rangel5041e9b2018-03-20 12:37:27 -060049 /*
Raul E Rangel99f54a62018-04-11 10:58:14 -060050 * SPD serial number.
Raul E Rangel5041e9b2018-03-20 12:37:27 -060051 */
Richard Spiegelbd654802018-02-22 10:03:39 -070052 uint8_t serial[DIMM_INFO_SERIAL_SIZE];
Raul E Rangel5041e9b2018-03-20 12:37:27 -060053 /*
54 * The last byte is '\0' for the end of string
55 *
56 * Must contain only printable ASCII.
57 */
Richard Spiegelbd654802018-02-22 10:03:39 -070058 uint8_t module_part_number[DIMM_INFO_PART_NUMBER_SIZE];
Raul E Rangel5041e9b2018-03-20 12:37:27 -060059 /*
60 * SPD Manufacturer ID
61 */
Kane Chen33faac62014-07-27 12:54:44 -070062 uint16_t mod_id;
Raul E Rangel5041e9b2018-03-20 12:37:27 -060063 /*
64 * SPD Module Type.
65 *
66 * See spd.h for valid values.
67 *
68 * e.g., SPD_RDIMM, SPD_SODIMM, SPD_MICRO_DIMM
69 */
Kane Chen33faac62014-07-27 12:54:44 -070070 uint8_t mod_type;
Raul E Rangel5041e9b2018-03-20 12:37:27 -060071 /*
72 * SPD bus width.
73 *
74 * Bits 0 - 2 encode the primary bus width:
75 * 0b000 = 8 bit width
76 * 0b001 = 16 bit width
77 * 0b010 = 32 bit width
78 * 0b011 = 64 bit width
79 *
80 * Bits 3 - 4 encode the extension bits (ECC):
81 * 0b00 = 0 extension bits
82 * 0b01 = 8 bit of ECC
83 *
84 * e.g.,
85 * 64 bit bus with 8 bits of ECC (72 bits total): 0b1011
86 * 64 bit bus with 0 bits of ECC (64 bits total): 0b0011
87 *
88 * See the smbios.h smbios_memory_bus_width enum.
89 */
Kane Chen33faac62014-07-27 12:54:44 -070090 uint8_t bus_width;
Christian Walterf9723222019-05-28 10:37:24 +020091 /*
92 * Voltage Level
93 */
94 uint16_t vdd_voltage;
Rob Barnes327f1052020-09-01 10:26:57 -060095 /*
96 * Max speed in MT/s
97 * If the value is 0, ddr_frequency should be used instead.
98 */
99 uint16_t max_speed_mts;
100 /*
101 * Configured speed in MT/s
102 * If the value is 0, ddr_frequency should be used instead.
103 */
104 uint16_t configured_speed_mts;
Stefan Reinauer6a001132017-07-13 02:20:27 +0200105} __packed;
Kane Chen33faac62014-07-27 12:54:44 -0700106
107struct memory_info {
Angel Pons6724ba42021-01-31 15:06:59 +0100108 /*
109 * SMBIOS error correction type.
110 * See the smbios.h smbios_memory_array_ecc enum.
111 */
112 uint8_t ecc_type;
Patrick Rudolph5e007802020-07-27 15:37:43 +0200113 /* Maximum capacity the DRAM controller/mainboard supports */
114 uint32_t max_capacity_mib;
115 /* Maximum number of DIMMs the DRAM controller/mainboard supports */
116 uint16_t number_of_devices;
117
118 /* active DIMM configuration */
Kane Chen33faac62014-07-27 12:54:44 -0700119 uint8_t dimm_cnt;
Richard Spiegelbd654802018-02-22 10:03:39 -0700120 struct dimm_info dimm[DIMM_INFO_TOTAL];
Stefan Reinauer6a001132017-07-13 02:20:27 +0200121} __packed;
Kane Chen33faac62014-07-27 12:54:44 -0700122
Nick Vaccaro3b24bb62020-09-30 13:05:09 -0700123/*
124 * mainboard_get_dram_part_num returns a DRAM part number override string
125 * return NULL = no part number override provided by mainboard
126 * return non-NULL = pointer to a string terminating in '\0'
127 */
128const char *mainboard_get_dram_part_num(void);
Kane Chen33faac62014-07-27 12:54:44 -0700129#endif