Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Google Inc. |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 5 | * Copyright (C) 2015 Intel Corporation. |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <arch/io.h> |
| 18 | #include <bootstate.h> |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 19 | #include <chip.h> |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 20 | #include <console/console.h> |
| 21 | #include <console/post_codes.h> |
| 22 | #include <cpu/x86/smm.h> |
Subrata Banik | e7ceae7 | 2017-03-08 17:59:40 +0530 | [diff] [blame] | 23 | #include <device/pci.h> |
Ravi Sarawadi | 1483d1f | 2017-09-28 17:06:01 -0700 | [diff] [blame] | 24 | #include <intelblocks/lpc_lib.h> |
Subrata Banik | c51df93 | 2018-05-08 11:58:01 +0530 | [diff] [blame] | 25 | #include <intelblocks/p2sb.h> |
Subrata Banik | e7ceae7 | 2017-03-08 17:59:40 +0530 | [diff] [blame] | 26 | #include <intelblocks/pcr.h> |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 27 | #include <reg_script.h> |
| 28 | #include <spi-generic.h> |
Dhaval Sharma | 9dca83c | 2016-01-18 17:28:20 +0530 | [diff] [blame] | 29 | #include <soc/me.h> |
Rizwan Qureshi | cf73c13 | 2016-08-04 20:01:12 +0530 | [diff] [blame] | 30 | #include <soc/p2sb.h> |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 31 | #include <soc/pci_devs.h> |
Subrata Banik | e7ceae7 | 2017-03-08 17:59:40 +0530 | [diff] [blame] | 32 | #include <soc/pcr_ids.h> |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 33 | #include <soc/pm.h> |
Barnali Sarkar | 0dddcd7 | 2016-08-02 17:49:56 +0530 | [diff] [blame] | 34 | #include <soc/smbus.h> |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 35 | #include <soc/systemagent.h> |
Subrata Banik | 771d611 | 2017-11-29 16:17:13 +0530 | [diff] [blame] | 36 | #include <soc/thermal.h> |
Barnali Sarkar | 7146445 | 2017-03-31 18:11:49 +0530 | [diff] [blame] | 37 | #include <stdlib.h> |
Subrata Banik | e7ceae7 | 2017-03-08 17:59:40 +0530 | [diff] [blame] | 38 | |
Subrata Banik | e7ceae7 | 2017-03-08 17:59:40 +0530 | [diff] [blame] | 39 | #define PSF_BASE_ADDRESS 0xA00 |
| 40 | #define PCR_PSFX_T0_SHDW_PCIEN 0x1C |
| 41 | #define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8) |
Archana Patni | 7846e34 | 2015-11-11 01:29:23 +0530 | [diff] [blame] | 42 | |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame^] | 43 | static void disable_sideband_access(void) |
Archana Patni | 7846e34 | 2015-11-11 01:29:23 +0530 | [diff] [blame] | 44 | { |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame^] | 45 | p2sb_disable_sideband_access(); |
Barnali Sarkar | fbf1018 | 2017-08-11 18:38:38 +0530 | [diff] [blame] | 46 | |
| 47 | /* hide p2sb device */ |
Subrata Banik | c51df93 | 2018-05-08 11:58:01 +0530 | [diff] [blame] | 48 | p2sb_hide(); |
Barnali Sarkar | fbf1018 | 2017-08-11 18:38:38 +0530 | [diff] [blame] | 49 | } |
| 50 | |
| 51 | static void pch_disable_heci(void) |
| 52 | { |
Archana Patni | 7846e34 | 2015-11-11 01:29:23 +0530 | [diff] [blame] | 53 | /* unhide p2sb device */ |
Subrata Banik | c51df93 | 2018-05-08 11:58:01 +0530 | [diff] [blame] | 54 | p2sb_unhide(); |
Archana Patni | 7846e34 | 2015-11-11 01:29:23 +0530 | [diff] [blame] | 55 | |
| 56 | /* disable heci */ |
Subrata Banik | e7ceae7 | 2017-03-08 17:59:40 +0530 | [diff] [blame] | 57 | pcr_or32(PID_PSF1, PSF_BASE_ADDRESS + PCR_PSFX_T0_SHDW_PCIEN, |
| 58 | PCR_PSFX_T0_SHDW_PCIEN_FUNDIS); |
Archana Patni | 7846e34 | 2015-11-11 01:29:23 +0530 | [diff] [blame] | 59 | |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame^] | 60 | disable_sideband_access(); |
Archana Patni | 7846e34 | 2015-11-11 01:29:23 +0530 | [diff] [blame] | 61 | } |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 62 | |
Subrata Banik | c51df93 | 2018-05-08 11:58:01 +0530 | [diff] [blame] | 63 | static void pch_finalize_script(struct device *dev) |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 64 | { |
Barnali Sarkar | 7146445 | 2017-03-31 18:11:49 +0530 | [diff] [blame] | 65 | uint32_t reg32; |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 66 | uint8_t *pmcbase; |
Archana Patni | 7846e34 | 2015-11-11 01:29:23 +0530 | [diff] [blame] | 67 | config_t *config; |
Archana Patni | 6c1bf27 | 2015-12-18 23:38:21 +0530 | [diff] [blame] | 68 | u8 reg8; |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 69 | |
Dhaval Sharma | 9dca83c | 2016-01-18 17:28:20 +0530 | [diff] [blame] | 70 | /* Display me status before we hide it */ |
| 71 | intel_me_status(); |
| 72 | |
Subrata Banik | 639bf8a | 2017-08-25 12:08:59 +0530 | [diff] [blame] | 73 | pmcbase = pmc_mmio_regs(); |
Archana Patni | 7846e34 | 2015-11-11 01:29:23 +0530 | [diff] [blame] | 74 | config = dev->chip_info; |
Archana Patni | 6c1bf27 | 2015-12-18 23:38:21 +0530 | [diff] [blame] | 75 | |
| 76 | /* |
Subrata Banik | 771d611 | 2017-11-29 16:17:13 +0530 | [diff] [blame] | 77 | * Set low maximum temp value used for dynamic thermal sensor |
| 78 | * shutdown consideration. |
| 79 | * |
| 80 | * If Dynamic Thermal Shutdown is enabled then PMC logic shuts down the |
| 81 | * thermal sensor when CPU is in a C-state and DTS Temp <= LTT. |
| 82 | */ |
| 83 | pch_thermal_configuration(); |
| 84 | |
| 85 | /* |
Archana Patni | 6c1bf27 | 2015-12-18 23:38:21 +0530 | [diff] [blame] | 86 | * Disable ACPI PM timer based on dt policy |
| 87 | * |
| 88 | * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. |
| 89 | * Disabling ACPI PM timer also switches off TCO |
| 90 | */ |
| 91 | |
| 92 | if (config->PmTimerDisabled) { |
| 93 | reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); |
| 94 | reg8 |= (1 << 1); |
| 95 | write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); |
| 96 | } |
| 97 | |
Naresh G Solanki | c261c4b | 2017-04-25 12:09:07 +0530 | [diff] [blame] | 98 | /* Disable XTAL shutdown qualification for low power idle. */ |
| 99 | if (config->s0ix_enable) { |
| 100 | reg32 = read32(pmcbase + CIR31C); |
| 101 | reg32 |= XTALSDQDIS; |
| 102 | write32(pmcbase + CIR31C, reg32); |
| 103 | } |
| 104 | |
Archana Patni | 6c1bf27 | 2015-12-18 23:38:21 +0530 | [diff] [blame] | 105 | /* we should disable Heci1 based on the devicetree policy */ |
Archana Patni | 7846e34 | 2015-11-11 01:29:23 +0530 | [diff] [blame] | 106 | if (config->HeciEnabled == 0) |
| 107 | pch_disable_heci(); |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 108 | } |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 109 | |
Subrata Banik | c51df93 | 2018-05-08 11:58:01 +0530 | [diff] [blame] | 110 | static void soc_lockdown(struct device *dev) |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 111 | { |
Barnali Sarkar | 0818a2a | 2017-08-17 11:52:39 +0530 | [diff] [blame] | 112 | struct soc_intel_skylake_config *config; |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 113 | u8 reg8; |
Barnali Sarkar | 0818a2a | 2017-08-17 11:52:39 +0530 | [diff] [blame] | 114 | |
Barnali Sarkar | 0818a2a | 2017-08-17 11:52:39 +0530 | [diff] [blame] | 115 | config = dev->chip_info; |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 116 | |
| 117 | /* Global SMI Lock */ |
| 118 | if (config->LockDownConfigGlobalSmi == 0) { |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 119 | reg8 = pci_read_config8(dev, GEN_PMCON_A); |
| 120 | reg8 |= SMI_LOCK; |
| 121 | pci_write_config8(dev, GEN_PMCON_A, reg8); |
| 122 | } |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 123 | } |
| 124 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 125 | static void soc_finalize(void *unused) |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 126 | { |
Subrata Banik | c51df93 | 2018-05-08 11:58:01 +0530 | [diff] [blame] | 127 | struct device *dev; |
| 128 | |
| 129 | dev = PCH_DEV_PMC; |
| 130 | |
| 131 | /* Check if PMC is enabled, else return */ |
| 132 | if (dev == NULL || dev->chip_info == NULL) |
| 133 | return; |
| 134 | |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 135 | printk(BIOS_DEBUG, "Finalizing chipset.\n"); |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 136 | |
Subrata Banik | c51df93 | 2018-05-08 11:58:01 +0530 | [diff] [blame] | 137 | pch_finalize_script(dev); |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 138 | |
Subrata Banik | c51df93 | 2018-05-08 11:58:01 +0530 | [diff] [blame] | 139 | soc_lockdown(dev); |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 140 | |
Duncan Laurie | 6f0e6fa | 2016-02-09 09:40:39 -0800 | [diff] [blame] | 141 | printk(BIOS_DEBUG, "Finalizing SMM.\n"); |
| 142 | outb(APM_CNT_FINALIZE, APM_CNT); |
| 143 | |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 144 | /* Indicate finalize step with post code */ |
| 145 | post_code(POST_OS_BOOT); |
| 146 | } |
| 147 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 148 | BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL); |
| 149 | BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL); |