soc/intel/skylake: Move PMC lock down config after resource allocation
This patch to ensures that coreboot is performing PMC
registers lockdown after PCI enumeration is done.
This requirements are intended to support platform security
guideline where all required chipset registers are expected
to be in lock down stage before launching any 3rd party
code as in option rom etc.
coreboot has to change its execution order to meet those
requirements. Hence PMC register lock down has been moved
right after pci resource allocation is done, so that
PMC registers can be lock down before calling post pci
enumeration FSP NotifyPhase() API which is targeted to
be done in BS_DEV_ENABLE-BS_ON_ENTRY.
TEST=Ensure PMC MMIO register 0xC4 bit 31 is set.
Change-Id: Ibd86a38fa78752ce007da63a9ccdd991ca21ab92
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index 2fb37caa9d..c79f2ac 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -111,7 +111,6 @@
u16 tcocnt;
uint8_t *pmcbase;
config_t *config;
- u32 pmsyncreg;
u8 reg8;
/* Set FAST_SPI opcode menu */
@@ -120,22 +119,17 @@
/* Lock FAST_SPIBAR */
fast_spi_lock_bar();
- /*TCO Lock down */
+ /* TCO Lock down */
tcobase = smbus_tco_regs();
tcocnt = inw(tcobase + TCO1_CNT);
tcocnt |= TCO_LOCK;
outw(tcocnt, tcobase + TCO1_CNT);
- /* PMSYNC */
- pmcbase = pmc_mmio_regs();
- pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG);
- pmsyncreg |= PMSYNC_LOCK;
- write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);
-
/* Display me status before we hide it */
intel_me_status();
dev = PCH_DEV_PMC;
+ pmcbase = pmc_mmio_regs();
config = dev->chip_info;
/*