Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Google Inc. |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 5 | * Copyright (C) 2015 Intel Corporation. |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <arch/io.h> |
| 18 | #include <bootstate.h> |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 19 | #include <chip.h> |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 20 | #include <console/console.h> |
| 21 | #include <console/post_codes.h> |
| 22 | #include <cpu/x86/smm.h> |
Subrata Banik | e7ceae7 | 2017-03-08 17:59:40 +0530 | [diff] [blame] | 23 | #include <device/pci.h> |
Barnali Sarkar | 7146445 | 2017-03-31 18:11:49 +0530 | [diff] [blame] | 24 | #include <intelblocks/fast_spi.h> |
Subrata Banik | e7ceae7 | 2017-03-08 17:59:40 +0530 | [diff] [blame] | 25 | #include <intelblocks/pcr.h> |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 26 | #include <reg_script.h> |
| 27 | #include <spi-generic.h> |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 28 | #include <soc/lpc.h> |
Dhaval Sharma | 9dca83c | 2016-01-18 17:28:20 +0530 | [diff] [blame] | 29 | #include <soc/me.h> |
Rizwan Qureshi | cf73c13 | 2016-08-04 20:01:12 +0530 | [diff] [blame] | 30 | #include <soc/p2sb.h> |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 31 | #include <soc/pci_devs.h> |
Subrata Banik | e7ceae7 | 2017-03-08 17:59:40 +0530 | [diff] [blame] | 32 | #include <soc/pcr_ids.h> |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 33 | #include <soc/pm.h> |
Barnali Sarkar | 0dddcd7 | 2016-08-02 17:49:56 +0530 | [diff] [blame] | 34 | #include <soc/smbus.h> |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 35 | #include <soc/systemagent.h> |
Barnali Sarkar | 7146445 | 2017-03-31 18:11:49 +0530 | [diff] [blame] | 36 | #include <stdlib.h> |
Subrata Banik | e7ceae7 | 2017-03-08 17:59:40 +0530 | [diff] [blame] | 37 | |
| 38 | #define PCR_DMI_GCS 0x274C |
| 39 | #define PCR_DMI_GCS_BILD (1 << 0) |
| 40 | #define PSF_BASE_ADDRESS 0xA00 |
| 41 | #define PCR_PSFX_T0_SHDW_PCIEN 0x1C |
| 42 | #define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8) |
Archana Patni | 7846e34 | 2015-11-11 01:29:23 +0530 | [diff] [blame] | 43 | |
Archana Patni | 7846e34 | 2015-11-11 01:29:23 +0530 | [diff] [blame] | 44 | static void pch_configure_endpoints(device_t dev, int epmask_id, uint32_t mask) |
| 45 | { |
| 46 | uint32_t reg32; |
| 47 | |
| 48 | reg32 = pci_read_config32(dev, PCH_P2SB_EPMASK(epmask_id)); |
| 49 | pci_write_config32(dev, PCH_P2SB_EPMASK(epmask_id), reg32 | mask); |
| 50 | } |
| 51 | |
Barnali Sarkar | fbf1018 | 2017-08-11 18:38:38 +0530 | [diff] [blame] | 52 | static void disable_sideband_access(void) |
Archana Patni | 7846e34 | 2015-11-11 01:29:23 +0530 | [diff] [blame] | 53 | { |
| 54 | device_t dev; |
| 55 | u8 reg8; |
| 56 | uint32_t mask; |
| 57 | |
| 58 | dev = PCH_DEV_P2SB; |
| 59 | |
| 60 | /* |
Barnali Sarkar | fbf1018 | 2017-08-11 18:38:38 +0530 | [diff] [blame] | 61 | * Set p2sb PCI offset EPMASK5 C4h [29, 28, 27, 26] to disable Sideband |
| 62 | * access for PCI Root Bridge. |
| 63 | * Set p2sb PCI offset EPMASK5 C4h [17, 16,10, 1] to disable Sideband |
| 64 | * access for MIPI controller. |
| 65 | */ |
| 66 | mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26) | (1 << 17) | |
| 67 | (1 << 16) | (1 << 10) | (1 << 1); |
| 68 | pch_configure_endpoints(dev, 5, mask); |
| 69 | |
| 70 | /* |
| 71 | * Set p2sb PCI offset EPMASK7 CCh ports E6, E5 (bits 6, 5) |
| 72 | * to disable Sideband access for XHCI controller. |
| 73 | */ |
| 74 | mask = (1 << 6) | (1 << 5); |
| 75 | pch_configure_endpoints(dev, 7, mask); |
| 76 | |
| 77 | /* Set the "Endpoint Mask Lock!", P2SB PCI offset E2h bit[1] to 1. */ |
| 78 | reg8 = pci_read_config8(dev, PCH_P2SB_E0 + 2); |
| 79 | pci_write_config8(dev, PCH_P2SB_E0 + 2, reg8 | (1 << 1)); |
| 80 | |
| 81 | /* hide p2sb device */ |
| 82 | pci_write_config8(dev, PCH_P2SB_E0 + 1, 1); |
| 83 | } |
| 84 | |
| 85 | static void pch_disable_heci(void) |
| 86 | { |
| 87 | device_t dev = PCH_DEV_P2SB; |
| 88 | |
| 89 | /* |
Archana Patni | 7846e34 | 2015-11-11 01:29:23 +0530 | [diff] [blame] | 90 | * if p2sb device 1f.1 is not present or hidden in devicetree |
| 91 | * p2sb device becomes NULL |
| 92 | */ |
| 93 | if (!dev) |
| 94 | return; |
| 95 | |
| 96 | /* unhide p2sb device */ |
| 97 | pci_write_config8(dev, PCH_P2SB_E0 + 1, 0); |
| 98 | |
| 99 | /* disable heci */ |
Subrata Banik | e7ceae7 | 2017-03-08 17:59:40 +0530 | [diff] [blame] | 100 | pcr_or32(PID_PSF1, PSF_BASE_ADDRESS + PCR_PSFX_T0_SHDW_PCIEN, |
| 101 | PCR_PSFX_T0_SHDW_PCIEN_FUNDIS); |
Archana Patni | 7846e34 | 2015-11-11 01:29:23 +0530 | [diff] [blame] | 102 | |
Barnali Sarkar | fbf1018 | 2017-08-11 18:38:38 +0530 | [diff] [blame] | 103 | disable_sideband_access(); |
Archana Patni | 7846e34 | 2015-11-11 01:29:23 +0530 | [diff] [blame] | 104 | } |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 105 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 106 | static void pch_finalize_script(void) |
| 107 | { |
| 108 | device_t dev; |
Barnali Sarkar | 7146445 | 2017-03-31 18:11:49 +0530 | [diff] [blame] | 109 | uint32_t reg32; |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 110 | u16 tcobase; |
| 111 | u16 tcocnt; |
| 112 | uint8_t *pmcbase; |
Archana Patni | 7846e34 | 2015-11-11 01:29:23 +0530 | [diff] [blame] | 113 | config_t *config; |
Archana Patni | 6c1bf27 | 2015-12-18 23:38:21 +0530 | [diff] [blame] | 114 | u8 reg8; |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 115 | |
Barnali Sarkar | 7146445 | 2017-03-31 18:11:49 +0530 | [diff] [blame] | 116 | /* Set FAST_SPI opcode menu */ |
| 117 | fast_spi_set_opcode_menu(); |
| 118 | |
| 119 | /* Lock FAST_SPIBAR */ |
| 120 | fast_spi_lock_bar(); |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 121 | |
Subrata Banik | 639bf8a | 2017-08-25 12:08:59 +0530 | [diff] [blame^] | 122 | /* TCO Lock down */ |
Barnali Sarkar | 49eca13 | 2016-08-12 00:05:27 +0530 | [diff] [blame] | 123 | tcobase = smbus_tco_regs(); |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 124 | tcocnt = inw(tcobase + TCO1_CNT); |
| 125 | tcocnt |= TCO_LOCK; |
| 126 | outw(tcocnt, tcobase + TCO1_CNT); |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 127 | |
Dhaval Sharma | 9dca83c | 2016-01-18 17:28:20 +0530 | [diff] [blame] | 128 | /* Display me status before we hide it */ |
| 129 | intel_me_status(); |
| 130 | |
Subrata Banik | 84f428f | 2017-08-25 11:54:10 +0530 | [diff] [blame] | 131 | dev = PCH_DEV_PMC; |
Subrata Banik | 639bf8a | 2017-08-25 12:08:59 +0530 | [diff] [blame^] | 132 | pmcbase = pmc_mmio_regs(); |
Archana Patni | 7846e34 | 2015-11-11 01:29:23 +0530 | [diff] [blame] | 133 | config = dev->chip_info; |
Archana Patni | 6c1bf27 | 2015-12-18 23:38:21 +0530 | [diff] [blame] | 134 | |
| 135 | /* |
| 136 | * Disable ACPI PM timer based on dt policy |
| 137 | * |
| 138 | * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. |
| 139 | * Disabling ACPI PM timer also switches off TCO |
| 140 | */ |
| 141 | |
| 142 | if (config->PmTimerDisabled) { |
| 143 | reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); |
| 144 | reg8 |= (1 << 1); |
| 145 | write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); |
| 146 | } |
| 147 | |
Naresh G Solanki | c261c4b | 2017-04-25 12:09:07 +0530 | [diff] [blame] | 148 | /* Disable XTAL shutdown qualification for low power idle. */ |
| 149 | if (config->s0ix_enable) { |
| 150 | reg32 = read32(pmcbase + CIR31C); |
| 151 | reg32 |= XTALSDQDIS; |
| 152 | write32(pmcbase + CIR31C, reg32); |
| 153 | } |
| 154 | |
Archana Patni | 6c1bf27 | 2015-12-18 23:38:21 +0530 | [diff] [blame] | 155 | /* we should disable Heci1 based on the devicetree policy */ |
Archana Patni | 7846e34 | 2015-11-11 01:29:23 +0530 | [diff] [blame] | 156 | if (config->HeciEnabled == 0) |
| 157 | pch_disable_heci(); |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 158 | } |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 159 | |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 160 | static void soc_lockdown(void) |
| 161 | { |
| 162 | u8 reg8; |
| 163 | device_t dev; |
| 164 | const struct device *dev1 = dev_find_slot(0, PCH_DEVFN_LPC); |
| 165 | const struct soc_intel_skylake_config *config = dev1->chip_info; |
| 166 | |
| 167 | /* Global SMI Lock */ |
| 168 | if (config->LockDownConfigGlobalSmi == 0) { |
| 169 | dev = PCH_DEV_PMC; |
| 170 | reg8 = pci_read_config8(dev, GEN_PMCON_A); |
| 171 | reg8 |= SMI_LOCK; |
| 172 | pci_write_config8(dev, GEN_PMCON_A, reg8); |
| 173 | } |
| 174 | |
Subrata Banik | c204aaa | 2017-08-17 15:49:58 +0530 | [diff] [blame] | 175 | if (config->chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { |
| 176 | /* Bios Interface Lock */ |
Barnali Sarkar | 7146445 | 2017-03-31 18:11:49 +0530 | [diff] [blame] | 177 | fast_spi_set_bios_interface_lock_down(); |
| 178 | |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 179 | /* GCS reg of DMI */ |
Subrata Banik | e7ceae7 | 2017-03-08 17:59:40 +0530 | [diff] [blame] | 180 | pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD); |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 181 | |
Subrata Banik | c204aaa | 2017-08-17 15:49:58 +0530 | [diff] [blame] | 182 | /* Bios Lock */ |
Barnali Sarkar | 7146445 | 2017-03-31 18:11:49 +0530 | [diff] [blame] | 183 | fast_spi_set_lock_enable(); |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 184 | } |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 185 | } |
| 186 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 187 | static void soc_finalize(void *unused) |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 188 | { |
| 189 | printk(BIOS_DEBUG, "Finalizing chipset.\n"); |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 190 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 191 | pch_finalize_script(); |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 192 | |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 193 | soc_lockdown(); |
| 194 | |
Duncan Laurie | 6f0e6fa | 2016-02-09 09:40:39 -0800 | [diff] [blame] | 195 | printk(BIOS_DEBUG, "Finalizing SMM.\n"); |
| 196 | outb(APM_CNT_FINALIZE, APM_CNT); |
| 197 | |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 198 | /* Indicate finalize step with post code */ |
| 199 | post_code(POST_OS_BOOT); |
| 200 | } |
| 201 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 202 | BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL); |
| 203 | BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL); |