Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <stdint.h> |
| 22 | #include <string.h> |
| 23 | #include <lib.h> |
| 24 | #include <timestamp.h> |
Hung-Te Lin | e29e2ff | 2013-01-18 16:50:25 +0800 | [diff] [blame] | 25 | #include <arch/byteorder.h> |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 26 | #include <arch/io.h> |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 27 | #include <device/pci_def.h> |
| 28 | #include <device/pnp_def.h> |
| 29 | #include <cpu/x86/lapic.h> |
| 30 | #include <pc80/mc146818rtc.h> |
Kyösti Mälkki | 6722f8d | 2014-06-16 09:14:49 +0300 | [diff] [blame] | 31 | #include <arch/acpi.h> |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 32 | #include <cbmem.h> |
| 33 | #include <console/console.h> |
Kyösti Mälkki | e3ddee0 | 2014-05-03 10:45:28 +0300 | [diff] [blame] | 34 | #include <bootmode.h> |
Edward O'Callaghan | 1b3acb1 | 2014-06-01 18:04:05 +1000 | [diff] [blame] | 35 | #include <superio/ite/common/ite.h> |
| 36 | #include <superio/ite/it8772f/it8772f.h> |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 37 | #include "northbridge/intel/sandybridge/sandybridge.h" |
| 38 | #include "northbridge/intel/sandybridge/raminit.h" |
| 39 | #include "southbridge/intel/bd82x6x/pch.h" |
| 40 | #include "southbridge/intel/bd82x6x/gpio.h" |
| 41 | #include <arch/cpu.h> |
| 42 | #include <cpu/x86/bist.h> |
| 43 | #include <cpu/x86/msr.h> |
Patrick Georgi | bd79c5e | 2014-11-28 22:35:36 +0100 | [diff] [blame] | 44 | #include <halt.h> |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 45 | #include "gpio.h" |
Kyösti Mälkki | afa7b13 | 2014-02-13 17:16:22 +0200 | [diff] [blame] | 46 | #if CONFIG_DRIVERS_UART_8250IO |
Edward O'Callaghan | 74834e0 | 2015-01-04 04:17:35 +1100 | [diff] [blame] | 47 | #include <superio/smsc/lpc47n207/lpc47n207.h> |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 48 | #endif |
| 49 | #if CONFIG_CHROMEOS |
| 50 | #include <vendorcode/google/chromeos/chromeos.h> |
| 51 | #endif |
| 52 | |
| 53 | /* Stumpy USB Reset Disable defined in cmos.layout */ |
| 54 | #if CONFIG_USE_OPTION_TABLE |
| 55 | #include "option_table.h" |
| 56 | #define CMOS_USB_RESET_DISABLE (CMOS_VSTART_stumpy_usb_reset_disable >> 3) |
| 57 | #else |
| 58 | #define CMOS_USB_RESET_DISABLE (400 >> 3) |
| 59 | #endif |
| 60 | #define USB_RESET_DISABLE_MAGIC (0xdd) /* Disable if set to this */ |
| 61 | |
Edward O'Callaghan | 1f9653a | 2014-07-14 16:31:25 +1000 | [diff] [blame] | 62 | #define DUMMY_DEV PNP_DEV(0x2e, 0) |
Edward O'Callaghan | 1b3acb1 | 2014-06-01 18:04:05 +1000 | [diff] [blame] | 63 | #define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1) |
| 64 | #define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO) |
| 65 | |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 66 | static void pch_enable_lpc(void) |
| 67 | { |
| 68 | /* Set COM1/COM2 decode range */ |
| 69 | pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); |
| 70 | |
Kyösti Mälkki | afa7b13 | 2014-02-13 17:16:22 +0200 | [diff] [blame] | 71 | #if CONFIG_DRIVERS_UART_8250IO |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 72 | /* Enable SuperIO + PS/2 Keyboard/Mouse + COM1 + lpc47n207 config*/ |
| 73 | pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN |\ |
| 74 | CNF2_LPC_EN | COMA_LPC_EN); |
| 75 | |
| 76 | /* map full 256 bytes at 0x1600 to the LPC bus */ |
| 77 | pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0xfc1601); |
| 78 | |
| 79 | try_enabling_LPC47N207_uart(); |
| 80 | #else |
| 81 | /* Enable SuperIO + PS/2 Keyboard/Mouse */ |
| 82 | pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN); |
| 83 | #endif |
| 84 | } |
| 85 | |
| 86 | static void rcba_config(void) |
| 87 | { |
| 88 | u32 reg32; |
| 89 | |
Vladimir Serbinenko | 33b535f | 2014-10-19 10:13:14 +0200 | [diff] [blame] | 90 | southbridge_configure_default_intmap(); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 91 | |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 92 | /* Disable unused devices (board specific) */ |
| 93 | reg32 = RCBA32(FD); |
| 94 | reg32 |= PCH_DISABLE_ALWAYS; |
| 95 | RCBA32(FD) = reg32; |
| 96 | } |
| 97 | |
| 98 | static void early_pch_init(void) |
| 99 | { |
| 100 | u8 reg8; |
| 101 | |
| 102 | // reset rtc power status |
| 103 | reg8 = pci_read_config8(PCH_LPC_DEV, 0xa4); |
| 104 | reg8 &= ~(1 << 2); |
| 105 | pci_write_config8(PCH_LPC_DEV, 0xa4, reg8); |
| 106 | } |
| 107 | |
| 108 | static void setup_sio_gpios(void) |
| 109 | { |
| 110 | /* |
| 111 | * GPIO10 as USBPWRON12# |
| 112 | * GPIO12 as USBPWRON13# |
| 113 | */ |
Edward O'Callaghan | 1f9653a | 2014-07-14 16:31:25 +1000 | [diff] [blame] | 114 | it8772f_gpio_setup(DUMMY_DEV, 1, 0x05, 0x05, 0x00, 0x05, 0x05); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 115 | |
| 116 | /* |
| 117 | * GPIO22 as wake SCI# |
| 118 | */ |
Edward O'Callaghan | 1f9653a | 2014-07-14 16:31:25 +1000 | [diff] [blame] | 119 | it8772f_gpio_setup(DUMMY_DEV, 2, 0x04, 0x04, 0x00, 0x04, 0x04); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 120 | |
| 121 | /* |
| 122 | * GPIO32 as EXTSMI# |
| 123 | */ |
Edward O'Callaghan | 1f9653a | 2014-07-14 16:31:25 +1000 | [diff] [blame] | 124 | it8772f_gpio_setup(DUMMY_DEV, 3, 0x04, 0x04, 0x00, 0x04, 0x04); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 125 | |
| 126 | /* |
| 127 | * GPIO45 as LED_POWER# |
| 128 | */ |
Edward O'Callaghan | 1f9653a | 2014-07-14 16:31:25 +1000 | [diff] [blame] | 129 | it8772f_gpio_setup(DUMMY_DEV, 4, 0x20, 0x20, 0x20, 0x20, 0x20); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 130 | |
| 131 | /* |
| 132 | * GPIO51 as USBPWRON8# |
| 133 | * GPIO52 as USBPWRON1# |
| 134 | */ |
Edward O'Callaghan | 1f9653a | 2014-07-14 16:31:25 +1000 | [diff] [blame] | 135 | it8772f_gpio_setup(DUMMY_DEV, 5, 0x06, 0x06, 0x00, 0x06, 0x06); |
| 136 | it8772f_gpio_setup(DUMMY_DEV, 6, 0x00, 0x00, 0x00, 0x00, 0x00); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 137 | } |
| 138 | |
Aaron Durbin | a0a3727 | 2014-08-14 08:35:11 -0500 | [diff] [blame] | 139 | #include <cpu/intel/romstage.h> |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 140 | void main(unsigned long bist) |
| 141 | { |
| 142 | int boot_mode = 0; |
| 143 | int cbmem_was_initted; |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 144 | |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 145 | struct pei_data pei_data = { |
Edward O'Callaghan | b27d360 | 2014-05-24 02:40:31 +1000 | [diff] [blame] | 146 | .pei_version = PEI_VERSION, |
| 147 | .mchbar = DEFAULT_MCHBAR, |
| 148 | .dmibar = DEFAULT_DMIBAR, |
| 149 | .epbar = DEFAULT_EPBAR, |
| 150 | .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, |
| 151 | .smbusbar = SMBUS_IO_BASE, |
| 152 | .wdbbar = 0x4000000, |
| 153 | .wdbsize = 0x1000, |
| 154 | .hpet_address = CONFIG_HPET_ADDRESS, |
| 155 | .rcba = DEFAULT_RCBABASE, |
| 156 | .pmbase = DEFAULT_PMBASE, |
| 157 | .gpiobase = DEFAULT_GPIOBASE, |
| 158 | .thermalbase = 0xfed08000, |
| 159 | .system_type = 0, // 0 Mobile, 1 Desktop/Server |
| 160 | .tseg_size = CONFIG_SMM_TSEG_SIZE, |
| 161 | .spd_addresses = { 0xa0, 0x00,0xa4,0x00 }, |
| 162 | .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, |
| 163 | .ec_present = 0, |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 164 | // 0 = leave channel enabled |
| 165 | // 1 = disable dimm 0 on channel |
| 166 | // 2 = disable dimm 1 on channel |
| 167 | // 3 = disable dimm 0+1 on channel |
Edward O'Callaghan | b27d360 | 2014-05-24 02:40:31 +1000 | [diff] [blame] | 168 | .dimm_channel0_disabled = 2, |
| 169 | .dimm_channel1_disabled = 2, |
| 170 | .max_ddr3_freq = 1333, |
| 171 | .usb_port_config = { |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 172 | { 1, 0, 0x0080 }, /* P0: Front port (OC0) */ |
| 173 | { 1, 1, 0x0040 }, /* P1: Back port (OC1) */ |
| 174 | { 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */ |
| 175 | { 1, 0, 0x0040 }, /* P3: MMC (no OC) */ |
| 176 | { 1, 2, 0x0080 }, /* P4: Front port (OC2) */ |
| 177 | { 0, 0, 0x0000 }, /* P5: Empty */ |
| 178 | { 0, 0, 0x0000 }, /* P6: Empty */ |
| 179 | { 0, 0, 0x0000 }, /* P7: Empty */ |
| 180 | { 1, 4, 0x0040 }, /* P8: Back port (OC4) */ |
| 181 | { 1, 4, 0x0040 }, /* P9: MINIPCIE3 (no OC) */ |
| 182 | { 1, 4, 0x0040 }, /* P10: BLUETOOTH (no OC) */ |
| 183 | { 0, 4, 0x0000 }, /* P11: Empty */ |
| 184 | { 1, 6, 0x0040 }, /* P12: Back port (OC6) */ |
| 185 | { 1, 5, 0x0040 }, /* P13: Back port (OC5) */ |
| 186 | }, |
| 187 | }; |
| 188 | |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 189 | timestamp_init(get_initial_timestamp()); |
| 190 | timestamp_add_now(TS_START_ROMSTAGE); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 191 | |
| 192 | if (bist == 0) |
| 193 | enable_lapic(); |
| 194 | |
| 195 | pch_enable_lpc(); |
| 196 | |
| 197 | /* Enable GPIOs */ |
| 198 | pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); |
| 199 | pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); |
| 200 | setup_pch_gpios(&stumpy_gpio_map); |
| 201 | setup_sio_gpios(); |
| 202 | |
| 203 | /* Early SuperIO setup */ |
Edward O'Callaghan | 1f9653a | 2014-07-14 16:31:25 +1000 | [diff] [blame] | 204 | it8772f_ac_resume_southbridge(DUMMY_DEV); |
Edward O'Callaghan | 1b3acb1 | 2014-06-01 18:04:05 +1000 | [diff] [blame] | 205 | ite_kill_watchdog(GPIO_DEV); |
| 206 | ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 207 | console_init(); |
| 208 | |
Kyösti Mälkki | e3ddee0 | 2014-05-03 10:45:28 +0300 | [diff] [blame] | 209 | init_bootmode_straps(); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 210 | |
| 211 | /* Halt if there was a built in self test failure */ |
| 212 | report_bist_failure(bist); |
| 213 | |
| 214 | if (MCHBAR16(SSKPD) == 0xCAFE) { |
| 215 | printk(BIOS_DEBUG, "soft reset detected\n"); |
| 216 | boot_mode = 1; |
| 217 | |
| 218 | /* System is not happy after keyboard reset... */ |
| 219 | printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); |
| 220 | outb(0x6, 0xcf9); |
Patrick Georgi | bd79c5e | 2014-11-28 22:35:36 +0100 | [diff] [blame] | 221 | halt(); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 222 | } |
| 223 | |
| 224 | /* Perform some early chipset initialization required |
| 225 | * before RAM initialization can work |
| 226 | */ |
| 227 | sandybridge_early_initialization(SANDYBRIDGE_MOBILE); |
| 228 | printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); |
| 229 | |
Vladimir Serbinenko | 332f14b | 2014-09-05 16:29:41 +0200 | [diff] [blame] | 230 | boot_mode = southbridge_detect_s3_resume() ? 2 : 0; |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 231 | |
| 232 | post_code(0x38); |
| 233 | /* Enable SPD ROMs and DDR-III DRAM */ |
| 234 | enable_smbus(); |
| 235 | |
| 236 | /* Prepare USB controller early in S3 resume */ |
| 237 | if (boot_mode == 2) { |
| 238 | /* |
| 239 | * For Stumpy the back USB ports are reset on resume |
| 240 | * so default to resetting the controller to make the |
| 241 | * kernel happy. There is a CMOS flag to disable the |
| 242 | * controller reset in case the kernel can tolerate |
| 243 | * the device power loss better in the future. |
| 244 | */ |
| 245 | u8 magic = cmos_read(CMOS_USB_RESET_DISABLE); |
| 246 | |
| 247 | if (magic == USB_RESET_DISABLE_MAGIC) { |
| 248 | printk(BIOS_DEBUG, "USB Controller Reset Disabled\n"); |
| 249 | enable_usb_bar(); |
| 250 | } else { |
| 251 | printk(BIOS_DEBUG, "USB Controller Reset Enabled\n"); |
| 252 | } |
| 253 | } else { |
| 254 | /* Ensure USB reset on resume is enabled at boot */ |
| 255 | cmos_write(0, CMOS_USB_RESET_DISABLE); |
| 256 | } |
| 257 | |
| 258 | post_code(0x39); |
| 259 | pei_data.boot_mode = boot_mode; |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 260 | timestamp_add_now(TS_BEFORE_INITRAM); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 261 | sdram_initialize(&pei_data); |
| 262 | |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 263 | timestamp_add_now(TS_AFTER_INITRAM); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 264 | post_code(0x3a); |
| 265 | /* Perform some initialization that must run before stage2 */ |
| 266 | early_pch_init(); |
| 267 | post_code(0x3b); |
| 268 | |
| 269 | rcba_config(); |
| 270 | post_code(0x3c); |
| 271 | |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 272 | quick_ram_check(); |
Stefan Reinauer | afcaac2 | 2012-06-18 15:43:50 -0700 | [diff] [blame] | 273 | post_code(0x3e); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 274 | |
Kyösti Mälkki | 2d8520b | 2014-01-06 17:20:31 +0200 | [diff] [blame] | 275 | cbmem_was_initted = !cbmem_recovery(boot_mode==2); |
Kyösti Mälkki | 7893848 | 2014-01-04 11:02:45 +0200 | [diff] [blame] | 276 | if (boot_mode!=2) |
| 277 | save_mrc_data(&pei_data); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 278 | |
Vladimir Serbinenko | c845b43 | 2014-09-05 03:37:44 +0200 | [diff] [blame] | 279 | if (boot_mode==2 && !cbmem_was_initted) { |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 280 | /* Failed S3 resume, reset to come up cleanly */ |
| 281 | outb(0x6, 0xcf9); |
Patrick Georgi | bd79c5e | 2014-11-28 22:35:36 +0100 | [diff] [blame] | 282 | halt(); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 283 | } |
Vladimir Serbinenko | c845b43 | 2014-09-05 03:37:44 +0200 | [diff] [blame] | 284 | northbridge_romstage_finalize(boot_mode==2); |
| 285 | |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 286 | post_code(0x3f); |
| 287 | #if CONFIG_CHROMEOS |
| 288 | init_chromeos(boot_mode); |
| 289 | #endif |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 290 | timestamp_add_now(TS_END_ROMSTAGE); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 291 | } |