Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2012 The Linux Foundation. All rights reserved. |
| 3 | * Source : APQ8064 LK boot |
| 4 | * |
| 5 | * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. |
| 6 | * |
| 7 | * Redistribution and use in source and binary forms, with or without |
| 8 | * modification, are permitted provided that the following conditions |
| 9 | * are met: |
| 10 | * * Redistributions of source code must retain the above copyright |
| 11 | * notice, this list of conditions and the following disclaimer. |
| 12 | * * Redistributions in binary form must reproduce the above copyright |
| 13 | * notice, this list of conditions and the following disclaimer in |
| 14 | * the documentation and/or other materials provided with the |
| 15 | * distribution. |
| 16 | * * Neither the name of Google, Inc. nor the names of its contributors |
| 17 | * may be used to endorse or promote products derived from this |
| 18 | * software without specific prior written permission. |
| 19 | * |
| 20 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 21 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 22 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 23 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
| 24 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 25 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
| 26 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
| 27 | * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
| 28 | * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| 29 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT |
| 30 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 31 | * SUCH DAMAGE. |
| 32 | */ |
| 33 | |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 34 | #include <arch/io.h> |
| 35 | #include <boot/coreboot_tables.h> |
| 36 | #include <console/console.h> |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 37 | #include <console/uart.h> |
Julius Werner | 73d1ed6 | 2014-10-20 13:20:49 -0700 | [diff] [blame] | 38 | #include <delay.h> |
Julius Werner | eaa9c45 | 2014-09-24 15:40:49 -0700 | [diff] [blame] | 39 | #include <gpio.h> |
Julius Werner | 73d1ed6 | 2014-10-20 13:20:49 -0700 | [diff] [blame] | 40 | #include <soc/clock.h> |
Julius Werner | 73d1ed6 | 2014-10-20 13:20:49 -0700 | [diff] [blame] | 41 | #include <soc/gsbi.h> |
| 42 | #include <soc/ipq_uart.h> |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 43 | #include <stdint.h> |
| 44 | #include <stdlib.h> |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 45 | |
| 46 | #define FIFO_DATA_SIZE 4 |
| 47 | |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 48 | typedef struct { |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 49 | void *uart_dm_base; |
| 50 | void *uart_gsbi_base; |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 51 | unsigned uart_gsbi; |
| 52 | uart_clk_mnd_t mnd_value; |
| 53 | gpio_func_data_t dbg_uart_gpio[NO_OF_DBG_UART_GPIOS]; |
| 54 | } uart_params_t; |
| 55 | |
| 56 | /* |
| 57 | * All constants lifted from u-boot's |
| 58 | * board/qcom/ipq806x_cdp/ipq806x_board_param.h |
| 59 | */ |
| 60 | static const uart_params_t uart_board_param = { |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 61 | .uart_dm_base = (void *)UART4_DM_BASE, |
| 62 | .uart_gsbi_base = (void *)UART_GSBI4_BASE, |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 63 | .uart_gsbi = GSBI_4, |
| 64 | .mnd_value = { 12, 625, 313 }, |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 65 | .dbg_uart_gpio = { |
| 66 | { |
| 67 | .gpio = 10, |
| 68 | .func = 1, |
| 69 | .dir = GPIO_OUTPUT, |
| 70 | .pull = GPIO_NO_PULL, |
| 71 | .drvstr = GPIO_12MA, |
| 72 | .enable = GPIO_DISABLE |
| 73 | }, |
| 74 | { |
| 75 | .gpio = 11, |
| 76 | .func = 1, |
| 77 | .dir = GPIO_INPUT, |
| 78 | .pull = GPIO_NO_PULL, |
| 79 | .drvstr = GPIO_12MA, |
| 80 | .enable = GPIO_DISABLE |
| 81 | }, |
| 82 | } |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 83 | }; |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 84 | |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 85 | /** |
| 86 | * msm_boot_uart_dm_init_rx_transfer - Init Rx transfer |
| 87 | * @uart_dm_base: UART controller base address |
| 88 | */ |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 89 | static unsigned int msm_boot_uart_dm_init_rx_transfer(void *uart_dm_base) |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 90 | { |
| 91 | /* Reset receiver */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 92 | write32(MSM_BOOT_UART_DM_CR(uart_dm_base), |
| 93 | MSM_BOOT_UART_DM_CMD_RESET_RX); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 94 | |
| 95 | /* Enable receiver */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 96 | write32(MSM_BOOT_UART_DM_CR(uart_dm_base), |
| 97 | MSM_BOOT_UART_DM_CR_RX_ENABLE); |
| 98 | write32(MSM_BOOT_UART_DM_DMRX(uart_dm_base), |
| 99 | MSM_BOOT_UART_DM_DMRX_DEF_VALUE); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 100 | |
| 101 | /* Clear stale event */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 102 | write32(MSM_BOOT_UART_DM_CR(uart_dm_base), |
| 103 | MSM_BOOT_UART_DM_CMD_RES_STALE_INT); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 104 | |
| 105 | /* Enable stale event */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 106 | write32(MSM_BOOT_UART_DM_CR(uart_dm_base), |
| 107 | MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 108 | |
| 109 | return MSM_BOOT_UART_DM_E_SUCCESS; |
| 110 | } |
| 111 | |
Vadim Bendebury | 7c25640 | 2015-01-13 13:07:48 -0800 | [diff] [blame] | 112 | #if IS_ENABLED(CONFIG_DRIVERS_UART) |
| 113 | static unsigned int msm_boot_uart_dm_init(void *uart_dm_base); |
| 114 | |
| 115 | /* Received data is valid or not */ |
| 116 | static int valid_data = 0; |
| 117 | |
| 118 | /* Received data */ |
| 119 | static unsigned int word = 0; |
| 120 | |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 121 | /** |
| 122 | * msm_boot_uart_dm_read - reads a word from the RX FIFO. |
| 123 | * @data: location where the read data is stored |
| 124 | * @count: no of valid data in the FIFO |
| 125 | * @wait: indicates blocking call or not blocking call |
| 126 | * |
| 127 | * Reads a word from the RX FIFO. If no data is available blocks if |
| 128 | * @wait is true, else returns %MSM_BOOT_UART_DM_E_RX_NOT_READY. |
| 129 | */ |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 130 | #if 0 /* Not used yet */ |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 131 | static unsigned int |
| 132 | msm_boot_uart_dm_read(unsigned int *data, int *count, int wait) |
| 133 | { |
| 134 | static int total_rx_data = 0; |
| 135 | static int rx_data_read = 0; |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 136 | void *base; |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 137 | uint32_t status_reg; |
| 138 | |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 139 | base = uart_board_param.uart_dm_base; |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 140 | |
| 141 | if (data == NULL) |
| 142 | return MSM_BOOT_UART_DM_E_INVAL; |
| 143 | |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 144 | status_reg = readl(MSM_BOOT_UART_DM_MISR(base)); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 145 | |
| 146 | /* Check for DM_RXSTALE for RX transfer to finish */ |
| 147 | while (!(status_reg & MSM_BOOT_UART_DM_RXSTALE)) { |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 148 | status_reg = readl(MSM_BOOT_UART_DM_MISR(base)); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 149 | if (!wait) |
| 150 | return MSM_BOOT_UART_DM_E_RX_NOT_READY; |
| 151 | } |
| 152 | |
| 153 | /* Check for Overrun error. We'll just reset Error Status */ |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 154 | if (readl(MSM_BOOT_UART_DM_SR(base)) & |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 155 | MSM_BOOT_UART_DM_SR_UART_OVERRUN) { |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 156 | writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT, |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 157 | MSM_BOOT_UART_DM_CR(base)); |
| 158 | total_rx_data = rx_data_read = 0; |
| 159 | msm_boot_uart_dm_init(base); |
| 160 | return MSM_BOOT_UART_DM_E_RX_NOT_READY; |
| 161 | } |
| 162 | |
| 163 | /* Read UART_DM_RX_TOTAL_SNAP for actual number of bytes received */ |
| 164 | if (total_rx_data == 0) |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 165 | total_rx_data = readl(MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base)); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 166 | |
| 167 | /* Data available in FIFO; read a word. */ |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 168 | *data = readl(MSM_BOOT_UART_DM_RF(base, 0)); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 169 | |
| 170 | /* WAR for http://prism/CR/548280 */ |
| 171 | if (*data == 0) { |
| 172 | return MSM_BOOT_UART_DM_E_RX_NOT_READY; |
| 173 | } |
| 174 | |
| 175 | /* increment the total count of chars we've read so far */ |
| 176 | rx_data_read += FIFO_DATA_SIZE; |
| 177 | |
| 178 | /* actual count of valid data in word */ |
| 179 | *count = ((total_rx_data < rx_data_read) ? |
| 180 | (FIFO_DATA_SIZE - (rx_data_read - total_rx_data)) : |
| 181 | FIFO_DATA_SIZE); |
| 182 | |
| 183 | /* If there are still data left in FIFO we'll read them before |
| 184 | * initializing RX Transfer again |
| 185 | */ |
| 186 | if (rx_data_read < total_rx_data) |
| 187 | return MSM_BOOT_UART_DM_E_SUCCESS; |
| 188 | |
| 189 | msm_boot_uart_dm_init_rx_transfer(base); |
| 190 | total_rx_data = rx_data_read = 0; |
| 191 | |
| 192 | return MSM_BOOT_UART_DM_E_SUCCESS; |
| 193 | } |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 194 | #endif |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 195 | |
Vadim Bendebury | 24a53dd | 2014-05-27 18:03:38 -0700 | [diff] [blame] | 196 | void uart_tx_byte(int idx, unsigned char data) |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 197 | { |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 198 | int num_of_chars = 1; |
| 199 | unsigned tx_data = 0; |
| 200 | void *base = uart_board_param.uart_dm_base; |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 201 | |
Vadim Bendebury | 24a53dd | 2014-05-27 18:03:38 -0700 | [diff] [blame] | 202 | /* Wait until transmit FIFO is empty. */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 203 | while (!(read32(MSM_BOOT_UART_DM_SR(base)) & |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 204 | MSM_BOOT_UART_DM_SR_TXEMT)) |
| 205 | udelay(1); |
Vadim Bendebury | 24a53dd | 2014-05-27 18:03:38 -0700 | [diff] [blame] | 206 | /* |
| 207 | * TX FIFO is ready to accept new character(s). First write number of |
| 208 | * characters to be transmitted. |
| 209 | */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 210 | write32(MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base), num_of_chars); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 211 | |
Vadim Bendebury | 24a53dd | 2014-05-27 18:03:38 -0700 | [diff] [blame] | 212 | /* And now write the character(s) */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 213 | write32(MSM_BOOT_UART_DM_TF(base, 0), tx_data); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 214 | } |
Vadim Bendebury | 7c25640 | 2015-01-13 13:07:48 -0800 | [diff] [blame] | 215 | #endif /* CONFIG_SERIAL_UART */ |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 216 | |
| 217 | /* |
| 218 | * msm_boot_uart_dm_reset - resets UART controller |
| 219 | * @base: UART controller base address |
| 220 | */ |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 221 | static unsigned int msm_boot_uart_dm_reset(void *base) |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 222 | { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 223 | write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RESET_RX); |
| 224 | write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RESET_TX); |
| 225 | write32(MSM_BOOT_UART_DM_CR(base), |
| 226 | MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT); |
| 227 | write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RES_TX_ERR); |
| 228 | write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RES_STALE_INT); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 229 | |
| 230 | return MSM_BOOT_UART_DM_E_SUCCESS; |
| 231 | } |
| 232 | |
| 233 | /* |
| 234 | * msm_boot_uart_dm_init - initilaizes UART controller |
| 235 | * @uart_dm_base: UART controller base address |
| 236 | */ |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 237 | static unsigned int msm_boot_uart_dm_init(void *uart_dm_base) |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 238 | { |
| 239 | /* Configure UART mode registers MR1 and MR2 */ |
| 240 | /* Hardware flow control isn't supported */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 241 | write32(MSM_BOOT_UART_DM_MR1(uart_dm_base), 0x0); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 242 | |
| 243 | /* 8-N-1 configuration: 8 data bits - No parity - 1 stop bit */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 244 | write32(MSM_BOOT_UART_DM_MR2(uart_dm_base), |
| 245 | MSM_BOOT_UART_DM_8_N_1_MODE); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 246 | |
| 247 | /* Configure Interrupt Mask register IMR */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 248 | write32(MSM_BOOT_UART_DM_IMR(uart_dm_base), |
| 249 | MSM_BOOT_UART_DM_IMR_ENABLED); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 250 | |
| 251 | /* |
| 252 | * Configure Tx and Rx watermarks configuration registers |
| 253 | * TX watermark value is set to 0 - interrupt is generated when |
| 254 | * FIFO level is less than or equal to 0 |
| 255 | */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 256 | write32(MSM_BOOT_UART_DM_TFWR(uart_dm_base), |
| 257 | MSM_BOOT_UART_DM_TFW_VALUE); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 258 | |
| 259 | /* RX watermark value */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 260 | write32(MSM_BOOT_UART_DM_RFWR(uart_dm_base), |
| 261 | MSM_BOOT_UART_DM_RFW_VALUE); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 262 | |
| 263 | /* Configure Interrupt Programming Register */ |
| 264 | /* Set initial Stale timeout value */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 265 | write32(MSM_BOOT_UART_DM_IPR(uart_dm_base), |
| 266 | MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 267 | |
| 268 | /* Configure IRDA if required */ |
| 269 | /* Disabling IRDA mode */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 270 | write32(MSM_BOOT_UART_DM_IRDA(uart_dm_base), 0x0); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 271 | |
| 272 | /* Configure hunt character value in HCR register */ |
| 273 | /* Keep it in reset state */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 274 | write32(MSM_BOOT_UART_DM_HCR(uart_dm_base), 0x0); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 275 | |
| 276 | /* |
| 277 | * Configure Rx FIFO base address |
| 278 | * Both TX/RX shares same SRAM and default is half-n-half. |
| 279 | * Sticking with default value now. |
| 280 | * As such RAM size is (2^RAM_ADDR_WIDTH, 32-bit entries). |
| 281 | * We have found RAM_ADDR_WIDTH = 0x7f |
| 282 | */ |
| 283 | |
| 284 | /* Issue soft reset command */ |
| 285 | msm_boot_uart_dm_reset(uart_dm_base); |
| 286 | |
| 287 | /* Enable/Disable Rx/Tx DM interfaces */ |
| 288 | /* Data Mover not currently utilized. */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 289 | write32(MSM_BOOT_UART_DM_DMEN(uart_dm_base), 0x0); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 290 | |
| 291 | /* Enable transmitter */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 292 | write32(MSM_BOOT_UART_DM_CR(uart_dm_base), |
| 293 | MSM_BOOT_UART_DM_CR_TX_ENABLE); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 294 | |
| 295 | /* Initialize Receive Path */ |
| 296 | msm_boot_uart_dm_init_rx_transfer(uart_dm_base); |
| 297 | |
| 298 | return 0; |
| 299 | } |
| 300 | |
| 301 | /** |
Vadim Bendebury | 7c25640 | 2015-01-13 13:07:48 -0800 | [diff] [blame] | 302 | * ipq806x_uart_init - initializes UART |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 303 | * |
| 304 | * Initializes clocks, GPIO and UART controller. |
| 305 | */ |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 306 | void uart_init(int idx) |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 307 | { |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 308 | /* Note int idx isn't used in this driver. */ |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 309 | void *dm_base; |
| 310 | void *gsbi_base; |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 311 | |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 312 | dm_base = uart_board_param.uart_dm_base; |
Vadim Bendebury | 7c25640 | 2015-01-13 13:07:48 -0800 | [diff] [blame] | 313 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 314 | if (read32(MSM_BOOT_UART_DM_CSR(dm_base)) == UART_DM_CLK_RX_TX_BIT_RATE) |
Vadim Bendebury | 7c25640 | 2015-01-13 13:07:48 -0800 | [diff] [blame] | 315 | return; /* UART must have been already initialized. */ |
| 316 | |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 317 | gsbi_base = uart_board_param.uart_gsbi_base; |
| 318 | ipq_configure_gpio(uart_board_param.dbg_uart_gpio, |
| 319 | NO_OF_DBG_UART_GPIOS); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 320 | |
| 321 | /* Configure the uart clock */ |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 322 | uart_clock_config(uart_board_param.uart_gsbi, |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 323 | uart_board_param.mnd_value.m_value, |
| 324 | uart_board_param.mnd_value.n_value, |
| 325 | uart_board_param.mnd_value.d_value, |
| 326 | 0); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 327 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 328 | write32(GSBI_CTRL_REG(gsbi_base), |
| 329 | GSBI_PROTOCOL_CODE_I2C_UART << GSBI_CTRL_REG_PROTOCOL_CODE_S); |
| 330 | write32(MSM_BOOT_UART_DM_CSR(dm_base), UART_DM_CLK_RX_TX_BIT_RATE); |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 331 | |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 332 | /* Intialize UART_DM */ |
| 333 | msm_boot_uart_dm_init(dm_base); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 334 | } |
| 335 | |
Vadim Bendebury | 7c25640 | 2015-01-13 13:07:48 -0800 | [diff] [blame] | 336 | /* for the benefit of non-console uart init */ |
| 337 | void ipq806x_uart_init(void) |
| 338 | { |
| 339 | uart_init(0); |
| 340 | } |
| 341 | |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 342 | #if 0 /* Not used yet */ |
| 343 | uint32_t uartmem_getbaseaddr(void) |
| 344 | { |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 345 | return (uint32_t)uart_board_param.uart_dm_base; |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 346 | } |
| 347 | #endif |
| 348 | |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 349 | /** |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 350 | * uart_tx_flush - transmits a string of data |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 351 | * @s: string to transmit |
| 352 | */ |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 353 | void uart_tx_flush(int idx) |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 354 | { |
Vadim Bendebury | b67b715 | 2015-01-13 12:46:57 -0800 | [diff] [blame] | 355 | void *base = uart_board_param.uart_dm_base; |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 356 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 357 | while (!(read32(MSM_BOOT_UART_DM_SR(base)) & |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 358 | MSM_BOOT_UART_DM_SR_TXEMT)) |
| 359 | ; |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 360 | } |
| 361 | |
| 362 | /** |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 363 | * uart_can_rx_byte - checks if data available for reading |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 364 | * |
| 365 | * Returns 1 if data available, 0 otherwise |
| 366 | */ |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 367 | #if 0 /* Not used yet */ |
| 368 | int uart_can_rx_byte(void) |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 369 | { |
| 370 | /* Return if data is already read */ |
| 371 | if (valid_data) |
| 372 | return 1; |
| 373 | |
| 374 | /* Read data from the FIFO */ |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 375 | if (msm_boot_uart_dm_read(&word, &valid_data, 0) != |
| 376 | MSM_BOOT_UART_DM_E_SUCCESS) |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 377 | return 0; |
| 378 | |
| 379 | return 1; |
| 380 | } |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 381 | #endif |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 382 | |
Vadim Bendebury | 7c25640 | 2015-01-13 13:07:48 -0800 | [diff] [blame] | 383 | #if IS_ENABLED(CONFIG_DRIVERS_UART) |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 384 | /** |
| 385 | * ipq806x_serial_getc - reads a character |
| 386 | * |
| 387 | * Returns the character read from serial port. |
| 388 | */ |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 389 | uint8_t uart_rx_byte(int idx) |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 390 | { |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 391 | uint8_t byte; |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 392 | |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 393 | #if 0 /* Not used yet */ |
| 394 | while (!uart_can_rx_byte()) { |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 395 | /* wait for incoming data */ |
| 396 | } |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 397 | #endif |
| 398 | byte = (uint8_t)(word & 0xff); |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 399 | word = word >> 8; |
| 400 | valid_data--; |
| 401 | |
| 402 | return byte; |
| 403 | } |
Vadim Bendebury | 7c25640 | 2015-01-13 13:07:48 -0800 | [diff] [blame] | 404 | #endif |
| 405 | |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 406 | #ifndef __PRE_RAM__ |
| 407 | /* TODO: Implement fuction */ |
| 408 | void uart_fill_lb(void *data) |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 409 | { |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 410 | } |
Vadim Bendebury | f17680b | 2014-04-23 14:00:59 -0700 | [diff] [blame] | 411 | #endif |