Angel Pons | 8a3453f | 2020-04-02 23:48:19 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 3 | |
| 4 | #include <stddef.h> |
Aaron Durbin | 932e09d | 2016-07-13 23:09:52 -0500 | [diff] [blame] | 5 | #include <arch/acpi.h> |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 6 | #include <assert.h> |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 7 | #include <console/console.h> |
| 8 | #include <cbmem.h> |
Patrick Rudolph | f677d17 | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 9 | #include <cf9_reset.h> |
robbie zhang | 13a2e94 | 2016-02-10 11:40:11 -0800 | [diff] [blame] | 10 | #include <cpu/intel/microcode.h> |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 11 | #include <cpu/x86/mtrr.h> |
| 12 | #include <ec/google/chromeec/ec.h> |
| 13 | #include <ec/google/chromeec/ec_commands.h> |
| 14 | #include <elog.h> |
Lee Leahy | b092c9e | 2016-01-01 18:09:50 -0800 | [diff] [blame] | 15 | #include <fsp/romstage.h> |
Aaron Durbin | decd062 | 2017-12-15 12:26:40 -0700 | [diff] [blame] | 16 | #include <mrc_cache.h> |
Kyösti Mälkki | 65e8f64 | 2016-06-27 11:27:56 +0300 | [diff] [blame] | 17 | #include <program_loading.h> |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 18 | #include <romstage_handoff.h> |
Lee Leahy | 0be6d93 | 2015-06-26 11:15:42 -0700 | [diff] [blame] | 19 | #include <smbios.h> |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 20 | #include <stage_cache.h> |
Aaron Durbin | afe8aee | 2016-11-29 21:37:42 -0600 | [diff] [blame] | 21 | #include <string.h> |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 22 | #include <timestamp.h> |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 23 | #include <vendorcode/google/chromeos/chromeos.h> |
| 24 | |
Arthur Heymans | 73ac121 | 2019-05-23 14:41:19 +0200 | [diff] [blame] | 25 | static void raminit_common(struct romstage_params *params) |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 26 | { |
Subrata Banik | 0beac81 | 2017-07-12 15:13:53 +0530 | [diff] [blame] | 27 | bool s3wake; |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 28 | struct region_device rdev; |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 29 | |
| 30 | post_code(0x32); |
| 31 | |
| 32 | timestamp_add_now(TS_BEFORE_INITRAM); |
| 33 | |
Subrata Banik | 0beac81 | 2017-07-12 15:13:53 +0530 | [diff] [blame] | 34 | s3wake = params->power_state->prev_sleep_state == ACPI_S3; |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 35 | |
Kyösti Mälkki | 7f50afb | 2019-09-11 17:12:26 +0300 | [diff] [blame] | 36 | elog_boot_notify(s3wake); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 37 | |
| 38 | /* Perform remaining SOC initialization */ |
| 39 | soc_pre_ram_init(params); |
| 40 | post_code(0x33); |
| 41 | |
| 42 | /* Check recovery and MRC cache */ |
Nico Huber | 66318aa | 2019-05-04 16:59:20 +0200 | [diff] [blame] | 43 | params->saved_data_size = 0; |
| 44 | params->saved_data = NULL; |
| 45 | if (!params->disable_saved_data) { |
Furquan Shaikh | 0325dc6 | 2016-07-25 13:02:36 -0700 | [diff] [blame] | 46 | if (vboot_recovery_mode_enabled()) { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 47 | /* Recovery mode does not use MRC cache */ |
| 48 | printk(BIOS_DEBUG, |
| 49 | "Recovery mode: not using MRC cache.\n"); |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 50 | } else if (CONFIG(CACHE_MRC_SETTINGS) |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 51 | && (!mrc_cache_get_current(MRC_TRAINING_DATA, |
| 52 | params->fsp_version, |
| 53 | &rdev))) { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 54 | /* MRC cache found */ |
Nico Huber | 66318aa | 2019-05-04 16:59:20 +0200 | [diff] [blame] | 55 | params->saved_data_size = region_device_sz(&rdev); |
| 56 | params->saved_data = rdev_mmap_full(&rdev); |
Elyes HAOUAS | 1895838 | 2018-08-07 12:23:16 +0200 | [diff] [blame] | 57 | /* Assume boot device is memory mapped. */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 58 | assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); |
Nico Huber | 16895c5 | 2019-05-04 16:29:17 +0200 | [diff] [blame] | 59 | } else if (s3wake) { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 60 | /* Waking from S3 and no cache. */ |
| 61 | printk(BIOS_DEBUG, |
| 62 | "No MRC cache found in S3 resume path.\n"); |
| 63 | post_code(POST_RESUME_FAILURE); |
Patrick Rudolph | f677d17 | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 64 | /* FIXME: A "system" reset is likely enough: */ |
| 65 | full_reset(); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 66 | } else { |
| 67 | printk(BIOS_DEBUG, "No MRC cache found.\n"); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 68 | } |
| 69 | } |
| 70 | |
| 71 | /* Initialize RAM */ |
| 72 | raminit(params); |
| 73 | timestamp_add_now(TS_AFTER_INITRAM); |
| 74 | |
| 75 | /* Save MRC output */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 76 | if (CONFIG(CACHE_MRC_SETTINGS)) { |
Nico Huber | 66318aa | 2019-05-04 16:59:20 +0200 | [diff] [blame] | 77 | printk(BIOS_DEBUG, "MRC data at %p %zu bytes\n", |
| 78 | params->data_to_save, params->data_to_save_size); |
Nico Huber | 16895c5 | 2019-05-04 16:29:17 +0200 | [diff] [blame] | 79 | if (!s3wake |
Nico Huber | 66318aa | 2019-05-04 16:59:20 +0200 | [diff] [blame] | 80 | && (params->data_to_save_size != 0) |
| 81 | && (params->data_to_save != NULL)) |
Lee Leahy | 216712a | 2017-03-17 11:23:32 -0700 | [diff] [blame] | 82 | mrc_cache_stash_data(MRC_TRAINING_DATA, |
| 83 | params->fsp_version, |
Nico Huber | 66318aa | 2019-05-04 16:59:20 +0200 | [diff] [blame] | 84 | params->data_to_save, |
| 85 | params->data_to_save_size); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 86 | } |
| 87 | |
| 88 | /* Save DIMM information */ |
Subrata Banik | 0beac81 | 2017-07-12 15:13:53 +0530 | [diff] [blame] | 89 | if (!s3wake) |
| 90 | mainboard_save_dimm_info(params); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 91 | |
| 92 | /* Create romstage handof information */ |
Aaron Durbin | 77e1399 | 2016-11-29 17:43:04 -0600 | [diff] [blame] | 93 | if (romstage_handoff_init( |
| 94 | params->power_state->prev_sleep_state == ACPI_S3) < 0) |
Patrick Rudolph | f677d17 | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 95 | /* FIXME: A "system" reset is likely enough: */ |
| 96 | full_reset(); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 97 | } |
| 98 | |
Arthur Heymans | 73ac121 | 2019-05-23 14:41:19 +0200 | [diff] [blame] | 99 | void cache_as_ram_stage_main(FSP_INFO_HEADER *fih) |
| 100 | { |
| 101 | struct romstage_params params = { |
| 102 | .chipset_context = fih, |
| 103 | }; |
| 104 | |
| 105 | post_code(0x30); |
| 106 | |
| 107 | timestamp_add_now(TS_START_ROMSTAGE); |
| 108 | |
| 109 | /* Load microcode before RAM init */ |
| 110 | if (CONFIG(SUPPORT_CPU_UCODE_IN_CBFS)) |
| 111 | intel_update_microcode_from_cbfs(); |
| 112 | |
| 113 | /* Display parameters */ |
| 114 | if (!CONFIG(NO_MMCONF_SUPPORT)) |
| 115 | printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n", |
| 116 | CONFIG_MMCONF_BASE_ADDRESS); |
| 117 | printk(BIOS_INFO, "Using FSP 1.1\n"); |
| 118 | |
| 119 | /* Display FSP banner */ |
| 120 | print_fsp_info(fih); |
| 121 | |
| 122 | /* Stash FSP version. */ |
| 123 | params.fsp_version = fsp_version(fih); |
| 124 | |
| 125 | /* Get power state */ |
| 126 | params.power_state = fill_power_state(); |
| 127 | |
| 128 | /* Board initialization before and after RAM is enabled */ |
| 129 | mainboard_pre_raminit(¶ms); |
| 130 | |
| 131 | post_code(0x31); |
| 132 | |
| 133 | /* Initialize memory */ |
| 134 | raminit_common(¶ms); |
| 135 | |
| 136 | soc_after_ram_init(¶ms); |
| 137 | post_code(0x38); |
| 138 | } |
| 139 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 140 | /* Initialize the power state */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 141 | __weak struct chipset_power_state *fill_power_state(void) |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 142 | { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 143 | return NULL; |
| 144 | } |
| 145 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 146 | /* Board initialization before and after RAM is enabled */ |
Arthur Heymans | 73ac121 | 2019-05-23 14:41:19 +0200 | [diff] [blame] | 147 | __weak void mainboard_pre_raminit(struct romstage_params *params) |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 148 | { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 149 | } |
| 150 | |
| 151 | /* Save the DIMM information for SMBIOS table 17 */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 152 | __weak void mainboard_save_dimm_info( |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 153 | struct romstage_params *params) |
| 154 | { |
| 155 | int channel; |
| 156 | CHANNEL_INFO *channel_info; |
| 157 | int dimm; |
| 158 | DIMM_INFO *dimm_info; |
| 159 | int dimm_max; |
| 160 | void *hob_list_ptr; |
| 161 | EFI_HOB_GUID_TYPE *hob_ptr; |
| 162 | int index; |
| 163 | struct memory_info *mem_info; |
| 164 | FSP_SMBIOS_MEMORY_INFO *memory_info_hob; |
| 165 | const EFI_GUID memory_info_hob_guid = FSP_SMBIOS_MEMORY_INFO_GUID; |
| 166 | |
| 167 | /* Locate the memory info HOB, presence validated by raminit */ |
| 168 | hob_list_ptr = fsp_get_hob_list(); |
| 169 | hob_ptr = get_next_guid_hob(&memory_info_hob_guid, hob_list_ptr); |
| 170 | memory_info_hob = (FSP_SMBIOS_MEMORY_INFO *)(hob_ptr + 1); |
| 171 | |
| 172 | /* Display the data in the FSP_SMBIOS_MEMORY_INFO HOB */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 173 | if (CONFIG(DISPLAY_HOBS)) { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 174 | printk(BIOS_DEBUG, "FSP_SMBIOS_MEMORY_INFO HOB\n"); |
| 175 | printk(BIOS_DEBUG, " 0x%02x: Revision\n", |
| 176 | memory_info_hob->Revision); |
| 177 | printk(BIOS_DEBUG, " 0x%02x: MemoryType\n", |
| 178 | memory_info_hob->MemoryType); |
Lee Leahy | 0be6d93 | 2015-06-26 11:15:42 -0700 | [diff] [blame] | 179 | printk(BIOS_DEBUG, " %d: MemoryFrequencyInMHz\n", |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 180 | memory_info_hob->MemoryFrequencyInMHz); |
Lee Leahy | 0be6d93 | 2015-06-26 11:15:42 -0700 | [diff] [blame] | 181 | printk(BIOS_DEBUG, " %d: DataWidth in bits\n", |
| 182 | memory_info_hob->DataWidth); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 183 | printk(BIOS_DEBUG, " 0x%02x: ErrorCorrectionType\n", |
| 184 | memory_info_hob->ErrorCorrectionType); |
| 185 | printk(BIOS_DEBUG, " 0x%02x: ChannelCount\n", |
| 186 | memory_info_hob->ChannelCount); |
| 187 | for (channel = 0; channel < memory_info_hob->ChannelCount; |
| 188 | channel++) { |
| 189 | channel_info = &memory_info_hob->ChannelInfo[channel]; |
| 190 | printk(BIOS_DEBUG, " Channel %d\n", channel); |
| 191 | printk(BIOS_DEBUG, " 0x%02x: ChannelId\n", |
| 192 | channel_info->ChannelId); |
| 193 | printk(BIOS_DEBUG, " 0x%02x: DimmCount\n", |
| 194 | channel_info->DimmCount); |
| 195 | for (dimm = 0; dimm < channel_info->DimmCount; |
| 196 | dimm++) { |
| 197 | dimm_info = &channel_info->DimmInfo[dimm]; |
| 198 | printk(BIOS_DEBUG, " DIMM %d\n", dimm); |
| 199 | printk(BIOS_DEBUG, " 0x%02x: DimmId\n", |
| 200 | dimm_info->DimmId); |
Lee Leahy | 0be6d93 | 2015-06-26 11:15:42 -0700 | [diff] [blame] | 201 | printk(BIOS_DEBUG, " %d: SizeInMb\n", |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 202 | dimm_info->SizeInMb); |
| 203 | } |
| 204 | } |
| 205 | } |
| 206 | |
| 207 | /* |
| 208 | * Allocate CBMEM area for DIMM information used to populate SMBIOS |
| 209 | * table 17 |
| 210 | */ |
| 211 | mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); |
Julius Werner | 540a980 | 2019-12-09 13:03:29 -0800 | [diff] [blame] | 212 | printk(BIOS_DEBUG, "CBMEM entry for DIMM info: %p\n", mem_info); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 213 | if (mem_info == NULL) |
| 214 | return; |
| 215 | memset(mem_info, 0, sizeof(*mem_info)); |
| 216 | |
| 217 | /* Describe the first N DIMMs in the system */ |
| 218 | index = 0; |
| 219 | dimm_max = ARRAY_SIZE(mem_info->dimm); |
| 220 | for (channel = 0; channel < memory_info_hob->ChannelCount; channel++) { |
| 221 | if (index >= dimm_max) |
| 222 | break; |
| 223 | channel_info = &memory_info_hob->ChannelInfo[channel]; |
| 224 | for (dimm = 0; dimm < channel_info->DimmCount; dimm++) { |
| 225 | if (index >= dimm_max) |
| 226 | break; |
| 227 | dimm_info = &channel_info->DimmInfo[dimm]; |
| 228 | |
| 229 | /* Populate the DIMM information */ |
| 230 | if (dimm_info->SizeInMb) { |
| 231 | mem_info->dimm[index].dimm_size = |
| 232 | dimm_info->SizeInMb; |
| 233 | mem_info->dimm[index].ddr_type = |
| 234 | memory_info_hob->MemoryType; |
| 235 | mem_info->dimm[index].ddr_frequency = |
| 236 | memory_info_hob->MemoryFrequencyInMHz; |
| 237 | mem_info->dimm[index].channel_num = |
| 238 | channel_info->ChannelId; |
| 239 | mem_info->dimm[index].dimm_num = |
| 240 | dimm_info->DimmId; |
Lee Leahy | 0be6d93 | 2015-06-26 11:15:42 -0700 | [diff] [blame] | 241 | switch (memory_info_hob->DataWidth) { |
| 242 | default: |
| 243 | case 8: |
| 244 | mem_info->dimm[index].bus_width = |
| 245 | MEMORY_BUS_WIDTH_8; |
| 246 | break; |
| 247 | |
| 248 | case 16: |
| 249 | mem_info->dimm[index].bus_width = |
| 250 | MEMORY_BUS_WIDTH_16; |
| 251 | break; |
| 252 | |
| 253 | case 32: |
| 254 | mem_info->dimm[index].bus_width = |
| 255 | MEMORY_BUS_WIDTH_32; |
| 256 | break; |
| 257 | |
| 258 | case 64: |
| 259 | mem_info->dimm[index].bus_width = |
| 260 | MEMORY_BUS_WIDTH_64; |
| 261 | break; |
| 262 | |
| 263 | case 128: |
| 264 | mem_info->dimm[index].bus_width = |
| 265 | MEMORY_BUS_WIDTH_128; |
| 266 | break; |
| 267 | } |
Duncan Laurie | 46a2c77 | 2015-07-20 16:48:55 -0700 | [diff] [blame] | 268 | |
| 269 | /* Add any mainboard specific information */ |
| 270 | mainboard_add_dimm_info(params, mem_info, |
| 271 | channel, dimm, index); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 272 | index++; |
| 273 | } |
| 274 | } |
| 275 | } |
| 276 | mem_info->dimm_cnt = index; |
| 277 | printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); |
| 278 | } |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 279 | |
Duncan Laurie | 46a2c77 | 2015-07-20 16:48:55 -0700 | [diff] [blame] | 280 | /* Add any mainboard specific information */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 281 | __weak void mainboard_add_dimm_info( |
Duncan Laurie | 46a2c77 | 2015-07-20 16:48:55 -0700 | [diff] [blame] | 282 | struct romstage_params *params, |
| 283 | struct memory_info *mem_info, |
| 284 | int channel, int dimm, int index) |
| 285 | { |
Duncan Laurie | 46a2c77 | 2015-07-20 16:48:55 -0700 | [diff] [blame] | 286 | } |
| 287 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 288 | /* Get the memory configuration data */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 289 | __weak int mrc_cache_get_current(int type, uint32_t version, |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 290 | struct region_device *rdev) |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 291 | { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 292 | return -1; |
| 293 | } |
| 294 | |
| 295 | /* Save the memory configuration data */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 296 | __weak int mrc_cache_stash_data(int type, uint32_t version, |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 297 | const void *data, size_t size) |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 298 | { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 299 | return -1; |
| 300 | } |
| 301 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 302 | /* Display the memory configuration */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 303 | __weak void report_memory_config(void) |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 304 | { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 305 | } |
| 306 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 307 | /* SOC initialization after RAM is enabled */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 308 | __weak void soc_after_ram_init(struct romstage_params *params) |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 309 | { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 310 | } |
| 311 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 312 | /* SOC initialization before RAM is enabled */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 313 | __weak void soc_pre_ram_init(struct romstage_params *params) |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 314 | { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 315 | } |