drivers/intel/fsp1_1: align on using ACPI_Sx definitions
The SLEEP_STATE_x definitions in the chipsets utilizing
FSP 1.1. driver have the exact same values as the ACPI_Sx
definitions. The chipsets will be moved over subsequently,
but updating this first allows the per-chipset patches
to be isolated.
BUG=chrome-os-partner:54977
Change-Id: I383a9a732ef68bf2276f6149ffa5360bcdfb70b3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15665
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index f99c87a..c1b1ca5 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -15,6 +15,7 @@
*/
#include <stddef.h>
+#include <arch/acpi.h>
#include <arch/io.h>
#include <arch/cbfs.h>
#include <arch/early_variables.h>
@@ -109,7 +110,7 @@
pei_data->boot_mode = params->power_state->prev_sleep_state;
#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
- if (params->power_state->prev_sleep_state != SLEEP_STATE_S3)
+ if (params->power_state->prev_sleep_state != ACPI_S3)
boot_count_increment();
#endif
@@ -131,7 +132,7 @@
/* MRC cache found */
params->pei_data->saved_data_size = cache->size;
params->pei_data->saved_data = &cache->data[0];
- } else if (params->pei_data->boot_mode == SLEEP_STATE_S3) {
+ } else if (params->pei_data->boot_mode == ACPI_S3) {
/* Waking from S3 and no cache. */
printk(BIOS_DEBUG,
"No MRC cache found in S3 resume path.\n");
@@ -151,7 +152,7 @@
if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) {
printk(BIOS_DEBUG, "MRC data at %p %d bytes\n",
pei_data->data_to_save, pei_data->data_to_save_size);
- if ((params->pei_data->boot_mode != SLEEP_STATE_S3)
+ if ((params->pei_data->boot_mode != ACPI_S3)
&& (params->pei_data->data_to_save_size != 0)
&& (params->pei_data->data_to_save != NULL))
mrc_cache_stash_data_with_version(
@@ -167,7 +168,7 @@
handoff = romstage_handoff_find_or_add();
if (handoff != NULL)
handoff->s3_resume = (params->power_state->prev_sleep_state ==
- SLEEP_STATE_S3);
+ ACPI_S3);
else {
printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
hard_reset();
@@ -181,7 +182,7 @@
!IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) &&
!IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK))
init_tpm(params->power_state->prev_sleep_state ==
- SLEEP_STATE_S3);
+ ACPI_S3);
}
void after_cache_as_ram_stage(void)
@@ -204,7 +205,7 @@
struct pei_data *pei_data;
pei_data = params->pei_data;
- if (params->pei_data->boot_mode == SLEEP_STATE_S0) {
+ if (params->pei_data->boot_mode == ACPI_S0) {
/* Ensure EC is running RO firmware. */
google_chromeec_check_ec_image(EC_IMAGE_RO);
}