Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Google Inc. |
Lee Leahy | a608969 | 2016-01-05 16:34:58 -0800 | [diff] [blame] | 5 | * Copyright (C) 2015-2016 Intel Corporation. |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <stddef.h> |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 18 | #include <arch/io.h> |
| 19 | #include <arch/cbfs.h> |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 20 | #include <arch/early_variables.h> |
Duncan Laurie | 91da91f | 2015-09-04 13:47:34 -0700 | [diff] [blame] | 21 | #include <boardid.h> |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 22 | #include <console/console.h> |
| 23 | #include <cbmem.h> |
robbie zhang | 13a2e94 | 2016-02-10 11:40:11 -0800 | [diff] [blame] | 24 | #include <cpu/intel/microcode.h> |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 25 | #include <cpu/x86/mtrr.h> |
| 26 | #include <ec/google/chromeec/ec.h> |
| 27 | #include <ec/google/chromeec/ec_commands.h> |
| 28 | #include <elog.h> |
Lee Leahy | b092c9e | 2016-01-01 18:09:50 -0800 | [diff] [blame] | 29 | #include <fsp/romstage.h> |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 30 | #include <reset.h> |
Kyösti Mälkki | 65e8f64 | 2016-06-27 11:27:56 +0300 | [diff] [blame^] | 31 | #include <program_loading.h> |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 32 | #include <romstage_handoff.h> |
Lee Leahy | 0be6d93 | 2015-06-26 11:15:42 -0700 | [diff] [blame] | 33 | #include <smbios.h> |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 34 | #include <soc/intel/common/mrc_cache.h> |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 35 | #include <stage_cache.h> |
| 36 | #include <timestamp.h> |
| 37 | #include <tpm.h> |
| 38 | #include <vendorcode/google/chromeos/chromeos.h> |
| 39 | |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 40 | asmlinkage void *romstage_main(FSP_INFO_HEADER *fih) |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 41 | { |
| 42 | void *top_of_stack; |
| 43 | struct pei_data pei_data; |
| 44 | struct romstage_params params = { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 45 | .pei_data = &pei_data, |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 46 | .chipset_context = fih, |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 47 | }; |
| 48 | |
| 49 | post_code(0x30); |
| 50 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 51 | timestamp_add_now(TS_START_ROMSTAGE); |
| 52 | |
robbie zhang | 13a2e94 | 2016-02-10 11:40:11 -0800 | [diff] [blame] | 53 | /* Load microcode before ram init */ |
| 54 | if (IS_ENABLED(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS)) |
| 55 | intel_update_microcode_from_cbfs(); |
| 56 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 57 | memset(&pei_data, 0, sizeof(pei_data)); |
| 58 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 59 | /* Display parameters */ |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 60 | printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n", |
| 61 | CONFIG_MMCONF_BASE_ADDRESS); |
Aaron Durbin | 929b602 | 2015-12-09 16:00:18 -0600 | [diff] [blame] | 62 | printk(BIOS_INFO, "Using FSP 1.1\n"); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 63 | |
| 64 | /* Display FSP banner */ |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 65 | print_fsp_info(fih); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 66 | |
Aaron Durbin | 929b602 | 2015-12-09 16:00:18 -0600 | [diff] [blame] | 67 | /* Stash FSP version. */ |
| 68 | params.fsp_version = fsp_version(fih); |
| 69 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 70 | /* Get power state */ |
| 71 | params.power_state = fill_power_state(); |
| 72 | |
Duncan Laurie | 91da91f | 2015-09-04 13:47:34 -0700 | [diff] [blame] | 73 | /* |
| 74 | * Read and print board version. Done after SOC romstage |
| 75 | * in case PCH needs to be configured to talk to the EC. |
| 76 | */ |
| 77 | if (IS_ENABLED(CONFIG_BOARD_ID_AUTO)) |
| 78 | printk(BIOS_INFO, "MLB: board version %d\n", board_id()); |
| 79 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 80 | /* Call into mainboard. */ |
| 81 | mainboard_romstage_entry(¶ms); |
| 82 | soc_after_ram_init(¶ms); |
| 83 | post_code(0x38); |
| 84 | |
| 85 | top_of_stack = setup_stack_and_mtrrs(); |
| 86 | |
Lee Leahy | 3e5bc1f | 2015-06-24 11:17:54 -0700 | [diff] [blame] | 87 | printk(BIOS_DEBUG, "Calling FspTempRamExit API\n"); |
| 88 | timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_START); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 89 | return top_of_stack; |
| 90 | } |
| 91 | |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 92 | void *cache_as_ram_stage_main(FSP_INFO_HEADER *fih) |
| 93 | { |
| 94 | return romstage_main(fih); |
| 95 | } |
| 96 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 97 | /* Entry from the mainboard. */ |
| 98 | void romstage_common(struct romstage_params *params) |
| 99 | { |
| 100 | const struct mrc_saved_data *cache; |
| 101 | struct romstage_handoff *handoff; |
| 102 | struct pei_data *pei_data; |
| 103 | |
| 104 | post_code(0x32); |
| 105 | |
| 106 | timestamp_add_now(TS_BEFORE_INITRAM); |
| 107 | |
| 108 | pei_data = params->pei_data; |
| 109 | pei_data->boot_mode = params->power_state->prev_sleep_state; |
| 110 | |
| 111 | #if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) |
| 112 | if (params->power_state->prev_sleep_state != SLEEP_STATE_S3) |
| 113 | boot_count_increment(); |
| 114 | #endif |
| 115 | |
| 116 | /* Perform remaining SOC initialization */ |
| 117 | soc_pre_ram_init(params); |
| 118 | post_code(0x33); |
| 119 | |
| 120 | /* Check recovery and MRC cache */ |
| 121 | params->pei_data->saved_data_size = 0; |
| 122 | params->pei_data->saved_data = NULL; |
| 123 | if (!params->pei_data->disable_saved_data) { |
| 124 | if (recovery_mode_enabled()) { |
| 125 | /* Recovery mode does not use MRC cache */ |
| 126 | printk(BIOS_DEBUG, |
| 127 | "Recovery mode: not using MRC cache.\n"); |
Lee Leahy | a608969 | 2016-01-05 16:34:58 -0800 | [diff] [blame] | 128 | } else if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS) |
| 129 | && (!mrc_cache_get_current_with_version(&cache, |
| 130 | params->fsp_version))) { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 131 | /* MRC cache found */ |
| 132 | params->pei_data->saved_data_size = cache->size; |
| 133 | params->pei_data->saved_data = &cache->data[0]; |
| 134 | } else if (params->pei_data->boot_mode == SLEEP_STATE_S3) { |
| 135 | /* Waking from S3 and no cache. */ |
| 136 | printk(BIOS_DEBUG, |
| 137 | "No MRC cache found in S3 resume path.\n"); |
| 138 | post_code(POST_RESUME_FAILURE); |
| 139 | hard_reset(); |
| 140 | } else { |
| 141 | printk(BIOS_DEBUG, "No MRC cache found.\n"); |
| 142 | mainboard_check_ec_image(params); |
| 143 | } |
| 144 | } |
| 145 | |
| 146 | /* Initialize RAM */ |
| 147 | raminit(params); |
| 148 | timestamp_add_now(TS_AFTER_INITRAM); |
| 149 | |
| 150 | /* Save MRC output */ |
Lee Leahy | a608969 | 2016-01-05 16:34:58 -0800 | [diff] [blame] | 151 | if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) { |
| 152 | printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", |
| 153 | pei_data->data_to_save, pei_data->data_to_save_size); |
| 154 | if ((params->pei_data->boot_mode != SLEEP_STATE_S3) |
| 155 | && (params->pei_data->data_to_save_size != 0) |
| 156 | && (params->pei_data->data_to_save != NULL)) |
| 157 | mrc_cache_stash_data_with_version( |
| 158 | params->pei_data->data_to_save, |
| 159 | params->pei_data->data_to_save_size, |
| 160 | params->fsp_version); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 161 | } |
| 162 | |
| 163 | /* Save DIMM information */ |
| 164 | mainboard_save_dimm_info(params); |
| 165 | |
| 166 | /* Create romstage handof information */ |
| 167 | handoff = romstage_handoff_find_or_add(); |
| 168 | if (handoff != NULL) |
| 169 | handoff->s3_resume = (params->power_state->prev_sleep_state == |
| 170 | SLEEP_STATE_S3); |
| 171 | else { |
| 172 | printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); |
| 173 | hard_reset(); |
| 174 | } |
| 175 | |
Duncan Laurie | fe4983e | 2016-03-14 09:29:09 -0700 | [diff] [blame] | 176 | /* |
| 177 | * Initialize the TPM, unless the TPM was already initialized |
| 178 | * in verstage and used to verify romstage. |
| 179 | */ |
| 180 | if (IS_ENABLED(CONFIG_LPC_TPM) && |
| 181 | !IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) && |
| 182 | !IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK)) |
| 183 | init_tpm(params->power_state->prev_sleep_state == |
| 184 | SLEEP_STATE_S3); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 185 | } |
| 186 | |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 187 | void after_cache_as_ram_stage(void) |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 188 | { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 189 | /* Load the ramstage. */ |
Kyösti Mälkki | 65e8f64 | 2016-06-27 11:27:56 +0300 | [diff] [blame^] | 190 | run_ramstage(); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 191 | die("ERROR - Failed to load ramstage!"); |
| 192 | } |
| 193 | |
| 194 | /* Initialize the power state */ |
| 195 | __attribute__((weak)) struct chipset_power_state *fill_power_state(void) |
| 196 | { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 197 | return NULL; |
| 198 | } |
| 199 | |
| 200 | __attribute__((weak)) void mainboard_check_ec_image( |
| 201 | struct romstage_params *params) |
| 202 | { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 203 | #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) |
| 204 | struct pei_data *pei_data; |
| 205 | |
| 206 | pei_data = params->pei_data; |
| 207 | if (params->pei_data->boot_mode == SLEEP_STATE_S0) { |
| 208 | /* Ensure EC is running RO firmware. */ |
| 209 | google_chromeec_check_ec_image(EC_IMAGE_RO); |
| 210 | } |
| 211 | #endif |
| 212 | } |
| 213 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 214 | /* Board initialization before and after RAM is enabled */ |
| 215 | __attribute__((weak)) void mainboard_romstage_entry( |
| 216 | struct romstage_params *params) |
| 217 | { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 218 | post_code(0x31); |
| 219 | |
| 220 | /* Initliaze memory */ |
| 221 | romstage_common(params); |
| 222 | } |
| 223 | |
| 224 | /* Save the DIMM information for SMBIOS table 17 */ |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 225 | __attribute__((weak)) void mainboard_save_dimm_info( |
| 226 | struct romstage_params *params) |
| 227 | { |
| 228 | int channel; |
| 229 | CHANNEL_INFO *channel_info; |
| 230 | int dimm; |
| 231 | DIMM_INFO *dimm_info; |
| 232 | int dimm_max; |
| 233 | void *hob_list_ptr; |
| 234 | EFI_HOB_GUID_TYPE *hob_ptr; |
| 235 | int index; |
| 236 | struct memory_info *mem_info; |
| 237 | FSP_SMBIOS_MEMORY_INFO *memory_info_hob; |
| 238 | const EFI_GUID memory_info_hob_guid = FSP_SMBIOS_MEMORY_INFO_GUID; |
| 239 | |
| 240 | /* Locate the memory info HOB, presence validated by raminit */ |
| 241 | hob_list_ptr = fsp_get_hob_list(); |
| 242 | hob_ptr = get_next_guid_hob(&memory_info_hob_guid, hob_list_ptr); |
| 243 | memory_info_hob = (FSP_SMBIOS_MEMORY_INFO *)(hob_ptr + 1); |
| 244 | |
| 245 | /* Display the data in the FSP_SMBIOS_MEMORY_INFO HOB */ |
| 246 | if (IS_ENABLED(CONFIG_DISPLAY_HOBS)) { |
| 247 | printk(BIOS_DEBUG, "FSP_SMBIOS_MEMORY_INFO HOB\n"); |
| 248 | printk(BIOS_DEBUG, " 0x%02x: Revision\n", |
| 249 | memory_info_hob->Revision); |
| 250 | printk(BIOS_DEBUG, " 0x%02x: MemoryType\n", |
| 251 | memory_info_hob->MemoryType); |
Lee Leahy | 0be6d93 | 2015-06-26 11:15:42 -0700 | [diff] [blame] | 252 | printk(BIOS_DEBUG, " %d: MemoryFrequencyInMHz\n", |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 253 | memory_info_hob->MemoryFrequencyInMHz); |
Lee Leahy | 0be6d93 | 2015-06-26 11:15:42 -0700 | [diff] [blame] | 254 | printk(BIOS_DEBUG, " %d: DataWidth in bits\n", |
| 255 | memory_info_hob->DataWidth); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 256 | printk(BIOS_DEBUG, " 0x%02x: ErrorCorrectionType\n", |
| 257 | memory_info_hob->ErrorCorrectionType); |
| 258 | printk(BIOS_DEBUG, " 0x%02x: ChannelCount\n", |
| 259 | memory_info_hob->ChannelCount); |
| 260 | for (channel = 0; channel < memory_info_hob->ChannelCount; |
| 261 | channel++) { |
| 262 | channel_info = &memory_info_hob->ChannelInfo[channel]; |
| 263 | printk(BIOS_DEBUG, " Channel %d\n", channel); |
| 264 | printk(BIOS_DEBUG, " 0x%02x: ChannelId\n", |
| 265 | channel_info->ChannelId); |
| 266 | printk(BIOS_DEBUG, " 0x%02x: DimmCount\n", |
| 267 | channel_info->DimmCount); |
| 268 | for (dimm = 0; dimm < channel_info->DimmCount; |
| 269 | dimm++) { |
| 270 | dimm_info = &channel_info->DimmInfo[dimm]; |
| 271 | printk(BIOS_DEBUG, " DIMM %d\n", dimm); |
| 272 | printk(BIOS_DEBUG, " 0x%02x: DimmId\n", |
| 273 | dimm_info->DimmId); |
Lee Leahy | 0be6d93 | 2015-06-26 11:15:42 -0700 | [diff] [blame] | 274 | printk(BIOS_DEBUG, " %d: SizeInMb\n", |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 275 | dimm_info->SizeInMb); |
| 276 | } |
| 277 | } |
| 278 | } |
| 279 | |
| 280 | /* |
| 281 | * Allocate CBMEM area for DIMM information used to populate SMBIOS |
| 282 | * table 17 |
| 283 | */ |
| 284 | mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); |
| 285 | printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info); |
| 286 | if (mem_info == NULL) |
| 287 | return; |
| 288 | memset(mem_info, 0, sizeof(*mem_info)); |
| 289 | |
| 290 | /* Describe the first N DIMMs in the system */ |
| 291 | index = 0; |
| 292 | dimm_max = ARRAY_SIZE(mem_info->dimm); |
| 293 | for (channel = 0; channel < memory_info_hob->ChannelCount; channel++) { |
| 294 | if (index >= dimm_max) |
| 295 | break; |
| 296 | channel_info = &memory_info_hob->ChannelInfo[channel]; |
| 297 | for (dimm = 0; dimm < channel_info->DimmCount; dimm++) { |
| 298 | if (index >= dimm_max) |
| 299 | break; |
| 300 | dimm_info = &channel_info->DimmInfo[dimm]; |
| 301 | |
| 302 | /* Populate the DIMM information */ |
| 303 | if (dimm_info->SizeInMb) { |
| 304 | mem_info->dimm[index].dimm_size = |
| 305 | dimm_info->SizeInMb; |
| 306 | mem_info->dimm[index].ddr_type = |
| 307 | memory_info_hob->MemoryType; |
| 308 | mem_info->dimm[index].ddr_frequency = |
| 309 | memory_info_hob->MemoryFrequencyInMHz; |
| 310 | mem_info->dimm[index].channel_num = |
| 311 | channel_info->ChannelId; |
| 312 | mem_info->dimm[index].dimm_num = |
| 313 | dimm_info->DimmId; |
Lee Leahy | 0be6d93 | 2015-06-26 11:15:42 -0700 | [diff] [blame] | 314 | switch (memory_info_hob->DataWidth) { |
| 315 | default: |
| 316 | case 8: |
| 317 | mem_info->dimm[index].bus_width = |
| 318 | MEMORY_BUS_WIDTH_8; |
| 319 | break; |
| 320 | |
| 321 | case 16: |
| 322 | mem_info->dimm[index].bus_width = |
| 323 | MEMORY_BUS_WIDTH_16; |
| 324 | break; |
| 325 | |
| 326 | case 32: |
| 327 | mem_info->dimm[index].bus_width = |
| 328 | MEMORY_BUS_WIDTH_32; |
| 329 | break; |
| 330 | |
| 331 | case 64: |
| 332 | mem_info->dimm[index].bus_width = |
| 333 | MEMORY_BUS_WIDTH_64; |
| 334 | break; |
| 335 | |
| 336 | case 128: |
| 337 | mem_info->dimm[index].bus_width = |
| 338 | MEMORY_BUS_WIDTH_128; |
| 339 | break; |
| 340 | } |
Duncan Laurie | 46a2c77 | 2015-07-20 16:48:55 -0700 | [diff] [blame] | 341 | |
| 342 | /* Add any mainboard specific information */ |
| 343 | mainboard_add_dimm_info(params, mem_info, |
| 344 | channel, dimm, index); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 345 | index++; |
| 346 | } |
| 347 | } |
| 348 | } |
| 349 | mem_info->dimm_cnt = index; |
| 350 | printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); |
| 351 | } |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 352 | |
Duncan Laurie | 46a2c77 | 2015-07-20 16:48:55 -0700 | [diff] [blame] | 353 | /* Add any mainboard specific information */ |
| 354 | __attribute__((weak)) void mainboard_add_dimm_info( |
| 355 | struct romstage_params *params, |
| 356 | struct memory_info *mem_info, |
| 357 | int channel, int dimm, int index) |
| 358 | { |
Duncan Laurie | 46a2c77 | 2015-07-20 16:48:55 -0700 | [diff] [blame] | 359 | } |
| 360 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 361 | /* Get the memory configuration data */ |
Lee Leahy | d52f258 | 2016-05-31 18:12:53 -0700 | [diff] [blame] | 362 | __attribute__((weak)) int mrc_cache_get_current_with_version( |
| 363 | const struct mrc_saved_data **cache, uint32_t version) |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 364 | { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 365 | return -1; |
| 366 | } |
| 367 | |
| 368 | /* Save the memory configuration data */ |
Lee Leahy | d52f258 | 2016-05-31 18:12:53 -0700 | [diff] [blame] | 369 | __attribute__((weak)) int mrc_cache_stash_data_with_version(const void *data, |
| 370 | size_t size, uint32_t version) |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 371 | { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 372 | return -1; |
| 373 | } |
| 374 | |
| 375 | /* Transition RAM from off or self-refresh to active */ |
| 376 | __attribute__((weak)) void raminit(struct romstage_params *params) |
| 377 | { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 378 | post_code(0x34); |
| 379 | die("ERROR - No RAM initialization specified!\n"); |
| 380 | } |
| 381 | |
| 382 | void ramstage_cache_invalid(void) |
| 383 | { |
| 384 | if (IS_ENABLED(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE)) |
| 385 | /* Perform cold reset on invalid ramstage cache. */ |
| 386 | hard_reset(); |
| 387 | } |
| 388 | |
| 389 | /* Display the memory configuration */ |
| 390 | __attribute__((weak)) void report_memory_config(void) |
| 391 | { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 392 | } |
| 393 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 394 | /* Choose top of stack and setup MTRRs */ |
| 395 | __attribute__((weak)) void *setup_stack_and_mtrrs(void) |
| 396 | { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 397 | die("ERROR - Must specify top of stack!\n"); |
| 398 | return NULL; |
| 399 | } |
| 400 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 401 | /* SOC initialization after RAM is enabled */ |
| 402 | __attribute__((weak)) void soc_after_ram_init(struct romstage_params *params) |
| 403 | { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 404 | } |
| 405 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 406 | /* SOC initialization before RAM is enabled */ |
| 407 | __attribute__((weak)) void soc_pre_ram_init(struct romstage_params *params) |
| 408 | { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 409 | } |