blob: 384a2dbbccdf828335f13eb2f18d6932e83f4712 [file] [log] [blame]
Martin Rothd75800c2014-05-12 21:56:27 -06001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
15## You should have received a copy of the GNU General Public License
16## along with this program; if not, write to the Free Software
17## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18##
19
20if BOARD_INTEL_BAYLEYBAY_FSP
21
22config BOARD_SPECIFIC_OPTIONS # dummy
23 def_bool y
24 select SOC_INTEL_FSP_BAYTRAIL
25 select BOARD_ROMSIZE_KB_2048
26 select HAVE_ACPI_TABLES
27 select HAVE_OPTION_TABLE
Martin Rothd75800c2014-05-12 21:56:27 -060028 select OVERRIDE_MRC_CACHE_LOC
29 select POST_IO
30 select INCLUDE_MICROCODE_IN_BUILD if FSP_PACKAGE_DEFAULT
31 select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT
32 select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
33 select DEFAULT_CONSOLE_LOGLEVEL_7 if FSP_PACKAGE_DEFAULT
Edward O'Callaghanba924282014-06-27 12:13:30 +100034 select TSC_MONOTONIC_TIMER
Martin Rothd75800c2014-05-12 21:56:27 -060035
36config MAINBOARD_DIR
37 string
38 default "intel/bayleybay_fsp"
39
40config INCLUDE_ME
41 bool
42 default n
43
44config LOCK_MANAGEMENT_ENGINE
45 bool
46 default n
47
48config MAINBOARD_PART_NUMBER
49 string
Vladimir Serbinenko74116572014-10-24 19:30:06 +020050 default "Bayley Bay CRB (FSP)"
Martin Rothd75800c2014-05-12 21:56:27 -060051
Martin Rothd75800c2014-05-12 21:56:27 -060052config IRQ_SLOT_COUNT
53 int
54 default 18
55
56config MAX_CPUS
57 int
58 default 16
59
60config CACHE_ROM_SIZE_OVERRIDE
61 hex
62 default 0x800000
63
Martin Rothd75800c2014-05-12 21:56:27 -060064config FSP_FILE
65 string
66 default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd"
67
68config MRC_CACHE_LOC_OVERRIDE
69 hex
70 default 0xfff80000
Martin Rothd866e582014-06-11 09:35:37 -060071 depends on ENABLE_FSP_FAST_BOOT
Martin Rothd75800c2014-05-12 21:56:27 -060072
73config CBFS_SIZE
74 hex
75 default 0x00200000
76
77config DRIVERS_PS2_KEYBOARD
78 bool
79 default n
80
81config CONSOLE_POST
82 bool
83 default y
84
85config ENABLE_FSP_FAST_BOOT
86 bool
87 depends on HAVE_FSP_BIN
88 default y
89
90config VIRTUAL_ROM_SIZE
91 hex
92 depends on ENABLE_FSP_FAST_BOOT
93 default 0x800000
94
95config FSP_PACKAGE_DEFAULT
96 bool "Configure defaults for the Intel FSP package"
97 default n
98
99config VGA_BIOS
100 bool
101 default y if FSP_PACKAGE_DEFAULT
102
103endif # BOARD_INTEL_BAYLEYBAY_FSP