intel/bayleybay: Add Intel's Bayley Bay mainboard
Bay Trail-I Platform – Bayley Bay-I Customer Reference Board
The Bayley Bay CRB-I is a dual-channel DDR3L SO-DIMM non-ECC platform.
It is designed to support the Bay Trail-I SoC.
This implementation uses the Intel FSP (Vist the Intel FSP
website for details on FSP architecture and support).
This code does not currently support S3. All other features and IO
ports are functional. Booted on Ubuntu 14.04, Mint 16,
Fedora 20 with SeaBIOS payload. Memtest86, FWTS, and
other tests pass.
Notes:
- Generates a 2MB binary to be flashed to the upper 2MB of the ROM,
to preserve the existing Intel Flash Descriptor & TXE binary.
- Tested with B0 & B3 Baytrail I parts
Board support page will be updated on acceptance.
Change-Id: I80c836c7590f2dc25ec854e7a0bb939024cea600
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5792
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
diff --git a/src/mainboard/intel/bayleybay_fsp/Kconfig b/src/mainboard/intel/bayleybay_fsp/Kconfig
new file mode 100644
index 0000000..3372eb0
--- /dev/null
+++ b/src/mainboard/intel/bayleybay_fsp/Kconfig
@@ -0,0 +1,111 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+if BOARD_INTEL_BAYLEYBAY_FSP
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select SOC_INTEL_FSP_BAYTRAIL
+ select BOARD_ROMSIZE_KB_2048
+ select HAVE_ACPI_TABLES
+ select HAVE_OPTION_TABLE
+ select EARLY_CBMEM_INIT
+ select OVERRIDE_MRC_CACHE_LOC
+ select POST_IO
+ select INCLUDE_MICROCODE_IN_BUILD if FSP_PACKAGE_DEFAULT
+ select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT
+ select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
+ select DEFAULT_CONSOLE_LOGLEVEL_7 if FSP_PACKAGE_DEFAULT
+
+config MAINBOARD_DIR
+ string
+ default "intel/bayleybay_fsp"
+
+config INCLUDE_ME
+ bool
+ default n
+
+config LOCK_MANAGEMENT_ENGINE
+ bool
+ default n
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Bayley Bay CRB"
+
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xe0000000
+
+config IRQ_SLOT_COUNT
+ int
+ default 18
+
+config MAX_CPUS
+ int
+ default 16
+
+config CACHE_ROM_SIZE_OVERRIDE
+ hex
+ default 0x800000
+
+config FSP_LOC
+ hex
+ default 0xfffc0000
+
+config FSP_FILE
+ string
+ default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd"
+
+config MRC_CACHE_LOC_OVERRIDE
+ hex
+ default 0xfff80000
+ depends on ENABLE_FAST_BOOT
+
+config CBFS_SIZE
+ hex
+ default 0x00200000
+
+config DRIVERS_PS2_KEYBOARD
+ bool
+ default n
+
+config CONSOLE_POST
+ bool
+ default y
+
+config ENABLE_FSP_FAST_BOOT
+ bool
+ depends on HAVE_FSP_BIN
+ default y
+
+config VIRTUAL_ROM_SIZE
+ hex
+ depends on ENABLE_FSP_FAST_BOOT
+ default 0x800000
+
+config FSP_PACKAGE_DEFAULT
+ bool "Configure defaults for the Intel FSP package"
+ default n
+
+config VGA_BIOS
+ bool
+ default y if FSP_PACKAGE_DEFAULT
+
+endif # BOARD_INTEL_BAYLEYBAY_FSP