Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Imagination Technologies |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 17 | #include <arch/io.h> |
| 18 | #include <soc/ddr_init.h> |
Ionela Voinescu | 3fa1ad0 | 2015-04-05 17:55:51 +0100 | [diff] [blame] | 19 | #include <soc/ddr_private_reg.h> |
Ionela Voinescu | 1d4c305 | 2015-06-07 23:22:34 +0100 | [diff] [blame] | 20 | #include <stdint.h> |
Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 21 | |
Ionela Voinescu | 3fa1ad0 | 2015-04-05 17:55:51 +0100 | [diff] [blame] | 22 | #define BL8 0 |
Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 23 | |
| 24 | /* |
| 25 | * Configuration for the Winbond W972GG6JB-25 part using |
| 26 | * Synopsys DDR uMCTL and DDR Phy |
| 27 | */ |
| 28 | int init_ddr2(void) |
| 29 | { |
| 30 | |
Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 31 | /* |
| 32 | * Reset the AXI bridge and DDR Controller in case any spurious |
| 33 | * writes have already happened to DDR - note must be done together, |
| 34 | * not sequentially |
| 35 | */ |
| 36 | write32(TOPLEVEL_REGS + DDR_CTRL_OFFSET, 0x00000000); |
| 37 | write32(TOPLEVEL_REGS + DDR_CTRL_OFFSET, 0x0000000F); |
Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 38 | /* |
| 39 | * Dummy read to fence the access between the reset above |
| 40 | * and thw DDR controller writes below |
| 41 | */ |
| 42 | read32(TOPLEVEL_REGS + DDR_CTRL_OFFSET); |
Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 43 | /* Timings for 400MHz |
| 44 | * therefore 200MHz (5ns) uMCTL (Internal) Rate |
| 45 | */ |
Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 46 | /* TOGCNT1U: Toggle Counter 1U Register: 1us 200h C8h */ |
| 47 | write32(DDR_PCTL + DDR_PCTL_TOGCNT1U_OFFSET, 0x000000C8); |
| 48 | /* TINIT: t_init Timing Register: at least 200us 200h C8h */ |
| 49 | write32(DDR_PCTL + DDR_PCTL_TINIT_OFFSET, 0x000000C8); |
| 50 | /* TRSTH: Reset High Time Register DDR3 ONLY */ |
| 51 | write32(DDR_PCTL + DDR_PCTL_TRSTH_OFFSET, 0x00000000); |
| 52 | /* TOGCNT100N: Toggle Counter 100N Register: 20d, 14h*/ |
| 53 | write32(DDR_PCTL + DDR_PCTL_TOGG_CNTR_100NS_OFFSET, 0x00000014); |
| 54 | /* DTUAWDT DTU Address Width Register |
| 55 | * 1:0 column_addr_width Def 10 - 7 3 10 bits |
| 56 | * 4:3 bank_addr_width Def 3 - 2 1 3 bits (8 bank) |
| 57 | * 7:6 row_addr_width Def 14 - 13 1 3 bits |
| 58 | * 10:9 number_ranks Def 1 - 1 0 0 1 Rank |
| 59 | */ |
| 60 | write32(DDR_PCTL + DDR_PCTL_DTUAWDT_OFFSET, 0x0000004B); |
| 61 | /* MCFG |
| 62 | * 0 BL 0 = 4 1 = 8 |
| 63 | * 1 RDRIMM 0 |
| 64 | * 2 BL8 Burst Terminate 0 |
| 65 | * 3 2T = 0 |
| 66 | * 4 Multi Rank 0 |
| 67 | * 5 DDR3 En 0 |
| 68 | * 6 LPDDR S4 En |
| 69 | * 7 BST En 0, 1 for LPDDR2/3 |
| 70 | * 15:8 Power down Idle, passed by argument |
| 71 | * 16 Power Down Type, passed by argument |
| 72 | * 17 Power Down Exit 0 = slow, 1 = fast, pba |
| 73 | * 19:18 tFAW 45ns = 9 clk 5*2 -1 1h |
| 74 | * 21:20 mDDR/LPDDR2 BL 0 |
| 75 | * 23:22 mDDR/LPDDR2 Enable 0 |
| 76 | * 31:24 mDDR/LPDDR2/3 Dynamic Clock Stop 0 |
| 77 | */ |
| 78 | write32(DDR_PCTL + DDR_PCTL_MCFG_OFFSET, |
| 79 | 0x00060000 | (BL8 ? 0x1 : 0x0)); |
| 80 | /* MCFG1: Memory Configuration-1 Register |
| 81 | * c7:0 sr_idle Self Refresh Idle Entery 32 * nclks 14h, set 0 for BUB |
| 82 | * 10:8 Fine tune MCFG.19:18 -1 |
| 83 | * 15:11 Reserved |
| 84 | * 23:16 Hardware Idle Period NA 0 |
| 85 | * 30:24 Reserved |
| 86 | * 31 c_active_in_pin exit auto clk stop NA 0 |
| 87 | */ |
| 88 | write32(DDR_PCTL + DDR_PCTL_MCFG1_OFFSET, 0x00000100); |
| 89 | /* DCR DRAM Config |
| 90 | * 2:0 SDRAM => DDR2 2 |
| 91 | * 3 DDR 8 Bank 1 |
| 92 | * 6:4 Primary DQ DDR3 Only 0 |
| 93 | * 7 Multi-Purpose Register DDR3 Only 0 |
| 94 | * 9:8 DDRTYPE LPDDR2 00 |
| 95 | * 26:10 Reserved |
| 96 | * 27 NOSRA No Simultaneous Rank Access 0 |
| 97 | * 28 DDR 2T 0 |
| 98 | * 29 UDIMM NA 0 |
| 99 | * 30 RDIMM NA 0 |
| 100 | * 31 TPD LPDDR2 0 |
| 101 | */ |
| 102 | write32(DDR_PHY + DDRPHY_DCR_OFFSET, 0x0000000A); |
Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 103 | /* Generate to use with PHY and PCTL |
Ionela Voinescu | 59074ff | 2015-03-05 16:40:07 +0000 | [diff] [blame] | 104 | * MR0 : MR Register, bits 12:0 imported dfrom MR |
Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 105 | * 2:0 BL 8 011 |
| 106 | * 3 BT Sequential 0 Interleaved 1 = 0 |
| 107 | * 6:4 CL 6 |
| 108 | * 7 TM Normal 0 |
| 109 | * 8 DLL Reset 1 (self Clearing) |
| 110 | * 11:9 WR 15 ns 6 (101) |
| 111 | * 12 PD Slow 1 Fast 0 0 |
Ionela Voinescu | 59074ff | 2015-03-05 16:40:07 +0000 | [diff] [blame] | 112 | * 15:13 RSVD RSVD |
Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 113 | * 31:16 Reserved |
| 114 | */ |
Ionela Voinescu | 721f299 | 2015-05-26 12:20:19 +0100 | [diff] [blame^] | 115 | write32(DDR_PHY + DDRPHY_MR_OFFSET, 0x00000B62 | (BL8 ? 0x1 : 0x0)); |
Ionela Voinescu | 59074ff | 2015-03-05 16:40:07 +0000 | [diff] [blame] | 116 | /* MR1 : EMR Register |
| 117 | * Generate to use with PHY and PCTL |
Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 118 | * 0 DE DLL Enable 0 Disable 1 |
| 119 | * 1 DIC Output Driver Imp Ctl 0 Full, 1 Half |
Ionela Voinescu | 59074ff | 2015-03-05 16:40:07 +0000 | [diff] [blame] | 120 | * 6,2 ODT 0 Disable, 1 75R, 2 150R, 3 50R; LSB: 2, MSB: 6 |
Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 121 | * 5:3 AL = 0 |
| 122 | * 9:7 OCD = 0 |
| 123 | * 10 DQS 0 diff, 1 single = 0 |
| 124 | * 11 RDQS NA 0 |
| 125 | * 12 QOFF Normal mode 0 |
Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 126 | * 15:13 RSVD |
| 127 | * 31:16 Reserved |
| 128 | */ |
Ionela Voinescu | 51ad6ac | 2015-03-05 17:11:14 +0000 | [diff] [blame] | 129 | write32(DDR_PHY + DDRPHY_EMR_OFFSET, 0x00000044); |
Ionela Voinescu | 59074ff | 2015-03-05 16:40:07 +0000 | [diff] [blame] | 130 | /* MR2 : EMR2 Register |
| 131 | * Generate to use with PHY and PCTL |
Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 132 | * 2:0 PASR, NA 000 |
| 133 | * 3 DDC NA 0 |
| 134 | * 6:4 RSVD |
| 135 | * 7 SFR 0 |
Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 136 | * 15:8 RSVD |
| 137 | * 31:16 Reserved |
| 138 | */ |
Ionela Voinescu | 59074ff | 2015-03-05 16:40:07 +0000 | [diff] [blame] | 139 | write32(DDR_PHY + DDRPHY_EMR2_OFFSET, 0x00000000); |
Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 140 | /* DSGCR |
| 141 | * 0 PUREN Def 1 |
| 142 | * 1 BDISEN Def 1 |
| 143 | * 2 ZUEN Def 1 |
| 144 | * 3 LPIOPD DEf 1 0 |
| 145 | * 4 LPDLLPD DEf 1 0 |
Ionela Voinescu | 6b95406 | 2015-05-21 13:29:45 +0100 | [diff] [blame] | 146 | * 7:5 DQSGX DQS Extention set to 1 - advised by Synopsys |
| 147 | * 10:8 DQSGE DQS Early Gate - 1 - advised by Sysnopsys |
Ionela Voinescu | 5d997f9 | 2015-03-30 12:00:35 +0100 | [diff] [blame] | 148 | * 11 NOBUB No Bubbles, adds latency 1 |
Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 149 | * 12 FXDLAT Fixed Read Latency 0 |
| 150 | * 15:13 Reserved |
| 151 | * 19:16 CKEPDD CKE Power Down 0000 |
| 152 | * 23:20 ODTPDD ODT Power Down 0000 |
| 153 | * 24 NL2PD Power Down Non LPDDR2 pins 0 |
| 154 | * 25 NL2OE Output Enable Non LPDDR2 pins 1 |
| 155 | * 26 TPDPD LPDDR Only 0 |
| 156 | * 27 TPDOE LPDDR Only 0 |
| 157 | * 28 CKOE Output Enable Clk's 1 |
| 158 | * 29 ODTOE Output Enable ODT 1 |
| 159 | * 30 RSTOE RST# Output Enable 1 |
| 160 | * 31 CKEOE CKE Output Enable 1 |
| 161 | */ |
Ionela Voinescu | 6b95406 | 2015-05-21 13:29:45 +0100 | [diff] [blame] | 162 | write32(DDR_PHY + DDRPHY_DSGCR_OFFSET, 0xF2000927); |
| 163 | /* Sysnopsys advised 500R pullup/pulldown DQS DQSN */ |
| 164 | write32(DDR_PHY + DDRPHY_DXCCR_OFFSET, 0x00000C40); |
Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 165 | /* DTPR0 : DRAM Timing Params 0 |
| 166 | * 1:0 tMRD 2 |
| 167 | * 4:2 tRTP 3 |
| 168 | * 7:5 tWTR 3 |
| 169 | * 11:8 tRP 6 |
| 170 | * 15:12 tRCD 6 |
| 171 | * 20:16 tRAS 18 |
| 172 | * 24:21 tRRD 4 |
| 173 | * 30:25 tRC 24 (23) |
| 174 | * 31 tCCD 0 BL/2 Cas to Cas |
| 175 | */ |
| 176 | write32(DDR_PHY + DDRPHY_DTPR0_OFFSET, 0x3092666E); |
| 177 | /* DTPR1 : DRAM Timing Params 1 |
| 178 | * 1:0 ODT On/Off Del Std 0 |
| 179 | * 2 tRTW Rd2Wr Del 0 std 1 +1 0 |
| 180 | * 8:3 tFAW 4 Bank Act 45ns = 18 18 |
| 181 | * 10:9 tMOD DDR3 Only 0 |
| 182 | * 11 tRTODT DDR3 Only 0 |
| 183 | * 15:12 Reserved |
| 184 | * 23:16 tRFC 195ns 78 def 131 78d |
| 185 | * 26:24 tDQSCK LPDDR2 only 1 |
| 186 | * 29:27 tDQSCKmax 1 |
| 187 | * 31:30 Reserved |
| 188 | */ |
| 189 | write32(DDR_PHY + DDRPHY_DTPR1_OFFSET, 0x094E0092); |
| 190 | /* DTPR2 : DRAM Timing Params 2 |
| 191 | * 9:0 tXS exit SR def 200, 200d |
| 192 | * 14:10 tXP PD Exit Del 8 3 |
| 193 | * 18:15 tCKE CKE Min pulse 3 |
| 194 | * 28:19 tDLLK DLL Lock time 200d |
| 195 | * 32:29 Reserved |
| 196 | */ |
| 197 | write32(DDR_PHY + DDRPHY_DTPR2_OFFSET, 0x06418CC8); |
| 198 | /* PTR0 : PHY Timing Params 0 |
| 199 | * 5:0 tDLLRST Def 27 |
| 200 | * 17:6 tDLLLOCK Def 2750 |
| 201 | * 21:18 tITMSRST Def 8 |
| 202 | * 31:22 Reserved 0 |
| 203 | */ |
| 204 | write32(DDR_PHY + DDRPHY_PTR0_OFFSET, 0x0022AF9B); |
| 205 | /* PTR1 : PHY Timing Params 1 |
| 206 | * 18:0 : tDINITO DRAM Init time 200us 80,000 Dec 0x13880 |
| 207 | * 29:19 : tDINIT1 DRAM Init time 400ns 160 Dec 0xA0 |
| 208 | */ |
| 209 | write32(DDR_PHY + DDRPHY_PTR1_OFFSET, 0x05013880); |
Ionela Voinescu | 1185c10 | 2015-05-21 13:11:51 +0100 | [diff] [blame] | 210 | /* DQS gating configuration: passive windowing mode */ |
| 211 | /* |
| 212 | * PGCR: PHY General cofiguration register |
| 213 | * 0 ITM DDR mode: 0 |
| 214 | * 1 DQS gading configuration: passive windowing 1 |
| 215 | * 2 DQS drift compensation: not supported in passive windowing 0 |
| 216 | * 4:3 DQS drift limit 0 |
| 217 | * 8:5 Digital test output select 0 |
| 218 | * 11:9 CK Enable: one bit for each 3 CK pair: 0x7 |
| 219 | * 13:12 CK Disable values: 0x2 |
| 220 | * 14 CK Invert 0 |
| 221 | * 15 IO loopback 0 |
| 222 | * 17:16 I/O DDR mode 0 |
| 223 | * 21:18 Ranks enable by training: 0xF |
| 224 | * 23:22 Impedance clock divider select 0x2 |
| 225 | * 24 Power down disable 1 |
| 226 | * 28:25 Refresh during training 0 |
| 227 | * 29 loopback DQS shift 0 |
| 228 | * 30 loopback DQS gating 0 |
| 229 | * 31 loopback mode 0 |
| 230 | */ |
| 231 | write32(DDR_PHY + DDRPHY_PGCR_OFFSET, 0x01BC2E02); |
Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 232 | /* PGSR : Wait for INIT/DLL/Z Done from Power on Reset */ |
| 233 | if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x00000007)) |
| 234 | return DDR_TIMEOUT; |
Ionela Voinescu | 59074ff | 2015-03-05 16:40:07 +0000 | [diff] [blame] | 235 | /* PIR : use PHY for DRAM Init */ |
| 236 | write32(DDR_PHY + DDRPHY_PIR_OFFSET, 0x000001DF); |
| 237 | /* PGSR : Wait for DRAM Init Done */ |
| 238 | if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x0000001F)) |
Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 239 | return DDR_TIMEOUT; |
Ionela Voinescu | 6b95406 | 2015-05-21 13:29:45 +0100 | [diff] [blame] | 240 | /* Disable Impedance Calibration */ |
| 241 | write32(DDR_PHY + DDRPHY_ZQ0CR0_OFFSET, 0x3000014A); |
| 242 | write32(DDR_PHY + DDRPHY_ZQ1CR0_OFFSET, 0x3000014A); |
| 243 | |
Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 244 | /* DF1STAT0 : wait for DFI_INIT_COMPLETE */ |
| 245 | if (wait_for_completion(DDR_PCTL + DDR_PCTL_DFISTAT0_OFFSET, |
| 246 | 0x00000001)) |
| 247 | return DDR_TIMEOUT; |
Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 248 | /* POWCTL : Start the memory Power Up seq*/ |
| 249 | write32(DDR_PCTL + DDR_PCTL_POWCTL_OFFSET, 0x00000001); |
Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 250 | /* POWSTAT : wait for POWER_UP_DONE */ |
| 251 | if (wait_for_completion(DDR_PCTL + DDR_PCTL_POWSTAT_OFFSET, |
| 252 | 0x00000001)) |
| 253 | return DDR_TIMEOUT; |
Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 254 | /* |
| 255 | * TREFI : t_refi Timing Register 1X |
| 256 | * 12:0 t_refi 7.8us in 100ns 0x4E |
| 257 | * 15:13 Reserved 0 |
| 258 | * 18:16 num_add_ref 0 |
| 259 | * 30:19 Reserved 0 |
| 260 | * 31 Update 1 |
| 261 | */ |
| 262 | write32(DDR_PCTL + DDR_PCTL_TREFI_OFFSET, 0x8000004E); |
| 263 | /* TMRD : t_mrd Timing Register -- Range 2 to 3 */ |
| 264 | write32(DDR_PCTL + DDR_PCTL_TMRD_OFFSET, 0x00000002); |
| 265 | /* |
| 266 | * TRFC : t_rfc Timing Register -- Range 15 to 131 |
| 267 | * 195ns / 2.5ns 78 x4E |
| 268 | */ |
| 269 | write32(DDR_PCTL + DDR_PCTL_TRFC_OFFSET, 0x0000004E); |
| 270 | /* TRP : t_rp Timing Register -- Range 3 to 7 |
| 271 | * 4:0 tRP 12.5 / 2.5 = 5 6 For Now 6-6-6 |
| 272 | * 17:16 rpea_extra tRPall 8 bank 1 |
| 273 | */ |
| 274 | write32(DDR_PCTL + DDR_PCTL_TRP_OFFSET, 0x00010006); |
| 275 | /* TAL : Additive Latency Register -- AL in MR1 */ |
| 276 | write32(DDR_PCTL + DDR_PCTL_TAL_OFFSET, 0x00000000); |
| 277 | /* DFITPHYWRLAT : Write cmd to dfi_wrdata_en */ |
| 278 | write32(DDR_PCTL + DDR_PCTL_DFIWRLAT_OFFSET, 0x00000002); |
| 279 | /* DFITRDDATAEN : Read cmd to dfi_rddata_en */ |
| 280 | write32(DDR_PCTL + DDR_PCTL_DFITRDDATAEN_OFFSET, 0x00000002); |
| 281 | /* TCL : CAS Latency Timing Register -- CASL in MR0 6-6-6 */ |
| 282 | write32(DDR_PCTL + DDR_PCTL_TCL_OFFSET, 0x00000006); |
| 283 | /* TCWL : CAS Write Latency Register --CASL-1 */ |
| 284 | write32(DDR_PCTL + DDR_PCTL_TCWL_OFFSET, 0x00000005); |
| 285 | /* |
| 286 | * TRAS : Activate to Precharge cmd time |
| 287 | * Range 8 to 24: 45ns / 2.5ns = 18d |
| 288 | */ |
| 289 | write32(DDR_PCTL + DDR_PCTL_TRAS_OFFSET, 0x00000012); |
| 290 | /* |
| 291 | * TRC : Min. ROW cylce time |
| 292 | * Range 11 to 31: 57.5ns / 2.5ns = 23d Playing safe 24 |
| 293 | */ |
| 294 | write32(DDR_PCTL + DDR_PCTL_TRC_OFFSET, 0x00000018); |
| 295 | /* |
| 296 | * TRCD : Row to Column Delay |
| 297 | * Range 3 to 7 (TCL = TRCD): 2.5ns / 2.5ns = 5 but running 6-6-6 6 |
| 298 | */ |
| 299 | write32(DDR_PCTL + DDR_PCTL_TRCD_OFFSET, 0x00000006); |
| 300 | /* TRRD : Row to Row delay -- Range 2 to 6: 2K Page 10ns / 2.5ns = 4*/ |
| 301 | write32(DDR_PCTL + DDR_PCTL_TRRD_OFFSET, 0x00000004); |
| 302 | /* TRTP : Read to Precharge time -- Range 2 to 4: 7.3ns / 2.5ns = 3 */ |
| 303 | write32(DDR_PCTL + DDR_PCTL_TRTP_OFFSET, 0x00000003); |
| 304 | /* TWR : Write recovery time -- WR in MR0: 15ns / 2.5ns = 6 |
| 305 | */ |
| 306 | write32(DDR_PCTL + DDR_PCTL_TWR_OFFSET, 0x00000006); |
| 307 | /* |
| 308 | * TWTR : Write to read turn around time |
| 309 | * Range 2 to 4: 7.3ns / 2.5ns = 3 |
| 310 | */ |
| 311 | write32(DDR_PCTL + DDR_PCTL_TWTR_OFFSET, 0x00000003); |
| 312 | /* TEXSR : Exit Self Refresh to first valid cmd: tXS 200*/ |
| 313 | write32(DDR_PCTL + DDR_PCTL_TEXSR_OFFSET, 0x000000C8); |
| 314 | /* |
| 315 | * TXP : Exit Power Down to first valid cmd |
| 316 | * tXP 2, Settingto 3 to match PHY |
| 317 | */ |
| 318 | write32(DDR_PCTL + DDR_PCTL_TXP_OFFSET, 0x00000003); |
| 319 | /* |
| 320 | * TDQS : t_dqs Timing Register |
| 321 | * DQS additional turn around Rank 2 Rank (1 Rank) Def 1 |
| 322 | */ |
| 323 | write32(DDR_PCTL + DDR_PCTL_TDQS_OFFSET, 0x00000001); |
Ionela Voinescu | 6b95406 | 2015-05-21 13:29:45 +0100 | [diff] [blame] | 324 | /*TRTW : Read to Write turn around time Def 3 |
Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 325 | * Actual gap t_bl + t_rtw |
| 326 | */ |
Ionela Voinescu | 6b95406 | 2015-05-21 13:29:45 +0100 | [diff] [blame] | 327 | write32(DDR_PCTL + DDR_PCTL_TRTW_OFFSET, 0x00000003); |
Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 328 | /* TCKE : CKE min pulse width DEf 3 */ |
| 329 | write32(DDR_PCTL + DDR_PCTL_TCKE_OFFSET, 0x00000003); |
| 330 | /* |
| 331 | * TXPDLL : Slow Exit Power Down to first valid cmd delay |
| 332 | * tXARDS 10+AL = 10 |
| 333 | */ |
| 334 | write32(DDR_PCTL + DDR_PCTL_TXPDLL_OFFSET, 0x0000000A); |
| 335 | /* |
| 336 | * TCKESR : Min CKE Low width for Self refresh entry to exit |
| 337 | * t_ckesr = 0 DDR2 |
| 338 | */ |
| 339 | write32(DDR_PCTL + DDR_PCTL_TCKESR_OFFSET, 0x00000000); |
| 340 | /* SCFG : State Configuration Register (Enabling Self Refresh) |
| 341 | * 0 LP_en Leave Off for Bring Up 0 |
| 342 | * 5:1 Reserved |
| 343 | * 6 Synopsys Internal Only 0 |
| 344 | * 7 Enale PHY indication of LP Opportunity 1 |
| 345 | * 11:8 bbflags_timing max UPCTL_TCU_SED_P - tRP (16 - 6) Use 4 |
| 346 | * 16:12 Additional delay on accertion of ac_pdd 4 |
| 347 | * 31:17 Reserved |
| 348 | */ |
| 349 | write32(DDR_PCTL + DDR_PCTL_SCFG_OFFSET, 0x00004480); |
| 350 | /* |
| 351 | * DFITPHYWRDATA : dfi_wrdata_en to drive wr data |
| 352 | * DFI Clks wrdata_en to wrdata Def 1 |
| 353 | */ |
| 354 | write32(DDR_PCTL + DDR_PCTL_DFITPHYWRDATA_OFFSET, 0x00000000); |
| 355 | /* |
| 356 | * DFITPHYRDLAT : dfi_rddata_en to dfi_rddata_valid |
| 357 | * DFI clks max rddata_en to rddata_valid Def 15 |
| 358 | */ |
| 359 | write32(DDR_PCTL + DDR_PCTL_DFITPHYRDLAT_OFFSET, 0x00000008); |
| 360 | /* MCMD : PREA, Addr 0 Bank 0 Rank 0 Del 0 |
| 361 | * 3:0 cmd_opcode PREA 00001 |
| 362 | * 16:4 cmd_addr 0 |
| 363 | * 19:17 bank_addr 0 |
| 364 | * 23:20 rank_sel 0 0001 |
| 365 | * 27:24 cmddelay 0 |
| 366 | * 30:24 Reserved |
| 367 | */ |
| 368 | write32(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80100001); |
Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 369 | /* MRS cmd wait for completion */ |
| 370 | if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00100001)) |
| 371 | return DDR_TIMEOUT; |
Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 372 | /* SCTL : UPCTL switch INIT CONFIG State */ |
| 373 | write32(DDR_PCTL + DDR_PCTL_SCTL_OFFSET, 0x00000001); |
Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 374 | /* STAT : Wait for Switch INIT to Config State */ |
| 375 | if (wait_for_completion(DDR_PCTL + DDR_PCTL_STAT_OFFSET, 0x00000001)) |
| 376 | return DDR_TIMEOUT; |
Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 377 | /* DFISTCFG0 : Drive various DFI signals appropriately |
| 378 | * 0 dfi_init_start 0 |
| 379 | * 1 dfi_freq_ratio_en 1 |
| 380 | * 2 dfi_data_byte_disable_en 1 |
| 381 | */ |
| 382 | write32(DDR_PCTL + DDR_PCTL_DFISTCFG0_OFFSET, 0x00000003); |
| 383 | /* DFISTCFG1 : Enable various DFI support |
| 384 | * 0 dfi_dram_clk_disable_en 1 |
| 385 | * 1 dfi_dram_clk_disable_en_pdp only lPDDR 0 |
| 386 | */ |
| 387 | write32(DDR_PCTL + DDR_PCTL_DFISTCFG1_OFFSET, 0x00000001); |
| 388 | /* DFISTCFG2 : Enable Parity and asoc interrupt |
| 389 | * 0 dfi_parity_in Enable 1 |
| 390 | * 1 Interrupt on dfi_parity_error 1 |
| 391 | */ |
| 392 | write32(DDR_PCTL + DDR_PCTL_DFISTCFG2_OFFSET, 0x00000003); |
| 393 | /* DFILPCFG0 : DFI Low Power Interface Configuration |
| 394 | * 0 Enable DFI LP IF during PD 1 |
| 395 | * 3:1 Reserved |
| 396 | * 7:4 DFI tlp_wakeup time 0 |
| 397 | * 8 Enable DFI LP IF during SR 1 |
| 398 | * 11:9 Reserved |
| 399 | * 15:12 dfi_lp_wakeup in SR 0 |
| 400 | * 19:16 tlp_resp DFI 2.1 recomend 7 |
| 401 | * 23:20 Reserved |
| 402 | * 24 Enable DFI LP in Deep Power Down 0 |
| 403 | * 27:25 Reserved |
| 404 | * 31:28 DFI LP Deep Power Down Value 0 |
| 405 | */ |
| 406 | write32(DDR_PCTL + DDR_PCTL_DFILPCFG0_OFFSET, 0x00070101); |
| 407 | /* DFIODTCFG : DFI ODT Configuration |
| 408 | * Only Enabled on Rank0 Writes |
| 409 | * 0 rank0_odt_read_nsel 0 |
| 410 | * 1 rank0_odt_read_sel 0 |
| 411 | * 2 rank0_odt_write_nsel 0 |
| 412 | * 3 rank0_odt_write_sel 1 |
| 413 | */ |
| 414 | write32(DDR_PCTL + DDR_PCTL_DFIODTCFG_OFFSET, 0x00000008); |
Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 415 | /* DFIODTCFG1 : DFI ODT Configuration |
| 416 | * 4:0 odt_lat_w 4 |
| 417 | * 12:8 odt_lat_r 0 Def |
| 418 | * 4:0 odt_len_bl8_w 6 Def |
| 419 | * 12:8 odt_len_bl8_r 6 Def |
| 420 | */ |
| 421 | write32(DDR_PCTL + DDR_PCTL_DFIODTCFG1_OFFSET, 0x06060004); |
Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 422 | /* DCFG : DRAM Density 256 Mb 16 Bit IO Width |
| 423 | * 1:0 Devicw Width 1 x8, 2 x16, 3 x32 2 |
| 424 | * 5:2 Density 2Gb = 5 |
| 425 | * 6 Dram Type (MDDR/LPDDR2) Only 0 |
| 426 | * 7 Reserved 0 |
Ionela Voinescu | a2c4f9e | 2015-03-30 11:59:10 +0100 | [diff] [blame] | 427 | * 10:8 Address Map R/B/C = 1 |
Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 428 | * 31:11 Reserved |
| 429 | */ |
Ionela Voinescu | a2c4f9e | 2015-03-30 11:59:10 +0100 | [diff] [blame] | 430 | write32(DDR_PCTL + DDR_PCTL_DCFG_OFFSET, 0x00000116); |
Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 431 | /* PCFG_0 : Port 0 AXI config */ |
Ionela Voinescu | 59074ff | 2015-03-05 16:40:07 +0000 | [diff] [blame] | 432 | if (BL8) |
Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 433 | write32(DDR_PCTL + DDR_PCTL_PCFG0_OFFSET, 0x000800A0); |
| 434 | else |
| 435 | write32(DDR_PCTL + DDR_PCTL_PCFG0_OFFSET, 0x000400A0); |
Ionela Voinescu | d6aaca9 | 2015-01-19 01:03:44 +0000 | [diff] [blame] | 436 | /* SCTL : UPCTL switch Config to ACCESS State */ |
| 437 | write32(DDR_PCTL + DDR_PCTL_SCTL_OFFSET, 0x00000002); |
| 438 | /* STAT : Wait for switch CFG -> GO State */ |
| 439 | if (wait_for_completion(DDR_PCTL + DDR_PCTL_STAT_OFFSET, 0x3)) |
| 440 | return DDR_TIMEOUT; |
| 441 | |
| 442 | return 0; |
| 443 | } |