Angel Pons | 7c33942 | 2021-05-17 18:12:01 +0200 | [diff] [blame] | 1 | ## SPDX-License-Identifier: GPL-2.0-only |
| 2 | |
| 3 | chip northbridge/intel/sandybridge |
Keith Hui | 7039edd | 2023-07-21 10:12:05 -0400 | [diff] [blame^] | 4 | # All MRC-capable boards in family (P8Z77-M[ PRO]) lists supported |
| 5 | # DIMMs down to 1.25v |
| 6 | register "ddr3lv_support" = "1" |
| 7 | # FIXME: Nothing can run native at 800MHz on p8z77-m, others may have same problem |
| 8 | register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800" |
| 9 | |
| 10 | register "usb_port_config" = "{ |
| 11 | {1, 0, 0x0080}, {1, 0, 0x0080}, {1, 1, 0x0080}, {1, 1, 0x0080}, {1, 2, 0x0080}, |
| 12 | {1, 2, 0x0080}, {1, 3, 0x0080}, {1, 3, 0x0080}, {1, 4, 0x0080}, {1, 4, 0x0080}, |
| 13 | {1, 6, 0x0080}, {1, 5, 0x0080}, {1, 5, 0x0080}, {1, 6, 0x0080} |
| 14 | }" |
| 15 | # 4 bit switch mask. 0=not switchable, 1=switchable |
| 16 | # Means once it's loaded the OS, it can swap ports |
| 17 | # from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf |
| 18 | register "usb3.hs_port_switch_mask" = "0xf" |
| 19 | # (The other 3 usb3.* settings can be set from nvram options, and so are set |
| 20 | # from runtime code) |
| 21 | |
Angel Pons | 7c33942 | 2021-05-17 18:12:01 +0200 | [diff] [blame] | 22 | device domain 0 on |
Arthur Heymans | b5df65a | 2022-11-12 14:51:49 +0100 | [diff] [blame] | 23 | device ref host_bridge on end # Host bridge |
| 24 | device ref peg10 on end # PCIEX16_1 |
| 25 | device ref igd on end # iGPU |
Angel Pons | 7c33942 | 2021-05-17 18:12:01 +0200 | [diff] [blame] | 26 | |
| 27 | chip southbridge/intel/bd82x6x |
Angel Pons | 7c33942 | 2021-05-17 18:12:01 +0200 | [diff] [blame] | 28 | register "sata_interface_speed_support" = "0x3" |
| 29 | register "sata_port_map" = "0x3f" |
| 30 | register "spi_lvscc" = "0x2005" |
| 31 | register "spi_uvscc" = "0x2005" |
| 32 | register "superspeed_capable_ports" = "0x0000000f" |
| 33 | register "xhci_overcurrent_mapping" = "0x00000c03" |
| 34 | register "xhci_switchable_ports" = "0x0000000f" |
| 35 | |
Arthur Heymans | b5df65a | 2022-11-12 14:51:49 +0100 | [diff] [blame] | 36 | device ref xhci on end # xHCI |
| 37 | device ref mei1 on end # MEI #1 |
| 38 | device ref mei2 off end # MEI #2 |
| 39 | device ref me_ide_r off end # ME IDE-R |
| 40 | device ref me_kt off end # ME KT |
| 41 | device ref gbe off end # Intel GbE |
| 42 | device ref ehci2 on end # EHCI #2 |
| 43 | device ref hda on end # HD Audio |
Angel Pons | 7c33942 | 2021-05-17 18:12:01 +0200 | [diff] [blame] | 44 | |
Arthur Heymans | b5df65a | 2022-11-12 14:51:49 +0100 | [diff] [blame] | 45 | device ref pcie_rp1 off end # RP #1 |
| 46 | device ref pcie_rp2 off end # RP #2 |
| 47 | device ref pcie_rp3 off end # RP #3 |
| 48 | device ref pcie_rp4 off end # RP #4 |
| 49 | device ref pcie_rp5 off end # RP #5 |
| 50 | device ref pcie_rp6 off end # RP #6 |
| 51 | device ref pcie_rp7 off end # RP #7 |
| 52 | device ref pcie_rp8 off end # RP #8 |
Angel Pons | 7c33942 | 2021-05-17 18:12:01 +0200 | [diff] [blame] | 53 | |
Arthur Heymans | b5df65a | 2022-11-12 14:51:49 +0100 | [diff] [blame] | 54 | device ref ehci1 on end # EHCI #1 |
| 55 | device ref pci_bridge off end # PCI bridge |
| 56 | device ref lpc on # LPC bridge |
Angel Pons | 7c33942 | 2021-05-17 18:12:01 +0200 | [diff] [blame] | 57 | end |
Arthur Heymans | b5df65a | 2022-11-12 14:51:49 +0100 | [diff] [blame] | 58 | device ref sata1 on end # SATA (AHCI) |
| 59 | device ref smbus on end # SMBus |
| 60 | device ref sata2 off end # SATA (Legacy) |
| 61 | device ref thermal off end # Thermal |
Angel Pons | 7c33942 | 2021-05-17 18:12:01 +0200 | [diff] [blame] | 62 | end |
| 63 | end |
| 64 | end |