SNB+MRC boards: Migrate MRC settings to devicetree
For Sandy Bridge boards with MRC raminit support, migrate as much
MRC settings to devicetree as possible, to stop mainboard code from
needlessly overwriting entire PEI data structure, so they will not
interfere with upcoming transition to one standard Haswell way of
providing SPD info to northbridge.
Some exceptions allowed are described below and in code comments.
SPD-related items are kept out of devicetree for now. They will be
migrated (with a different representation) with the Haswell SPD
transition.
google/{butterfly,link,parrot,stout} have max DDR3 frequency set in
pei_data to 1600 (2*800), but in devicetree to 666. The reason for the
difference seems to be problems with native raminit code. These are
converted into ternaries tied to CONFIG_USE_NATIVE_RAMINIT, with an
added "fix me" tag. asus/p8x7x-series also needs the same treatment,
based on testing various memory on p8z77-m hardware.
TEST=Builds on all affected boards. asus/p8z77-m still works with multiple RAM modules tested.
Change-Id: Ie349a8f400eecca3cdbc196ea0790aebe0549e39
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
diff --git a/src/mainboard/asus/p8x7x-series/devicetree.cb b/src/mainboard/asus/p8x7x-series/devicetree.cb
index 0dc77f3..2913519 100644
--- a/src/mainboard/asus/p8x7x-series/devicetree.cb
+++ b/src/mainboard/asus/p8x7x-series/devicetree.cb
@@ -1,6 +1,24 @@
## SPDX-License-Identifier: GPL-2.0-only
chip northbridge/intel/sandybridge
+ # All MRC-capable boards in family (P8Z77-M[ PRO]) lists supported
+ # DIMMs down to 1.25v
+ register "ddr3lv_support" = "1"
+ # FIXME: Nothing can run native at 800MHz on p8z77-m, others may have same problem
+ register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800"
+
+ register "usb_port_config" = "{
+ {1, 0, 0x0080}, {1, 0, 0x0080}, {1, 1, 0x0080}, {1, 1, 0x0080}, {1, 2, 0x0080},
+ {1, 2, 0x0080}, {1, 3, 0x0080}, {1, 3, 0x0080}, {1, 4, 0x0080}, {1, 4, 0x0080},
+ {1, 6, 0x0080}, {1, 5, 0x0080}, {1, 5, 0x0080}, {1, 6, 0x0080}
+ }"
+ # 4 bit switch mask. 0=not switchable, 1=switchable
+ # Means once it's loaded the OS, it can swap ports
+ # from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf
+ register "usb3.hs_port_switch_mask" = "0xf"
+ # (The other 3 usb3.* settings can be set from nvram options, and so are set
+ # from runtime code)
+
device domain 0 on
device ref host_bridge on end # Host bridge
device ref peg10 on end # PCIEX16_1