- Implement an enable method for pci devices.
- Add initial support for the amd8131
- Update the mptable to something possible
- hdama/Config add the amd8131 southbridge
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@968 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c
index 25c39f8..d9ce9c5 100644
--- a/src/devices/pci_device.c
+++ b/src/devices/pci_device.c
@@ -572,23 +572,18 @@
continue;
}
memset(dev, 0, sizeof(*dev));
+ dev->bus = bus;
+ dev->devfn = devfn;
+ dev->vendor = id & 0xffff;
+ dev->device = (id >> 16) & 0xffff;
+ dev->hdr_type = hdr_type;
+ /* class code, the upper 3 bytes of PCI_CLASS_REVISION */
+ dev->class = class >> 8;
+
+ /* If we don't have prior information about this device enable it */
+ dev->enable = 1;
}
- dev->bus = bus;
- dev->devfn = devfn;
- dev->vendor = id & 0xffff;
- dev->device = (id >> 16) & 0xffff;
- dev->hdr_type = hdr_type;
- /* class code, the upper 3 bytes of PCI_CLASS_REVISION */
- dev->class = class >> 8;
-
- /* non-destructively determine if device can be a master: */
- cmd = pci_read_config8(dev, PCI_COMMAND);
- pci_write_config8(dev, PCI_COMMAND, cmd | PCI_COMMAND_MASTER);
- tmp = pci_read_config8(dev, PCI_COMMAND);
-
- dev->master = ((tmp & PCI_COMMAND_MASTER) != 0);
- pci_write_config8(dev, PCI_COMMAND, cmd);
/* Look at the vendor and device id, or at least the
* header type and class and figure out which set of configuration
@@ -600,9 +595,16 @@
free(dev);
continue;
}
- printk_debug("PCI: %02x:%02x.%01x [%04x/%04x]\n",
+
+ /* Now run the magic enable/disable sequence for the device */
+ if (dev->ops && dev->ops->enable) {
+ dev->ops->enable(dev);
+ }
+
+ printk_debug("PCI: %02x:%02x.%01x [%04x/%04x] %s\n",
bus->secondary, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
- dev->vendor, dev->device);
+ dev->vendor, dev->device,
+ dev->enable?"enabled": "disabled");
/* Put it into the global device chain. */
append_device(dev);