blob: 29252fec99de79026b2c51d59b508c32f5e7bf35 [file] [log] [blame]
Michael Niewöhner7f2aaac2019-09-19 09:22:04 +02001chip soc/intel/skylake
2
3 # GPE configuration
4 # Note that GPE events called out in ASL code rely on this
5 # route. i.e. If this route changes then the affected GPE
6 # offset bits also need to be changed.
7 register "gpe0_dw0" = "GPP_G"
8 register "gpe0_dw1" = "GPP_D"
9 register "gpe0_dw2" = "GPP_E"
10
11 register "gen1_dec" = "0x007c0a01" # Super IO SWC
12 register "gen2_dec" = "0x000c0ca1" # IPMI KCS
Michael Niewöhner7f2aaac2019-09-19 09:22:04 +020013
Felix Singer9a1b47e2023-10-23 17:37:21 +020014 register "usb2_ports" = "{
15 [0] = USB2_PORT_MID(OC3), /* USB 9 (3.0) */
16 [1] = USB2_PORT_MID(OC3), /* USB 8 (3.0) */
17 [2] = USB2_PORT_MID(OC1), /* USB 3 */
18 [3] = USB2_PORT_MID(OC1), /* USB 2 */
19 [4] = USB2_PORT_MID(OC2), /* USB 1 */
20 [5] = USB2_PORT_MID(OC2), /* USB 0 */
21 [6] = USB2_PORT_MID(OC0), /* USB 5 */
22 [7] = USB2_PORT_MID(OC0), /* USB 4 */
23 [8] = USB2_PORT_MID(OC_SKIP), /* IPMI USB HUB */
24 [9] = USB2_PORT_MID(OC5), /* USB 10 (3.0) */
25 [10] = USB2_PORT_MID(OC4), /* USB 7 (3.0) */
26 [11] = USB2_PORT_MID(OC4), /* USB 6 (3.0) */
27 }"
Michael Niewöhner7f2aaac2019-09-19 09:22:04 +020028
Felix Singer9a1b47e2023-10-23 17:37:21 +020029 register "usb3_ports" = "{
30 [0] = USB3_PORT_DEFAULT(OC4), /* USB 7 */
31 [1] = USB3_PORT_DEFAULT(OC4), /* USB 6 */
32 [2] = USB3_PORT_DEFAULT(OC5), /* USB 10 */
33 [3] = USB3_PORT_DEFAULT(OC3), /* USB 9 */
34 [4] = USB3_PORT_DEFAULT(OC3), /* USB 8 */
35 }"
Michael Niewöhner7f2aaac2019-09-19 09:22:04 +020036
37 device domain 0 on
Michael Niewöhner0bae5a72020-12-05 22:48:41 +010038 subsystemid 0x15d9 0x0896 inherit
Felix Singera03999b2023-10-23 09:01:05 +020039 device ref peg0 on
40 # Slot JPCIE6
Michael Niewöhner7f2aaac2019-09-19 09:22:04 +020041 smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "CPU SLOT6 PCI-E 3.0 X8(IN X16)" "SlotDataBusWidth8X"
42 end
Felix Singera03999b2023-10-23 09:01:05 +020043 device ref peg1 on
44 # Slot JPCIE7
Michael Niewöhner7f2aaac2019-09-19 09:22:04 +020045 smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT7 PCI-E 3.0 X8" "SlotDataBusWidth8X"
46 end
Felix Singera03999b2023-10-23 09:01:05 +020047 device ref pcie_rp1 on
48 # Slot JPCIE4
Michael Niewöhnerddd44f42020-11-24 01:23:28 +010049 register "PcieRpEnable[0]" = "1"
Michael Niewöhnerfb7a06b2020-11-24 22:47:44 +010050 register "PcieRpLtrEnable[0]" = "1"
Michael Niewöhner6bc12962020-12-05 23:00:03 +010051 register "PcieRpAdvancedErrorReporting[0]" = "1"
Michael Niewöhner7f2aaac2019-09-19 09:22:04 +020052 smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X"
53 end
Felix Singera03999b2023-10-23 09:01:05 +020054 device ref pcie_rp5 on
55 # Slot JPCIE5
Michael Niewöhnerddd44f42020-11-24 01:23:28 +010056 register "PcieRpEnable[4]" = "1"
Michael Niewöhnerfb7a06b2020-11-24 22:47:44 +010057 register "PcieRpLtrEnable[4]" = "1"
Michael Niewöhner6bc12962020-12-05 23:00:03 +010058 register "PcieRpAdvancedErrorReporting[4]" = "1"
Michael Niewöhner7f2aaac2019-09-19 09:22:04 +020059 smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT5 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X"
60 end
Felix Singera03999b2023-10-23 09:01:05 +020061 device ref pcie_rp9 on
Michael Niewöhnerddd44f42020-11-24 01:23:28 +010062 register "PcieRpEnable[8]" = "1"
Michael Niewöhnerfb7a06b2020-11-24 22:47:44 +010063 register "PcieRpLtrEnable[8]" = "1"
Michael Niewöhner6bc12962020-12-05 23:00:03 +010064 register "PcieRpAdvancedErrorReporting[8]" = "1"
Michael Niewöhner0bae5a72020-12-05 22:48:41 +010065 device pci 00.0 on # GbE 1
66 subsystemid 0x15d9 0x1533
67 end
Michael Niewöhner7f2aaac2019-09-19 09:22:04 +020068 end
Felix Singera03999b2023-10-23 09:01:05 +020069 device ref pcie_rp10 on
Michael Niewöhnerddd44f42020-11-24 01:23:28 +010070 register "PcieRpEnable[9]" = "1"
Michael Niewöhnerfb7a06b2020-11-24 22:47:44 +010071 register "PcieRpLtrEnable[9]" = "1"
Michael Niewöhner6bc12962020-12-05 23:00:03 +010072 register "PcieRpAdvancedErrorReporting[9]" = "1"
Michael Niewöhner0bae5a72020-12-05 22:48:41 +010073 device pci 00.0 on # GbE 2
74 subsystemid 0x15d9 0x1533
75 end
Michael Niewöhner7f2aaac2019-09-19 09:22:04 +020076 end
Felix Singera03999b2023-10-23 09:01:05 +020077 device ref pcie_rp11 on
Michael Niewöhnerddd44f42020-11-24 01:23:28 +010078 register "PcieRpEnable[10]" = "1"
Michael Niewöhnerfb7a06b2020-11-24 22:47:44 +010079 register "PcieRpLtrEnable[10]" = "1"
Michael Niewöhner6bc12962020-12-05 23:00:03 +010080 register "PcieRpAdvancedErrorReporting[10]" = "1"
Michael Niewöhner7f2aaac2019-09-19 09:22:04 +020081 device pci 00.0 on # Aspeed PCI Bridge
82 device pci 00.0 on end # Aspeed 2400 VGA
83 end
84 end
Felix Singera03999b2023-10-23 09:01:05 +020085 device ref lpc_espi on
Michael Niewöhner7f2aaac2019-09-19 09:22:04 +020086 chip drivers/ipmi
Michael Niewöhner961ceff2020-11-23 13:31:30 +010087 use pch_gpio as gpio_dev
88 register "bmc_jumper_gpio" = "GPP_D22" # JPB1
Michael Niewöhner8281a532020-11-08 19:32:13 +010089 register "post_complete_gpio" = "GPP_B20"
Michael Niewöhner7f2aaac2019-09-19 09:22:04 +020090 # On cold boot it takes a while for the BMC to start the IPMI service
91 register "wait_for_bmc" = "1"
92 register "bmc_boot_timeout" = "60"
93 device pnp ca2.0 on end # IPMI KCS
94 end
95 chip superio/common
96 device pnp 2e.0 on
97 chip superio/aspeed/ast2400
98 device pnp 2e.2 on # SUART1 / COM1 (ext)
99 io 0x60 = 0x3f8
100 irq 0x70 = 4
Michael Niewöhner1c8e4642020-02-23 22:51:05 +0100101 drq 0xf0 = 0x00
Michael Niewöhner7f2aaac2019-09-19 09:22:04 +0200102 end
103 device pnp 2e.3 on # SUART2 / COM2 (int)
104 io 0x60 = 0x2f8
105 irq 0x70 = 3
Michael Niewöhner1c8e4642020-02-23 22:51:05 +0100106 drq 0xf0 = 0x00
Michael Niewöhner7f2aaac2019-09-19 09:22:04 +0200107 end
108 device pnp 2e.4 on # SWC
109 io 0x60 = 0xa00
110 io 0x62 = 0xa10
111 io 0x64 = 0xa20
112 io 0x66 = 0xa30
Michael Niewöhner2a28c812020-07-25 23:47:44 +0200113 irq 0x70 = 0x00
Michael Niewöhner7f2aaac2019-09-19 09:22:04 +0200114 end
115 device pnp 2e.5 off end # KBC
Michael Niewöhner2a28c812020-07-25 23:47:44 +0200116 device pnp 2e.7 on # GPIO
117 irq 0x70 = 0x00
118 end
Michael Niewöhner68241732020-02-10 19:21:22 +0100119 device pnp 2e.b off end # SUART3
120 device pnp 2e.c off end # SUART4
Michael Niewöhner2a28c812020-07-25 23:47:44 +0200121 device pnp 2e.d on # iLPC2AHB
122 irq 0x70 = 0x00
123 end
Michael Niewöhner7f2aaac2019-09-19 09:22:04 +0200124 device pnp 2e.e on # Mailbox
125 io 0x60 = 0xa40
126 irq 0x70 = 0x00
127 end
128 end
129 end
130 end
131 end
132 end
133end