Michael Niewöhner | 7f2aaac | 2019-09-19 09:22:04 +0200 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
| 3 | # GPE configuration |
| 4 | # Note that GPE events called out in ASL code rely on this |
| 5 | # route. i.e. If this route changes then the affected GPE |
| 6 | # offset bits also need to be changed. |
| 7 | register "gpe0_dw0" = "GPP_G" |
| 8 | register "gpe0_dw1" = "GPP_D" |
| 9 | register "gpe0_dw2" = "GPP_E" |
| 10 | |
| 11 | register "gen1_dec" = "0x007c0a01" # Super IO SWC |
| 12 | register "gen2_dec" = "0x000c0ca1" # IPMI KCS |
Michael Niewöhner | 7f2aaac | 2019-09-19 09:22:04 +0200 | [diff] [blame] | 13 | |
Michael Niewöhner | 7f2aaac | 2019-09-19 09:22:04 +0200 | [diff] [blame] | 14 | # USB configuration |
| 15 | # USB0/1 |
| 16 | register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" |
| 17 | register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" |
| 18 | |
| 19 | # USB2/3 |
| 20 | register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" |
| 21 | register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" |
| 22 | |
| 23 | # USB4/5 |
| 24 | register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" |
| 25 | register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" |
| 26 | |
| 27 | # USB6/7 (USB3.0) |
| 28 | register "usb2_ports[11]" = "USB2_PORT_MID(OC4)" |
| 29 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)" |
| 30 | register "usb2_ports[10]" = "USB2_PORT_MID(OC4)" |
| 31 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC4)" |
| 32 | |
| 33 | # USB8/9 (USB3.0) |
| 34 | register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" |
| 35 | register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" |
| 36 | register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" |
| 37 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" |
| 38 | |
| 39 | # USB10 (USB3.0) |
| 40 | register "usb2_ports[9]" = "USB2_PORT_MID(OC5)" |
| 41 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC5)" |
| 42 | |
| 43 | # IPMI USB HUB |
| 44 | register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" |
| 45 | |
| 46 | device domain 0 on |
Michael Niewöhner | 0bae5a7 | 2020-12-05 22:48:41 +0100 | [diff] [blame] | 47 | subsystemid 0x15d9 0x0896 inherit |
Michael Niewöhner | 7f2aaac | 2019-09-19 09:22:04 +0200 | [diff] [blame] | 48 | device pci 01.0 on # CPU PCIe Port (x16) / PCIe Slot 6 (JPCIE6) |
| 49 | smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "CPU SLOT6 PCI-E 3.0 X8(IN X16)" "SlotDataBusWidth8X" |
| 50 | end |
| 51 | device pci 01.1 on # CPU PCIe Port (x8) / PCIe Slot 7 (JPCIE7) |
| 52 | smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT7 PCI-E 3.0 X8" "SlotDataBusWidth8X" |
| 53 | end |
| 54 | device pci 1c.0 on # PCH PCIe Port 1 / PCIe Slot 4 (JPCIE4) |
Michael Niewöhner | ddd44f4 | 2020-11-24 01:23:28 +0100 | [diff] [blame] | 55 | register "PcieRpEnable[0]" = "1" |
Michael Niewöhner | fb7a06b | 2020-11-24 22:47:44 +0100 | [diff] [blame] | 56 | register "PcieRpLtrEnable[0]" = "1" |
Michael Niewöhner | 6bc1296 | 2020-12-05 23:00:03 +0100 | [diff] [blame] | 57 | register "PcieRpAdvancedErrorReporting[0]" = "1" |
Michael Niewöhner | 7f2aaac | 2019-09-19 09:22:04 +0200 | [diff] [blame] | 58 | smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" |
| 59 | end |
| 60 | device pci 1c.4 on # PCH PCIe Port 5 / PCIe Slot 5 (JPCIE5) |
Michael Niewöhner | ddd44f4 | 2020-11-24 01:23:28 +0100 | [diff] [blame] | 61 | register "PcieRpEnable[4]" = "1" |
Michael Niewöhner | fb7a06b | 2020-11-24 22:47:44 +0100 | [diff] [blame] | 62 | register "PcieRpLtrEnable[4]" = "1" |
Michael Niewöhner | 6bc1296 | 2020-12-05 23:00:03 +0100 | [diff] [blame] | 63 | register "PcieRpAdvancedErrorReporting[4]" = "1" |
Michael Niewöhner | 7f2aaac | 2019-09-19 09:22:04 +0200 | [diff] [blame] | 64 | smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT5 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" |
| 65 | end |
| 66 | device pci 1d.0 on # PCH PCIe Port 9 |
Michael Niewöhner | ddd44f4 | 2020-11-24 01:23:28 +0100 | [diff] [blame] | 67 | register "PcieRpEnable[8]" = "1" |
Michael Niewöhner | fb7a06b | 2020-11-24 22:47:44 +0100 | [diff] [blame] | 68 | register "PcieRpLtrEnable[8]" = "1" |
Michael Niewöhner | 6bc1296 | 2020-12-05 23:00:03 +0100 | [diff] [blame] | 69 | register "PcieRpAdvancedErrorReporting[8]" = "1" |
Michael Niewöhner | 0bae5a7 | 2020-12-05 22:48:41 +0100 | [diff] [blame] | 70 | device pci 00.0 on # GbE 1 |
| 71 | subsystemid 0x15d9 0x1533 |
| 72 | end |
Michael Niewöhner | 7f2aaac | 2019-09-19 09:22:04 +0200 | [diff] [blame] | 73 | end |
| 74 | device pci 1d.1 on # PCH PCIe Port 10 |
Michael Niewöhner | ddd44f4 | 2020-11-24 01:23:28 +0100 | [diff] [blame] | 75 | register "PcieRpEnable[9]" = "1" |
Michael Niewöhner | fb7a06b | 2020-11-24 22:47:44 +0100 | [diff] [blame] | 76 | register "PcieRpLtrEnable[9]" = "1" |
Michael Niewöhner | 6bc1296 | 2020-12-05 23:00:03 +0100 | [diff] [blame] | 77 | register "PcieRpAdvancedErrorReporting[9]" = "1" |
Michael Niewöhner | 0bae5a7 | 2020-12-05 22:48:41 +0100 | [diff] [blame] | 78 | device pci 00.0 on # GbE 2 |
| 79 | subsystemid 0x15d9 0x1533 |
| 80 | end |
Michael Niewöhner | 7f2aaac | 2019-09-19 09:22:04 +0200 | [diff] [blame] | 81 | end |
| 82 | device pci 1d.2 on # PCH PCIe Port 11 |
Michael Niewöhner | ddd44f4 | 2020-11-24 01:23:28 +0100 | [diff] [blame] | 83 | register "PcieRpEnable[10]" = "1" |
Michael Niewöhner | fb7a06b | 2020-11-24 22:47:44 +0100 | [diff] [blame] | 84 | register "PcieRpLtrEnable[10]" = "1" |
Michael Niewöhner | 6bc1296 | 2020-12-05 23:00:03 +0100 | [diff] [blame] | 85 | register "PcieRpAdvancedErrorReporting[10]" = "1" |
Michael Niewöhner | 7f2aaac | 2019-09-19 09:22:04 +0200 | [diff] [blame] | 86 | device pci 00.0 on # Aspeed PCI Bridge |
| 87 | device pci 00.0 on end # Aspeed 2400 VGA |
| 88 | end |
| 89 | end |
| 90 | device pci 1f.0 on # LPC Interface |
| 91 | chip drivers/ipmi |
Michael Niewöhner | 961ceff | 2020-11-23 13:31:30 +0100 | [diff] [blame] | 92 | use pch_gpio as gpio_dev |
| 93 | register "bmc_jumper_gpio" = "GPP_D22" # JPB1 |
Michael Niewöhner | 8281a53 | 2020-11-08 19:32:13 +0100 | [diff] [blame^] | 94 | register "post_complete_gpio" = "GPP_B20" |
Michael Niewöhner | 7f2aaac | 2019-09-19 09:22:04 +0200 | [diff] [blame] | 95 | # On cold boot it takes a while for the BMC to start the IPMI service |
| 96 | register "wait_for_bmc" = "1" |
| 97 | register "bmc_boot_timeout" = "60" |
| 98 | device pnp ca2.0 on end # IPMI KCS |
| 99 | end |
| 100 | chip superio/common |
| 101 | device pnp 2e.0 on |
| 102 | chip superio/aspeed/ast2400 |
| 103 | device pnp 2e.2 on # SUART1 / COM1 (ext) |
| 104 | io 0x60 = 0x3f8 |
| 105 | irq 0x70 = 4 |
Michael Niewöhner | 1c8e464 | 2020-02-23 22:51:05 +0100 | [diff] [blame] | 106 | drq 0xf0 = 0x00 |
Michael Niewöhner | 7f2aaac | 2019-09-19 09:22:04 +0200 | [diff] [blame] | 107 | end |
| 108 | device pnp 2e.3 on # SUART2 / COM2 (int) |
| 109 | io 0x60 = 0x2f8 |
| 110 | irq 0x70 = 3 |
Michael Niewöhner | 1c8e464 | 2020-02-23 22:51:05 +0100 | [diff] [blame] | 111 | drq 0xf0 = 0x00 |
Michael Niewöhner | 7f2aaac | 2019-09-19 09:22:04 +0200 | [diff] [blame] | 112 | end |
| 113 | device pnp 2e.4 on # SWC |
| 114 | io 0x60 = 0xa00 |
| 115 | io 0x62 = 0xa10 |
| 116 | io 0x64 = 0xa20 |
| 117 | io 0x66 = 0xa30 |
Michael Niewöhner | 2a28c81 | 2020-07-25 23:47:44 +0200 | [diff] [blame] | 118 | irq 0x70 = 0x00 |
Michael Niewöhner | 7f2aaac | 2019-09-19 09:22:04 +0200 | [diff] [blame] | 119 | end |
| 120 | device pnp 2e.5 off end # KBC |
Michael Niewöhner | 2a28c81 | 2020-07-25 23:47:44 +0200 | [diff] [blame] | 121 | device pnp 2e.7 on # GPIO |
| 122 | irq 0x70 = 0x00 |
| 123 | end |
Michael Niewöhner | 6824173 | 2020-02-10 19:21:22 +0100 | [diff] [blame] | 124 | device pnp 2e.b off end # SUART3 |
| 125 | device pnp 2e.c off end # SUART4 |
Michael Niewöhner | 2a28c81 | 2020-07-25 23:47:44 +0200 | [diff] [blame] | 126 | device pnp 2e.d on # iLPC2AHB |
| 127 | irq 0x70 = 0x00 |
| 128 | end |
Michael Niewöhner | 7f2aaac | 2019-09-19 09:22:04 +0200 | [diff] [blame] | 129 | device pnp 2e.e on # Mailbox |
| 130 | io 0x60 = 0xa40 |
| 131 | irq 0x70 = 0x00 |
| 132 | end |
| 133 | end |
| 134 | end |
| 135 | end |
| 136 | end |
| 137 | end |
| 138 | end |