Michael Niewöhner | 7f2aaac | 2019-09-19 09:22:04 +0200 | [diff] [blame^] | 1 | chip soc/intel/skylake |
| 2 | |
| 3 | # GPE configuration |
| 4 | # Note that GPE events called out in ASL code rely on this |
| 5 | # route. i.e. If this route changes then the affected GPE |
| 6 | # offset bits also need to be changed. |
| 7 | register "gpe0_dw0" = "GPP_G" |
| 8 | register "gpe0_dw1" = "GPP_D" |
| 9 | register "gpe0_dw2" = "GPP_E" |
| 10 | |
| 11 | register "gen1_dec" = "0x007c0a01" # Super IO SWC |
| 12 | register "gen2_dec" = "0x000c0ca1" # IPMI KCS |
| 13 | register "gen3_dec" = "0x000c03e1" # UART3 |
| 14 | register "gen4_dec" = "0x000c02e1" # UART4 |
| 15 | |
| 16 | # PCIe configuration |
| 17 | register "PcieRpEnable[0]" = "1" # Enable PCH PCIe Port 1 / PCH SLOT4 |
| 18 | register "PcieRpEnable[4]" = "1" # Enable PCH PCIe Port 5 / PCH SLOT5 |
| 19 | register "PcieRpEnable[8]" = "1" # Enable PCH PCIe Port 9 / GbE 1 |
| 20 | register "PcieRpEnable[9]" = "1" # Enable PCH PCIe Port 10 / GbE 2 |
| 21 | register "PcieRpEnable[10]" = "1" # Enable PCH PCIe Port 11 / Aspeed 2400 VGA |
| 22 | |
| 23 | # USB configuration |
| 24 | # USB0/1 |
| 25 | register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" |
| 26 | register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" |
| 27 | |
| 28 | # USB2/3 |
| 29 | register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" |
| 30 | register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" |
| 31 | |
| 32 | # USB4/5 |
| 33 | register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" |
| 34 | register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" |
| 35 | |
| 36 | # USB6/7 (USB3.0) |
| 37 | register "usb2_ports[11]" = "USB2_PORT_MID(OC4)" |
| 38 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)" |
| 39 | register "usb2_ports[10]" = "USB2_PORT_MID(OC4)" |
| 40 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC4)" |
| 41 | |
| 42 | # USB8/9 (USB3.0) |
| 43 | register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" |
| 44 | register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" |
| 45 | register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" |
| 46 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" |
| 47 | |
| 48 | # USB10 (USB3.0) |
| 49 | register "usb2_ports[9]" = "USB2_PORT_MID(OC5)" |
| 50 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC5)" |
| 51 | |
| 52 | # IPMI USB HUB |
| 53 | register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" |
| 54 | |
| 55 | device domain 0 on |
| 56 | device pci 01.0 on # CPU PCIe Port (x16) / PCIe Slot 6 (JPCIE6) |
| 57 | smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "CPU SLOT6 PCI-E 3.0 X8(IN X16)" "SlotDataBusWidth8X" |
| 58 | end |
| 59 | device pci 01.1 on # CPU PCIe Port (x8) / PCIe Slot 7 (JPCIE7) |
| 60 | smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT7 PCI-E 3.0 X8" "SlotDataBusWidth8X" |
| 61 | end |
| 62 | device pci 1c.0 on # PCH PCIe Port 1 / PCIe Slot 4 (JPCIE4) |
| 63 | smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" |
| 64 | end |
| 65 | device pci 1c.4 on # PCH PCIe Port 5 / PCIe Slot 5 (JPCIE5) |
| 66 | smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT5 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" |
| 67 | end |
| 68 | device pci 1d.0 on # PCH PCIe Port 9 |
| 69 | device pci 00.0 on end # GbE 1 |
| 70 | end |
| 71 | device pci 1d.1 on # PCH PCIe Port 10 |
| 72 | device pci 00.1 on end # GbE 2 |
| 73 | end |
| 74 | device pci 1d.2 on # PCH PCIe Port 11 |
| 75 | device pci 00.0 on # Aspeed PCI Bridge |
| 76 | device pci 00.0 on end # Aspeed 2400 VGA |
| 77 | end |
| 78 | end |
| 79 | device pci 1f.0 on # LPC Interface |
| 80 | chip drivers/ipmi |
| 81 | # On cold boot it takes a while for the BMC to start the IPMI service |
| 82 | register "wait_for_bmc" = "1" |
| 83 | register "bmc_boot_timeout" = "60" |
| 84 | device pnp ca2.0 on end # IPMI KCS |
| 85 | end |
| 86 | chip superio/common |
| 87 | device pnp 2e.0 on |
| 88 | chip superio/aspeed/ast2400 |
| 89 | device pnp 2e.2 on # SUART1 / COM1 (ext) |
| 90 | io 0x60 = 0x3f8 |
| 91 | irq 0x70 = 4 |
| 92 | end |
| 93 | device pnp 2e.3 on # SUART2 / COM2 (int) |
| 94 | io 0x60 = 0x2f8 |
| 95 | irq 0x70 = 3 |
| 96 | end |
| 97 | device pnp 2e.4 on # SWC |
| 98 | io 0x60 = 0xa00 |
| 99 | io 0x62 = 0xa10 |
| 100 | io 0x64 = 0xa20 |
| 101 | io 0x66 = 0xa30 |
| 102 | irq 0x70 = 0xb |
| 103 | end |
| 104 | device pnp 2e.5 off end # KBC |
| 105 | device pnp 2e.7 on end # GPIO |
| 106 | device pnp 2e.b on # SUART3 |
| 107 | io 0x60 = 0x3e8 |
| 108 | irq 0x70 = 4 |
| 109 | end |
| 110 | device pnp 2e.c on # SUART4 |
| 111 | io 0x60 = 0x2e8 |
| 112 | irq 0x70 = 3 |
| 113 | end |
| 114 | device pnp 2e.d on end # iLPC2AHB |
| 115 | device pnp 2e.e on # Mailbox |
| 116 | io 0x60 = 0xa40 |
| 117 | irq 0x70 = 0x00 |
| 118 | end |
| 119 | end |
| 120 | end |
| 121 | end |
| 122 | end |
| 123 | end |
| 124 | end |