Ionela Voinescu | 3fa1ad0 | 2015-04-05 17:55:51 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Imagination Technologies |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Ionela Voinescu | 3fa1ad0 | 2015-04-05 17:55:51 +0100 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <stdint.h> |
| 18 | #include <arch/io.h> |
| 19 | #include <soc/ddr_init.h> |
| 20 | #include <soc/ddr_private_reg.h> |
| 21 | |
| 22 | /* |
| 23 | * Configuration for the Winbond W631GG6KB part using |
| 24 | * Synopsys DDR uMCTL and DDR Phy |
| 25 | */ |
| 26 | int init_ddr3(void) |
| 27 | { |
| 28 | uint32_t temp_rw_val; |
| 29 | |
| 30 | temp_rw_val = read32(TOPLEVEL_REGS + DDR_CTRL_OFFSET); |
| 31 | /* Set CLK_EN = 1 */ |
| 32 | temp_rw_val |= 0x2; |
| 33 | write32(TOPLEVEL_REGS + DDR_CTRL_OFFSET, temp_rw_val); |
| 34 | read32(TOPLEVEL_REGS + DDR_CTRL_OFFSET); |
| 35 | /* |
| 36 | * Reset the AXI bridge and DDR Controller in case any spurious |
| 37 | * writes have already happened to DDR |
| 38 | */ |
| 39 | /* Drive the 3 resets low */ |
| 40 | write32(TOPLEVEL_REGS + DDR_CTRL_OFFSET, 0x00000002); |
| 41 | read32(TOPLEVEL_REGS + DDR_CTRL_OFFSET); |
| 42 | read32(TOPLEVEL_REGS + DDR_CTRL_OFFSET); |
| 43 | |
| 44 | /* And release */ |
| 45 | write32(TOPLEVEL_REGS + DDR_CTRL_OFFSET, 0x0000000F); |
| 46 | /* Dummy read to fence the access between the reset above and |
| 47 | * the DDR controller writes below |
| 48 | */ |
| 49 | read32(TOPLEVEL_REGS + DDR_CTRL_OFFSET); |
| 50 | |
| 51 | /* Timings for 400MHz |
| 52 | * therefore 200MHz (5ns) uMCTL (Internal) Rate |
| 53 | */ |
| 54 | /* TOGCNT1U: Toggle Counter 1U Register: 1us 200h C8h */ |
| 55 | write32(DDR_PCTL + DDR_PCTL_TOGCNT1U_OFFSET, 0x000000C8); |
| 56 | /* TINIT: t_init Timing Register: at least 200us 200h C8h */ |
| 57 | write32(DDR_PCTL + DDR_PCTL_TINIT_OFFSET, 0x000000C8); |
| 58 | /* TRSTH: Reset High Time Register DDR3 ONLY */ |
| 59 | write32(DDR_PCTL + DDR_PCTL_TRSTH_OFFSET, 0x000001F4); |
| 60 | /* TOGCNT100N: Toggle Counter 100N Register: 20d, 14h*/ |
| 61 | write32(DDR_PCTL + DDR_PCTL_TOGG_CNTR_100NS_OFFSET, 0x00000014); |
| 62 | /* DTUAWDT DTU Address Width Register |
| 63 | * 1:0 column_addr_width Def 10 - 7 3 10 bits |
| 64 | * 4:3 bank_addr_width Def 3 - 2 1 3 bits (8 bank) |
| 65 | * 7:6 row_addr_width Def 14 - 13 1 3 bits |
| 66 | * 10:9 number_ranks Def 1 - 1 0 0 1 Rank |
| 67 | */ |
| 68 | write32(DDR_PCTL + DDR_PCTL_DTUAWDT_OFFSET, 0x0000004B); |
| 69 | /* MCFG |
| 70 | * 0 BL 1 -> 8 fixed |
| 71 | * 1 RDRIMM 0 |
| 72 | * 2 BL8 Burst Terminate 0 |
| 73 | * 3 2T = 0 |
| 74 | * 4 Multi Rank 0 |
| 75 | * 5 DDR3 En 1 |
| 76 | * 6 LPDDR S4 En |
| 77 | * 7 BST En 0, 1 for LPDDR2/3 |
| 78 | * 15:8 Power down Idle, passed by argument |
| 79 | * 16 Power Down Type, passed by argument |
| 80 | * 17 Power Down Exit 0 = slow, 1 = fast, pba |
| 81 | * 19:18 tFAW 45ns = 9 clk 5*2 -1 1h |
| 82 | * 21:20 mDDR/LPDDR2 BL 0 |
| 83 | * 23:22 mDDR/LPDDR2 Enable 0 |
| 84 | * 31:24 mDDR/LPDDR2/3 Dynamic Clock Stop 0 |
| 85 | */ |
| 86 | write32(DDR_PCTL + DDR_PCTL_MCFG_OFFSET, 0x00060021); |
| 87 | /* MCFG1: Memory Configuration-1 Register |
| 88 | * c7:0 sr_idle Self Refresh Idle Entery 32 * nclks 14h, set 0 for BUB |
| 89 | * 10:8 Fine tune MCFG.19:18 -1 |
| 90 | * 15:11 Reserved |
| 91 | * 23:16 Hardware Idle Period NA 0 |
| 92 | * 30:24 Reserved |
| 93 | * 31 c_active_in_pin exit auto clk stop NA 0 |
| 94 | */ |
| 95 | write32(DDR_PCTL + DDR_PCTL_MCFG1_OFFSET, 0x00000100); |
| 96 | /* DCR DRAM Config |
| 97 | * 2:0 SDRAM => DDR3 3 |
| 98 | * 3 DDR 8 Bank 1 |
| 99 | * 6:4 Primary DQ DDR3 Only 0 |
| 100 | * 7 Multi-Purpose Register DDR3 Only 0 |
| 101 | * 9:8 DDRTYPE LPDDR2 00 |
| 102 | * 26:10 Reserved |
| 103 | * 27 NOSRA No Simultaneous Rank Access 0 |
| 104 | * 28 DDR 2T 0 |
| 105 | * 29 UDIMM NA 0 |
| 106 | * 30 RDIMM NA 0 |
| 107 | * 31 TPD LPDDR2 0 |
| 108 | */ |
| 109 | write32(DDR_PHY + DDRPHY_DCR_OFFSET, 0x0000000B); |
| 110 | /* Generate to use with PHY and PCTL |
| 111 | * MR0 : DDR3 mode register 0 |
| 112 | * 1:0 BL 8 fixed 00 |
| 113 | * 3 BT Sequential 0 Interleaved 1 = 0 |
| 114 | * 6:4,2 CL 6 |
| 115 | * 7 TM Normal 0 |
| 116 | * 8 DLL Reset 1 (self Clearing) |
| 117 | * 11:9 WR 15 ns 6 (010) |
| 118 | * 12 PD Slow 1 Fast 0 0 |
| 119 | * 15:13 RSVD RSVD |
| 120 | * 31:16 Reserved |
| 121 | */ |
Ionela Voinescu | 721f299 | 2015-05-26 12:20:19 +0100 | [diff] [blame] | 122 | write32(DDR_PHY + DDRPHY_MR_OFFSET, 0x00001520); |
Ionela Voinescu | 3fa1ad0 | 2015-04-05 17:55:51 +0100 | [diff] [blame] | 123 | /* MR1 : DDR3 mode register 1 |
| 124 | * Generate to use with PHY and PCTL |
| 125 | * 0 DE DLL Enable 0 Disable 1 |
| 126 | * 5,1 DIC Output Driver RZQ/6 |
| 127 | * 9,6,2 ODT RZQ/4 |
| 128 | * 4:3 AL = 0 |
| 129 | * 7 write leveling enabled 0 |
| 130 | * 10 DQS 0 diff, 1 single = 0 |
| 131 | * 11 TDQS NA 0 |
| 132 | * 12 QOFF Normal mode 0 |
| 133 | * 15:13 RSVD |
| 134 | * 31:16 Reserved |
| 135 | */ |
| 136 | write32(DDR_PHY + DDRPHY_EMR_OFFSET, 0x00000004); |
| 137 | /* MR2 : DDR3 mode register 2 |
| 138 | * Generate to use with PHY and PCTL |
| 139 | * 2:0 PASR, NA 000 |
| 140 | * 3 CWL 000 (5) tck = 22.5ns |
| 141 | * 6 auto self-refresh 1 |
| 142 | * 7 SRT normal 0 |
| 143 | * 8 RSVD |
| 144 | * 10:9 dynamic ODT 10 RZQ/2 |
| 145 | * 31:11 Reserved |
| 146 | */ |
| 147 | write32(DDR_PHY + DDRPHY_EMR2_OFFSET, 0x00000440); |
| 148 | /* MR3: DDR3 mode register 3 |
| 149 | * 1:0 MPRLOC 00 |
| 150 | * 2 MPR 0 |
| 151 | */ |
| 152 | write32(DDR_PHY + DDRPHY_EMR3_OFFSET, 0x00000000); |
| 153 | /* DTAR : Data Training Register |
| 154 | * 11:0 Data Training Column Address |
| 155 | * 27:12 Data Training Row Address |
| 156 | * 30:28 Data Training Bank Address |
| 157 | * 31 Data Training Use MPR (DDR3 Only) |
| 158 | */ |
| 159 | write32(DDR_PHY + DDRPHY_DTAR_OFFSET, 0x00000000); |
| 160 | /* DSGCR |
| 161 | * 0 PUREN Def 1 |
| 162 | * 1 BDISEN Def 1 |
| 163 | * 2 ZUEN Def 1 |
| 164 | * 3 LPIOPD DEf 1 0 |
| 165 | * 4 LPDLLPD DEf 1 0 |
Ionela Voinescu | 6b95406 | 2015-05-21 13:29:45 +0100 | [diff] [blame] | 166 | * 7:5 DQSGX DQS Extention set to 1 - advised by Synopsys |
| 167 | * 10:8 DQSGE DQS Early Gate - 1 - advised by Sysnopsys |
Ionela Voinescu | 3fa1ad0 | 2015-04-05 17:55:51 +0100 | [diff] [blame] | 168 | * 11 NOBUB No Bubbles, adds latency 1 |
| 169 | * 12 FXDLAT Fixed Read Latency 0 |
| 170 | * 15:13 Reserved |
| 171 | * 19:16 CKEPDD CKE Power Down 0000 |
| 172 | * 23:20 ODTPDD ODT Power Down 0000 |
| 173 | * 24 NL2PD Power Down Non LPDDR2 pins 0 |
| 174 | * 25 NL2OE Output Enable Non LPDDR2 pins 1 |
| 175 | * 26 TPDPD LPDDR Only 0 |
| 176 | * 27 TPDOE LPDDR Only 1 |
| 177 | * 28 CKOE Output Enable Clk's 1 |
| 178 | * 29 ODTOE Output Enable ODT 1 |
| 179 | * 30 RSTOE RST# Output Enable 1 |
| 180 | * 31 CKEOE CKE Output Enable 1 |
| 181 | */ |
Ionela Voinescu | 6b95406 | 2015-05-21 13:29:45 +0100 | [diff] [blame] | 182 | write32(DDR_PHY + DDRPHY_DSGCR_OFFSET, 0xFA000927); |
| 183 | /* Sysnopsys advised 500R pullup/pulldown DQS DQSN */ |
| 184 | write32(DDR_PHY + DDRPHY_DXCCR_OFFSET, 0x00000C40); |
Ionela Voinescu | 3fa1ad0 | 2015-04-05 17:55:51 +0100 | [diff] [blame] | 185 | /* DTPR0 : DRAM Timing Params 0 |
| 186 | * 1:0 tMRD 0 |
| 187 | * 4:2 tRTP 2 |
| 188 | * 7:5 tWTR 4 |
| 189 | * 11:8 tRP 6 |
| 190 | * 15:12 tRCD 6 |
| 191 | * 20:16 tRAS 15 |
| 192 | * 24:21 tRRD 4 for x16 |
| 193 | * 30:25 tRC 21 |
| 194 | * 31 tCCD 0 BL/2 Cas to Cas |
| 195 | */ |
| 196 | write32(DDR_PHY + DDRPHY_DTPR0_OFFSET, 0x2A8F6688); |
| 197 | /* DTPR1 : DRAM Timing Params 1 |
| 198 | * 1:0 ODT On/Off Del Std 0 |
| 199 | * 2 tRTW Rd2Wr Del 0 std 1 +1 0 |
| 200 | * 8:3 tFAW 20 Clk |
| 201 | * 10:9 tMOD DDR3 Only 15 |
| 202 | * 11 tRTODT DDR3 Only 0 |
| 203 | * 15:12 Reserved |
| 204 | * 23:16 tRFC 160ns 64 ref 131 |
| 205 | * 26:24 tDQSCK LPDDR2 only 1 |
| 206 | * 29:27 tDQSCKmax 1 |
| 207 | * 31:30 Reserved |
| 208 | */ |
| 209 | write32(DDR_PHY + DDRPHY_DTPR1_OFFSET, 0x094006A0); |
| 210 | /* DTPR2 : DRAM Timing Params 2 |
| 211 | * 9:0 tXS exit SR def 512d |
| 212 | * 14:10 tXP PD Exit Del 8 5 |
| 213 | * 18:15 tCKE CKE Min pulse 5 |
| 214 | * 28:19 tDLLK DLL Lock time 512d |
| 215 | * 32:29 Reserved |
| 216 | */ |
| 217 | write32(DDR_PHY + DDRPHY_DTPR2_OFFSET, 0x10029600); |
| 218 | /* PTR0 : PHY Timing Params 0 |
| 219 | * 5:0 tDLLRST Def 27 |
| 220 | * 17:6 tDLLLOCK Def 2750 |
| 221 | * 21:18 tITMSRST Def 8 |
| 222 | * 31:22 Reserved 0 |
| 223 | */ |
| 224 | write32(DDR_PHY + DDRPHY_PTR0_OFFSET, 0x0022AF9B); |
| 225 | /* PTR1 : PHY Timing Params 1 |
| 226 | * 18:0 : tDINITO DRAM Init time 500us 200,000 Dec 0x30D40 |
| 227 | * 29:19 : tDINIT1 DRAM Init time tRFC + 10ns 68 |
| 228 | */ |
| 229 | write32(DDR_PHY + DDRPHY_PTR1_OFFSET, 0x02230D40); |
| 230 | /* DQS gating configuration: passive windowing mode */ |
| 231 | /* |
| 232 | * PGCR: PHY General cofiguration register |
| 233 | * 0 ITM DDR mode: 0 |
| 234 | * 1 DQS gading configuration: passive windowing 1 |
| 235 | * 2 DQS drift compensation: not supported in passive windowing 0 |
| 236 | * 4:3 DQS drift limit 0 |
| 237 | * 8:5 Digital test output select 0 |
| 238 | * 11:9 CK Enable: one bit for each 3 CK pair: 0x7 |
| 239 | * 13:12 CK Disable values: 0x2 |
| 240 | * 14 CK Invert 0 |
| 241 | * 15 IO loopback 0 |
| 242 | * 17:16 I/O DDR mode 0 |
| 243 | * 21:18 Ranks enable by training: 0xF |
| 244 | * 23:22 Impedance clock divider select 0x2 |
| 245 | * 24 Power down disable 1 |
| 246 | * 28:25 Refresh during training 0 |
| 247 | * 29 loopback DQS shift 0 |
| 248 | * 30 loopback DQS gating 0 |
| 249 | * 31 loopback mode 0 |
| 250 | */ |
| 251 | write32(DDR_PHY + DDRPHY_PGCR_OFFSET, 0x01BC2E02); |
| 252 | |
| 253 | /* PGSR : Wait for INIT/DLL/Z Done from Power on Reset */ |
| 254 | if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x00000007)) |
| 255 | return DDR_TIMEOUT; |
| 256 | /* PIR : PHY controlled init */ |
| 257 | write32(DDR_PHY + DDRPHY_PIR_OFFSET, 0x0000001F); |
| 258 | /* PGSR : Wait for DRAM Init Done */ |
| 259 | if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x00000007)) |
| 260 | return DDR_TIMEOUT; |
| 261 | /* PIR : controller DRAM initialization */ |
| 262 | write32(DDR_PHY + DDRPHY_PIR_OFFSET, 0x00040001); |
| 263 | /* PGSR : Wait for DRAM Init Done */ |
| 264 | if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x0000000F)) |
| 265 | return DDR_TIMEOUT; |
| 266 | /********************************************************************/ |
| 267 | /* DF1STAT0 : wait for DFI_INIT_COMPLETE */ |
| 268 | if (wait_for_completion(DDR_PCTL + DDR_PCTL_DFISTAT0_OFFSET, |
| 269 | 0x00000001)) |
| 270 | return DDR_TIMEOUT; |
| 271 | /* POWCTL : Start the memory Power Up seq*/ |
| 272 | write32(DDR_PCTL + DDR_PCTL_POWCTL_OFFSET, 0x80000001); |
| 273 | /* POWSTAT : wait for POWER_UP_DONE */ |
| 274 | if (wait_for_completion(DDR_PCTL + DDR_PCTL_POWSTAT_OFFSET, |
| 275 | 0x00000001)) |
| 276 | return DDR_TIMEOUT; |
| 277 | /* |
| 278 | * TREFI : t_refi Timing Register 1X |
| 279 | * 12:0 t_refi 7.8us in 100ns 0x4E |
| 280 | * 15:13 Reserved 0 |
| 281 | * 18:16 num_add_ref 0 |
| 282 | * 30:19 Reserved 0 |
| 283 | * 31 Update 1 |
| 284 | */ |
| 285 | write32(DDR_PCTL + DDR_PCTL_TREFI_OFFSET, 0x8000004E); |
| 286 | /* TMRD : t_mrd Timing Register -- Range 2 to 4*/ |
| 287 | write32(DDR_PCTL + DDR_PCTL_TMRD_OFFSET, 0x00000004); |
| 288 | /* |
| 289 | * TRFC : t_rfc Timing Register -- Range 15 to 131 |
| 290 | * 195ns / 2.5ns 78 x4E |
| 291 | */ |
| 292 | write32(DDR_PCTL + DDR_PCTL_TRFC_OFFSET, 0x0000004E); |
| 293 | /* TRP : t_rp Timing Register -- Range 3 to 7 |
| 294 | * 4:0 tRP 12.5 / 2.5 = 5 6 For Now 6-6-6 |
| 295 | * 17:16 rpea_extra DDR3 - value 0 |
| 296 | */ |
| 297 | write32(DDR_PCTL + DDR_PCTL_TRP_OFFSET, 0x00000006); |
| 298 | /* TAL : Additive Latency Register -- AL in MR1 */ |
| 299 | write32(DDR_PCTL + DDR_PCTL_TAL_OFFSET, 0x00000000); |
| 300 | /* TCL : CAS Latency Timing Register -- CASL in MR0 6-6-6 */ |
| 301 | write32(DDR_PCTL + DDR_PCTL_TCL_OFFSET, 0x00000006); |
| 302 | /* TCWL : CAS Write Latency Register --CASL-1 */ |
| 303 | write32(DDR_PCTL + DDR_PCTL_TCWL_OFFSET, 0x00000005); |
| 304 | /* TRAS : Activate to Precharge cmd time 15 45ns / 2.5ns = 18d */ |
| 305 | write32(DDR_PCTL + DDR_PCTL_TRAS_OFFSET, 0x0000000F); |
| 306 | /* TRC : Min. ROW cylce time 21 |
| 307 | * 57.5ns / 2.5ns = 23d Playing safe 24 |
| 308 | */ |
| 309 | write32(DDR_PCTL + DDR_PCTL_TRC_OFFSET, 0x00000015); |
| 310 | /* TRCD : Row to Column Delay # Range 3 to 7 (TCL = TRCD) |
| 311 | * 12.5ns / 2.5ns = 5 but running 6-6-6 6 |
| 312 | */ |
| 313 | write32(DDR_PCTL + DDR_PCTL_TRCD_OFFSET, 0x00000006); |
| 314 | /* TRRD : Row to Row delay -- Range 2 to 6 |
| 315 | * 2K Page 10ns / 2.5ns = 4 |
| 316 | */ |
| 317 | write32(DDR_PCTL + DDR_PCTL_TRRD_OFFSET, 0x00000004); |
| 318 | /* TRTP : Read to Precharge time -- Range 2 to 4 |
| 319 | * Largest 4 or 7.5ns / 2.5ns = 4 |
| 320 | */ |
| 321 | write32(DDR_PCTL + DDR_PCTL_TRTP_OFFSET, 0x00000004); |
| 322 | /* TWR : Write recovery time -- WR in MR0: 15ns / 2.5ns = 6 */ |
| 323 | write32(DDR_PCTL + DDR_PCTL_TWR_OFFSET, 0x00000006); |
| 324 | /* TWTR : Write to read turn around time -- Range 2 to 4 |
| 325 | * Largest 4 or 7.5ns / 2.5ns = 4 |
| 326 | */ |
| 327 | write32(DDR_PCTL + DDR_PCTL_TWTR_OFFSET, 0x00000004); |
| 328 | /* TEXSR : Exit Self Refresh to first valid cmd: tXS 512 */ |
| 329 | write32(DDR_PCTL + DDR_PCTL_TEXSR_OFFSET, 0x00000200); |
| 330 | /* TXP : Exit Power Down to first valid cmd |
| 331 | * tXP 2, Settingto 3 to match PHY |
| 332 | */ |
| 333 | write32(DDR_PCTL + DDR_PCTL_TXP_OFFSET, 0x00000003); |
| 334 | /* TDQS : t_dqs Timing Register |
| 335 | * DQS additional turn around Rank 2 Rank (1 Rank) Def 1 |
| 336 | */ |
| 337 | write32(DDR_PCTL + DDR_PCTL_TDQS_OFFSET, 0x00000001); |
Ionela Voinescu | 6b95406 | 2015-05-21 13:29:45 +0100 | [diff] [blame] | 338 | /* TRTW : Read to Write turn around time Def 3 |
Ionela Voinescu | 3fa1ad0 | 2015-04-05 17:55:51 +0100 | [diff] [blame] | 339 | * Actual gap t_bl + t_rtw |
| 340 | */ |
Ionela Voinescu | 6b95406 | 2015-05-21 13:29:45 +0100 | [diff] [blame] | 341 | write32(DDR_PCTL + DDR_PCTL_TRTW_OFFSET, 0x00000003); |
Ionela Voinescu | 3fa1ad0 | 2015-04-05 17:55:51 +0100 | [diff] [blame] | 342 | /* TCKE : CKE min pulse width DEf 3 */ |
| 343 | write32(DDR_PCTL + DDR_PCTL_TCKE_OFFSET, 0x00000003); |
| 344 | /* TXPDLL : Slow Exit Power Down to first valid cmd delay |
| 345 | * tXARDS 10+AL = 10 |
| 346 | */ |
| 347 | write32(DDR_PCTL + DDR_PCTL_TXPDLL_OFFSET, 0x0000000A); |
| 348 | /* TCKESR : Min CKE Low width for Self refresh entry to exit |
| 349 | * t_ckesr = 0 DDR2 |
| 350 | */ |
| 351 | write32(DDR_PCTL + DDR_PCTL_TCKESR_OFFSET, 0x00000004); |
| 352 | /* TMOD : MRS to any Non-MRS command -- Range 0 to 31 */ |
| 353 | write32(DDR_PCTL + DDR_PCTL_TMOD_OFFSET, 0x0000000F); |
| 354 | /* TZQCS : SDRAM ZQ Calibration Short Period */ |
| 355 | write32(DDR_PCTL + DDR_PCTL_TZQCS_OFFSET, 0x00000040); |
| 356 | /* TZQCL : SDRAM ZQ Calibration Long Period */ |
| 357 | write32(DDR_PCTL + DDR_PCTL_TZQCL_OFFSET, 0x00000200); |
| 358 | /* SCFG : State Configuration Register (Enabling Self Refresh) |
| 359 | * 0 LP_en Leave Off for Bring Up 0 |
| 360 | * 5:1 Reserved |
| 361 | * 6 Synopsys Internal Only 0 |
| 362 | * 7 Enale PHY indication of LP Opportunity 1 |
| 363 | * 11:8 bbflags_timing max UPCTL_TCU_SED_P - tRP (16 - 6) Use 4 |
| 364 | * 16:12 Additional delay on accertion of ac_pdd 4 |
| 365 | * 31:17 Reserved |
| 366 | */ |
| 367 | write32(DDR_PCTL + DDR_PCTL_SCFG_OFFSET, 0x00004480); |
| 368 | /* TREFI_MEM_DDR3 */ |
| 369 | write32(DDR_PCTL + DDR_PCTL_TREFI_MEM_DDR3_OFFSET, 0x00000C30); |
| 370 | |
| 371 | /* DFITPHYWRLAT : Write cmd to dfi_wrdata_en */ |
| 372 | write32(DDR_PCTL + DDR_PCTL_DFIWRLAT_OFFSET, 0x00000002); |
| 373 | /* DFITRDDATAEN : Read cmd to dfi_rddata_en */ |
| 374 | write32(DDR_PCTL + DDR_PCTL_DFITRDDATAEN_OFFSET, 0x00000002); |
| 375 | /* |
| 376 | * DFITPHYWRDATA : dfi_wrdata_en to drive wr data |
| 377 | * DFI Clks wrdata_en to wrdata Def 1 |
| 378 | */ |
| 379 | write32(DDR_PCTL + DDR_PCTL_DFITPHYWRDATA_OFFSET, 0x00000000); |
| 380 | /* |
| 381 | * DFITPHYRDLAT : dfi_rddata_en to dfi_rddata_valid |
| 382 | * DFI clks max rddata_en to rddata_valid Def 15 |
| 383 | */ |
| 384 | write32(DDR_PCTL + DDR_PCTL_DFITPHYRDLAT_OFFSET, 0x00000008); |
| 385 | /* DFISTCFG0 : Drive various DFI signals appropriately |
| 386 | * 0 dfi_init_start 1 |
| 387 | * 1 dfi_freq_ratio_en 1 |
| 388 | * 2 dfi_data_byte_disable_en 1 |
| 389 | */ |
| 390 | write32(DDR_PCTL + DDR_PCTL_DFISTCFG0_OFFSET, 0x00000007); |
| 391 | /* DFISTCFG1 : Enable various DFI support |
| 392 | * 0 dfi_dram_clk_disable_en 1 |
| 393 | * 1 dfi_dram_clk_disable_en_pdp only lPDDR 0 |
| 394 | */ |
| 395 | write32(DDR_PCTL + DDR_PCTL_DFISTCFG1_OFFSET, 0x00000001); |
| 396 | /* DFISTCFG2 : Enable Parity and asoc interrupt |
| 397 | * 0 dfi_parity_in Enable 1 |
| 398 | * 1 Interrupt on dfi_parity_error 1 |
| 399 | */ |
| 400 | write32(DDR_PCTL + DDR_PCTL_DFISTCFG2_OFFSET, 0x00000003); |
| 401 | /* DFILPCFG0 : DFI Low Power Interface Configuration |
| 402 | * 0 Enable DFI LP IF during PD 1 |
| 403 | * 3:1 Reserved |
| 404 | * 7:4 DFI tlp_wakeup time 0 |
| 405 | * 8 Enable DFI LP IF during SR 1 |
| 406 | * 11:9 Reserved |
| 407 | * 15:12 dfi_lp_wakeup in SR 0 |
| 408 | * 19:16 tlp_resp DFI 2.1 recomend 7 |
| 409 | * 23:20 Reserved |
| 410 | * 24 Enable DFI LP in Deep Power Down 0 |
| 411 | * 27:25 Reserved |
| 412 | * 31:28 DFI LP Deep Power Down Value 0 |
| 413 | */ |
| 414 | write32(DDR_PCTL + DDR_PCTL_DFILPCFG0_OFFSET, 0x00070101); |
| 415 | /* DFIODTCFG : DFI ODT Configuration |
| 416 | * Only Enabled on Rank0 Writes |
| 417 | * 0 rank0_odt_read_nsel 0 |
| 418 | * 1 rank0_odt_read_sel 0 |
| 419 | * 2 rank0_odt_write_nsel 0 |
| 420 | * 3 rank0_odt_write_sel 1 |
| 421 | */ |
| 422 | write32(DDR_PCTL + DDR_PCTL_DFIODTCFG_OFFSET, 0x00000008); |
| 423 | /* DFIODTCFG1 : DFI ODT Configuration |
| 424 | * 4:0 odt_lat_w 0 |
| 425 | * 12:8 odt_lat_r 0 Def |
| 426 | * 4:0 odt_len_bl8_w 6 Def |
| 427 | * 12:8 odt_len_bl8_r 6 Def |
| 428 | */ |
| 429 | write32(DDR_PCTL + DDR_PCTL_DFIODTCFG1_OFFSET, 0x060600000); |
| 430 | |
| 431 | /* Memory initilization */ |
| 432 | /* MCMD : PREA, Addr 0 Bank 0 Rank 0 Del 0 |
| 433 | * 3:0 cmd_opcode PREA 00001 |
| 434 | * 16:4 cmd_addr 0 |
| 435 | * 19:17 bank_addr 0 |
| 436 | * 23:20 rank_sel 0 0001 |
| 437 | * 27:24 cmddelay 0 |
| 438 | * 30:24 Reserved |
| 439 | */ |
| 440 | /* MCMD: MR2 */ |
| 441 | write32(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80004403); |
| 442 | /* MRS cmd wait for completion */ |
| 443 | if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00004403)) |
| 444 | return DDR_TIMEOUT; |
| 445 | /* MCMD: MR3 */ |
| 446 | write32(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80000003); |
| 447 | /* MRS cmd wait for completion */ |
| 448 | if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00000003)) |
| 449 | return DDR_TIMEOUT; |
| 450 | /* MCMD: MR1 */ |
| 451 | write32(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80000043); |
| 452 | /* MRS cmd wait for completion */ |
| 453 | if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00000043)) |
| 454 | return DDR_TIMEOUT; |
| 455 | /* MCMD: MR0 */ |
| 456 | write32(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80015203); |
| 457 | /* MRS cmd wait for completion */ |
| 458 | if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00015203)) |
| 459 | return DDR_TIMEOUT; |
| 460 | /* MCMD: ZQS cmd, long 5 short 4 */ |
| 461 | write32(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80104005); |
| 462 | /* MRS cmd wait for completion */ |
| 463 | if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00104005)) |
| 464 | return DDR_TIMEOUT; |
| 465 | /* MCMD: deselect command */ |
| 466 | write32(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80100000); |
| 467 | /* MRS cmd wait for completion */ |
| 468 | if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00100000)) |
| 469 | return DDR_TIMEOUT; |
| 470 | /* MCMD: deselect command */ |
| 471 | write32(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x8010000A); |
| 472 | /* MRS cmd wait for completion */ |
| 473 | if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x0010000A)) |
| 474 | return DDR_TIMEOUT; |
| 475 | |
| 476 | /* DCFG : DRAM Density 256 Mb 16 Bit IO Width |
| 477 | * 1:0 Devicw Width 1 x8, 2 x16, 3 x32 2 |
| 478 | * 5:2 Density 2Gb = 5 |
| 479 | * 6 Dram Type (MDDR/LPDDR2) Only 0 |
| 480 | * 7 Reserved 0 |
| 481 | * 10:8 Address Map R/B/C = 1 |
| 482 | * 31:11 Reserved |
| 483 | */ |
| 484 | write32(DDR_PCTL + DDR_PCTL_DCFG_OFFSET, 0x00000116); |
| 485 | /* PCFG_0 : Port 0 AXI config */ |
| 486 | write32(DDR_PCTL + DDR_PCTL_PCFG0_OFFSET, 0x000800A0); |
| 487 | /* SCTL : UPCTL switch INIT CONFIG State */ |
| 488 | write32(DDR_PCTL + DDR_PCTL_SCTL_OFFSET, 0x00000001); |
| 489 | /* STAT : Wait for Switch INIT to Config State */ |
| 490 | if (wait_for_completion(DDR_PCTL + DDR_PCTL_STAT_OFFSET, 0x00000001)) |
| 491 | return DDR_TIMEOUT; |
| 492 | /* STAT : Wait for Switch INIT to Config State */ |
| 493 | write32(DDR_PCTL + DDR_PCTL_CMDTSTATEN_OFFSET, 0x00000001); |
| 494 | /* STAT : Wait for Switch INIT to Config State */ |
| 495 | if (wait_for_completion(DDR_PCTL + DDR_PCTL_CMDTSTAT_OFFSET, |
| 496 | 0x00000001)) |
| 497 | return DDR_TIMEOUT; |
| 498 | /* Use PHY for DRAM init */ |
| 499 | write32(DDR_PHY + DDRPHY_PIR_OFFSET, 0x00000181); |
| 500 | /* STAT : Wait for Switch INIT to Config State */ |
| 501 | if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x00000001F)) |
| 502 | return DDR_TIMEOUT; |
Ionela Voinescu | 6b95406 | 2015-05-21 13:29:45 +0100 | [diff] [blame] | 503 | /* Disable Impedance Calibration */ |
| 504 | write32(DDR_PHY + DDRPHY_ZQ0CR0_OFFSET, 0x3000014A); |
| 505 | write32(DDR_PHY + DDRPHY_ZQ1CR0_OFFSET, 0x3000014A); |
| 506 | |
Ionela Voinescu | 3fa1ad0 | 2015-04-05 17:55:51 +0100 | [diff] [blame] | 507 | /* SCTL : UPCTL switch Config to ACCESS State */ |
| 508 | write32(DDR_PCTL + DDR_PCTL_SCTL_OFFSET, 0x00000002); |
| 509 | /* STAT : Wait for switch CFG -> GO State */ |
| 510 | if (wait_for_completion(DDR_PCTL + DDR_PCTL_STAT_OFFSET, 0x3)) |
| 511 | return DDR_TIMEOUT; |
| 512 | |
| 513 | return 0; |
| 514 | } |