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review.coreboot.org / coreboot / 69cd729c0cde6f15d1de692f5a2da5d3dfe8ba15 / . / src / mainboard / intel / strago / devicetree.cb
blob: d44a1b64ab6f833099e3fd5bfaaf53855cfc5238 [file] [log] [blame]
Lee Leahy5cb9dda2015-05-01 10:34:54 -0700[diff] [blame]1chip soc/intel/braswell
2
3 ############################################################
4 # Set the parameters for MemoryInit
5 ############################################################
6
Lee Leahy5cb9dda2015-05-01 10:34:54 -0700[diff] [blame]7 register "PcdMrcInitSpdAddr1" = "0xa0"
8 register "PcdMrcInitSpdAddr2" = "0xa2"
9 register "PcdIgdDvmt50PreAlloc" = "1"
Lee Leahy5cb9dda2015-05-01 10:34:54 -0700[diff] [blame]10 register "PcdDvfsEnable" = "0"
Shobhit Srivastavac4153c12015-10-09 17:05:16 +0530[diff] [blame]11 register "PcdCaMirrorEn" = "1"
Lee Leahy5cb9dda2015-05-01 10:34:54 -0700[diff] [blame]12
13 ############################################################
14 # Set the parameters for SiliconInit
15 ############################################################
16
17 register "PcdSdcardMode" = "PCH_ACPI_MODE"
18 register "PcdEnableHsuart0" = "0"
19 register "PcdEnableHsuart1" = "1"
20 register "PcdEnableAzalia" = "1"
21 register "PcdEnableXhci" = "1"
22 register "PcdEnableLpe" = "1"
23 register "PcdEnableDma0" = "1"
24 register "PcdEnableDma1" = "1"
25 register "PcdEnableI2C0" = "1"
26 register "PcdEnableI2C1" = "1"
Divagar Mohandass4f4c6e82015-09-21 11:51:07 +0530[diff] [blame]27 register "PcdEnableI2C2" = "0"
28 register "PcdEnableI2C3" = "0"
Lee Leahy5cb9dda2015-05-01 10:34:54 -0700[diff] [blame]29 register "PcdEnableI2C4" = "1"
30 register "PcdEnableI2C5" = "1"
Divagar Mohandass4f4c6e82015-09-21 11:51:07 +0530[diff] [blame]31 register "PcdEnableI2C6" = "0"
Lee Leahy5cb9dda2015-05-01 10:34:54 -0700[diff] [blame]32 register "PunitPwrConfigDisable" = "0" # Enable SVID
Kane Chen8ff43082015-10-26 15:11:53 +0800[diff] [blame]33 register "ChvSvidConfig" = "SVID_PMIC_CONFIG"
Lee Leahy5cb9dda2015-05-01 10:34:54 -0700[diff] [blame]34 register "PcdEmmcMode" = "PCH_ACPI_MODE"
Lee Leahy5cb9dda2015-05-01 10:34:54 -0700[diff] [blame]35 register "PcdEnableSata" = "0" # Disable SATA
36 register "Usb2Port0PerPortPeTxiSet" = "7"
37 register "Usb2Port0PerPortTxiSet" = "5"
38 register "Usb2Port0IUsbTxEmphasisEn" = "2"
39 register "Usb2Port0PerPortTxPeHalf" = "1"
40 register "Usb2Port1PerPortPeTxiSet" = "7"
41 register "Usb2Port1PerPortTxiSet" = "3"
42 register "Usb2Port1IUsbTxEmphasisEn" = "2"
43 register "Usb2Port1PerPortTxPeHalf" = "1"
44 register "Usb2Port2PerPortPeTxiSet" = "7"
45 register "Usb2Port2PerPortTxiSet" = "3"
46 register "Usb2Port2IUsbTxEmphasisEn" = "2"
47 register "Usb2Port2PerPortTxPeHalf" = "1"
48 register "Usb2Port3PerPortPeTxiSet" = "7"
49 register "Usb2Port3PerPortTxiSet" = "3"
50 register "Usb2Port3IUsbTxEmphasisEn" = "2"
51 register "Usb2Port3PerPortTxPeHalf" = "1"
52 register "Usb2Port4PerPortPeTxiSet" = "7"
53 register "Usb2Port4PerPortTxiSet" = "3"
54 register "Usb2Port4IUsbTxEmphasisEn" = "2"
55 register "Usb2Port4PerPortTxPeHalf" = "1"
56 register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a"
57 register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64"
58 register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64"
59 register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a"
Lee Leahy5cb9dda2015-05-01 10:34:54 -0700[diff] [blame]60 register "PcdPchSsicEnable" = "1"
Lee Leahy5cb9dda2015-05-01 10:34:54 -0700[diff] [blame]61 register "PMIC_I2CBus" = "0"
62 register "ISPEnable" = "0" # Disable IUNIT
63 register "ISPPciDevConfig" = "3"
Hannah Williams79445c72016-01-17 23:11:25 -0800[diff] [blame]64 register "PcdSdDetectChk" = "0" # Disable SD card detect
Lee Leahy5cb9dda2015-05-01 10:34:54 -0700[diff] [blame]65
66 # LPE audio codec settings
fdurairxaff502e2015-08-21 15:36:53 -0700[diff] [blame]67 register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
Lee Leahy5cb9dda2015-05-01 10:34:54 -0700[diff] [blame]68
Angel Pons8d5b6742021-09-27 13:04:28 +0200[diff] [blame]69 register "dptf_enable" = "true"
70
Lee Leahy5cb9dda2015-05-01 10:34:54 -0700[diff] [blame]71 # Enable devices in ACPI mode
72 register "lpss_acpi_mode" = "1"
73 register "emmc_acpi_mode" = "1"
74 register "sd_acpi_mode" = "1"
75 register "lpe_acpi_mode" = "1"
76
77 # Disable SLP_X stretching after SUS power well fail.
78 register "disable_slp_x_stretch_sus_fail" = "1"
79
80 # Allow PCIe devices to wake system from suspend
81 register "pcie_wake_enable" = "1"
82
Arthur Heymans69cd7292022-11-07 13:52:11 +0100[diff] [blame^]83 device cpu_cluster 0 on end
Lee Leahy5cb9dda2015-05-01 10:34:54 -0700[diff] [blame]84 device domain 0 on
85 # EDS Table 24-4, Figure 24-5
86 device pci 00.0 on end # 8086 2280 - SoC transaction router
87 device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display
Divagar Mohandass4f4c6e82015-09-21 11:51:07 +0530[diff] [blame]88 device pci 03.0 off end # 8086 22b8 - Camera and Image Processor
Lee Leahy5cb9dda2015-05-01 10:34:54 -0700[diff] [blame]89 device pci 0b.0 on end # 8086 22dc - ?
90 device pci 10.0 on end # 8086 2294 - MMC Port
91 device pci 11.0 off end # 8086 0F15 - SDIO Port
92 device pci 12.0 on end # 8086 0F16 - SD Port
93 device pci 13.0 off end # 8086 22a3 - Sata controller
94 device pci 14.0 on end # 8086 22b5 - USB XHCI - Only 1 USB controller at a time
95 device pci 15.0 on end # 8086 22a8 - LP Engine Audio
96 device pci 16.0 off end # 8086 22b7 - USB device
97 device pci 18.0 on end # 8086 22c0 - SIO - DMA
98 device pci 18.1 on end # 8086 22c1 - I2C Port 1
99 device pci 18.2 on end # 8086 22c2 - I2C Port 2
Divagar Mohandass4f4c6e82015-09-21 11:51:07 +0530[diff] [blame]100 device pci 18.3 off end # 8086 22c3 - I2C Port 3
101 device pci 18.4 off end # 8086 22c4 - I2C Port 4
Lee Leahy5cb9dda2015-05-01 10:34:54 -0700[diff] [blame]102 device pci 18.5 on end # 8086 22c5 - I2C Port 5
103 device pci 18.6 on end # 8086 22c6 - I2C Port 6
Divagar Mohandass4f4c6e82015-09-21 11:51:07 +0530[diff] [blame]104 device pci 18.7 off end # 8086 22c7 - I2C Port 7
105 device pci 1a.0 off end # 8086 0F18 - Trusted Execution Engine
Lee Leahy5cb9dda2015-05-01 10:34:54 -0700[diff] [blame]106 device pci 1b.0 on end # 8086 0F04 - HD Audio
107 device pci 1c.0 on end # 8086 0000 - PCIe Root Port 1
108 device pci 1c.1 on end # 8086 0000 - PCIe Root Port 2
109 device pci 1c.2 on end # 8086 0000 - PCIe Root Port 3
Divagar Mohandass4f4c6e82015-09-21 11:51:07 +0530[diff] [blame]110 device pci 1c.3 off end # 8086 0000 - PCIe Root Port 4
Lee Leahy5cb9dda2015-05-01 10:34:54 -0700[diff] [blame]111 device pci 1e.0 on end # 8086 2286 - SIO - DMA
112 device pci 1e.1 off end # 8086 0F08 - PWM 1
113 device pci 1e.2 off end # 8086 0F09 - PWM 2
114 device pci 1e.3 on end # 8086 228a - HSUART 1
Divagar Mohandass4f4c6e82015-09-21 11:51:07 +0530[diff] [blame]115 device pci 1e.4 off end # 8086 228c - HSUART 2
Lee Leahy5cb9dda2015-05-01 10:34:54 -0700[diff] [blame]116 device pci 1e.5 on end # 8086 228e - SPI 1
Divagar Mohandass4f4c6e82015-09-21 11:51:07 +0530[diff] [blame]117 device pci 1e.6 off end # 8086 2290 - SPI 2
118 device pci 1e.7 off end # 8086 22ac - SPI 3
Lee Leahy5cb9dda2015-05-01 10:34:54 -0700[diff] [blame]119 device pci 1f.0 on # 8086 229c - LPC bridge
120 chip drivers/pc80/tpm
121 # Rising edge interrupt
122 register "irq_polarity" = "2"
123 device pnp 0c31.0 on
124 irq 0x70 = 10
125 end
126 end
127 chip ec/google/chromeec
128 device pnp 0c09.0 on end
129 end
130 end # LPC Bridge
131 device pci 1f.3 off end # 8086 0F12 - SMBus 0
132 end
133end