| Lee Leahy | 5cb9dda | 2015-05-01 10:34:54 -0700 | [diff] [blame^] | 1 | chip soc/intel/braswell |
| 2 | |
| 3 | ############################################################ |
| 4 | # Set the parameters for MemoryInit |
| 5 | ############################################################ |
| 6 | |
| 7 | register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB |
| 8 | |
| 9 | register "PcdMrcInitMmioSize" = "0x0800" |
| 10 | register "PcdMrcInitSpdAddr1" = "0xa0" |
| 11 | register "PcdMrcInitSpdAddr2" = "0xa2" |
| 12 | register "PcdIgdDvmt50PreAlloc" = "1" |
| 13 | register "PcdApertureSize" = "2" |
| 14 | register "PcdGttSize" = "1" |
| 15 | register "PcdDvfsEnable" = "0" |
| 16 | |
| 17 | ############################################################ |
| 18 | # Set the parameters for SiliconInit |
| 19 | ############################################################ |
| 20 | |
| 21 | register "PcdSdcardMode" = "PCH_ACPI_MODE" |
| 22 | register "PcdEnableHsuart0" = "0" |
| 23 | register "PcdEnableHsuart1" = "1" |
| 24 | register "PcdEnableAzalia" = "1" |
| 25 | register "PcdEnableXhci" = "1" |
| 26 | register "PcdEnableLpe" = "1" |
| 27 | register "PcdEnableDma0" = "1" |
| 28 | register "PcdEnableDma1" = "1" |
| 29 | register "PcdEnableI2C0" = "1" |
| 30 | register "PcdEnableI2C1" = "1" |
| 31 | register "PcdEnableI2C2" = "1" |
| 32 | register "PcdEnableI2C3" = "1" |
| 33 | register "PcdEnableI2C4" = "1" |
| 34 | register "PcdEnableI2C5" = "1" |
| 35 | register "PcdEnableI2C6" = "1" |
| 36 | register "PunitPwrConfigDisable" = "0" # Enable SVID |
| 37 | register "ChvSvidConfig" = "SVID_CONFIG1" |
| 38 | register "PcdEmmcMode" = "PCH_ACPI_MODE" |
| 39 | register "PcdUsb3ClkSsc" = "1" |
| 40 | register "PcdDispClkSsc" = "1" |
| 41 | register "PcdSataClkSsc" = "1" |
| 42 | register "PcdEnableSata" = "0" # Disable SATA |
| 43 | register "Usb2Port0PerPortPeTxiSet" = "7" |
| 44 | register "Usb2Port0PerPortTxiSet" = "5" |
| 45 | register "Usb2Port0IUsbTxEmphasisEn" = "2" |
| 46 | register "Usb2Port0PerPortTxPeHalf" = "1" |
| 47 | register "Usb2Port1PerPortPeTxiSet" = "7" |
| 48 | register "Usb2Port1PerPortTxiSet" = "3" |
| 49 | register "Usb2Port1IUsbTxEmphasisEn" = "2" |
| 50 | register "Usb2Port1PerPortTxPeHalf" = "1" |
| 51 | register "Usb2Port2PerPortPeTxiSet" = "7" |
| 52 | register "Usb2Port2PerPortTxiSet" = "3" |
| 53 | register "Usb2Port2IUsbTxEmphasisEn" = "2" |
| 54 | register "Usb2Port2PerPortTxPeHalf" = "1" |
| 55 | register "Usb2Port3PerPortPeTxiSet" = "7" |
| 56 | register "Usb2Port3PerPortTxiSet" = "3" |
| 57 | register "Usb2Port3IUsbTxEmphasisEn" = "2" |
| 58 | register "Usb2Port3PerPortTxPeHalf" = "1" |
| 59 | register "Usb2Port4PerPortPeTxiSet" = "7" |
| 60 | register "Usb2Port4PerPortTxiSet" = "3" |
| 61 | register "Usb2Port4IUsbTxEmphasisEn" = "2" |
| 62 | register "Usb2Port4PerPortTxPeHalf" = "1" |
| 63 | register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a" |
| 64 | register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" |
| 65 | register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" |
| 66 | register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" |
| 67 | register "PcdSataInterfaceSpeed" = "3" |
| 68 | register "PcdPchSsicEnable" = "1" |
| 69 | register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM |
| 70 | register "PMIC_I2CBus" = "0" |
| 71 | register "ISPEnable" = "0" # Disable IUNIT |
| 72 | register "ISPPciDevConfig" = "3" |
| 73 | |
| 74 | # LPE audio codec settings |
| 75 | register "lpe_codec_clk_freq" = "25" # 25MHz clock |
| 76 | register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] |
| 77 | |
| 78 | # Enable devices in ACPI mode |
| 79 | register "lpss_acpi_mode" = "1" |
| 80 | register "emmc_acpi_mode" = "1" |
| 81 | register "sd_acpi_mode" = "1" |
| 82 | register "lpe_acpi_mode" = "1" |
| 83 | |
| 84 | # Disable SLP_X stretching after SUS power well fail. |
| 85 | register "disable_slp_x_stretch_sus_fail" = "1" |
| 86 | |
| 87 | # Allow PCIe devices to wake system from suspend |
| 88 | register "pcie_wake_enable" = "1" |
| 89 | |
| 90 | device cpu_cluster 0 on |
| 91 | device lapic 0 on end |
| 92 | end |
| 93 | device domain 0 on |
| 94 | # EDS Table 24-4, Figure 24-5 |
| 95 | device pci 00.0 on end # 8086 2280 - SoC transaction router |
| 96 | device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display |
| 97 | device pci 03.0 on end # 8086 22b8 - Camera and Image Processor |
| 98 | device pci 0b.0 on end # 8086 22dc - ? |
| 99 | device pci 10.0 on end # 8086 2294 - MMC Port |
| 100 | device pci 11.0 off end # 8086 0F15 - SDIO Port |
| 101 | device pci 12.0 on end # 8086 0F16 - SD Port |
| 102 | device pci 13.0 off end # 8086 22a3 - Sata controller |
| 103 | device pci 14.0 on end # 8086 22b5 - USB XHCI - Only 1 USB controller at a time |
| 104 | device pci 15.0 on end # 8086 22a8 - LP Engine Audio |
| 105 | device pci 16.0 off end # 8086 22b7 - USB device |
| 106 | device pci 18.0 on end # 8086 22c0 - SIO - DMA |
| 107 | device pci 18.1 on end # 8086 22c1 - I2C Port 1 |
| 108 | device pci 18.2 on end # 8086 22c2 - I2C Port 2 |
| 109 | device pci 18.3 on end # 8086 22c3 - I2C Port 3 |
| 110 | device pci 18.4 on end # 8086 22c4 - I2C Port 4 |
| 111 | device pci 18.5 on end # 8086 22c5 - I2C Port 5 |
| 112 | device pci 18.6 on end # 8086 22c6 - I2C Port 6 |
| 113 | device pci 18.7 on end # 8086 22c7 - I2C Port 7 |
| 114 | device pci 1a.0 on end # 8086 0F18 - Trusted Execution Engine |
| 115 | device pci 1b.0 on end # 8086 0F04 - HD Audio |
| 116 | device pci 1c.0 on end # 8086 0000 - PCIe Root Port 1 |
| 117 | device pci 1c.1 on end # 8086 0000 - PCIe Root Port 2 |
| 118 | device pci 1c.2 on end # 8086 0000 - PCIe Root Port 3 |
| 119 | device pci 1c.3 on end # 8086 0000 - PCIe Root Port 4 |
| 120 | device pci 1e.0 on end # 8086 2286 - SIO - DMA |
| 121 | device pci 1e.1 off end # 8086 0F08 - PWM 1 |
| 122 | device pci 1e.2 off end # 8086 0F09 - PWM 2 |
| 123 | device pci 1e.3 on end # 8086 228a - HSUART 1 |
| 124 | device pci 1e.4 on end # 8086 228c - HSUART 2 |
| 125 | device pci 1e.5 on end # 8086 228e - SPI 1 |
| 126 | device pci 1e.6 on end # 8086 2290 - SPI 2 |
| 127 | device pci 1e.7 on end # 8086 22ac - SPI 3 |
| 128 | device pci 1f.0 on # 8086 229c - LPC bridge |
| 129 | chip drivers/pc80/tpm |
| 130 | # Rising edge interrupt |
| 131 | register "irq_polarity" = "2" |
| 132 | device pnp 0c31.0 on |
| 133 | irq 0x70 = 10 |
| 134 | end |
| 135 | end |
| 136 | chip ec/google/chromeec |
| 137 | device pnp 0c09.0 on end |
| 138 | end |
| 139 | end # LPC Bridge |
| 140 | device pci 1f.3 off end # 8086 0F12 - SMBus 0 |
| 141 | end |
| 142 | end |