blob: f092380d15c827cec1010284ec552c202c142dc8 [file] [log] [blame]
Sven Schnelled8129f92011-04-20 09:12:17 +00001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2007-2009 coresystems GmbH
5## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
6##
7## This program is free software; you can redistribute it and/or
8## modify it under the terms of the GNU General Public License as
9## published by the Free Software Foundation; version 2 of
10## the License.
11##
12## This program is distributed in the hope that it will be useful,
13## but WITHOUT ANY WARRANTY; without even the implied warranty of
14## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15## GNU General Public License for more details.
16##
17## You should have received a copy of the GNU General Public License
18## along with this program; if not, write to the Free Software
19## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
20## MA 02110-1301 USA
21##
22
23chip northbridge/intel/i945
24
Stefan Reinauer0aa37c42013-02-12 15:20:54 -080025 device cpu_cluster 0 on
Sven Schnelled8129f92011-04-20 09:12:17 +000026 chip cpu/intel/socket_mFCPGA478
27 device lapic 0 on end
28 end
29 end
30
Stefan Reinauer4aff4452013-02-12 14:17:15 -080031 device domain 0 on
Sven Schnelled8129f92011-04-20 09:12:17 +000032 device pci 00.0 on # Host bridge
33 subsystemid 0x17aa 0x2015
34 end
35 device pci 01.0 on # PCI-e
36 device pci 00.0 on # VGA
37 subsystemid 0x17aa 0x20a4
38 end
39 end
40
41 device pci 02.0 on # GMA Graphics controller
42 subsystemid 0x17aa 0x201a
43 end
44 device pci 02.1 on # display controller
45 subsystemid 0x17aa 0x201a
46 end
47
48 chip southbridge/intel/i82801gx
49 register "pirqa_routing" = "0x0b"
50 register "pirqb_routing" = "0x0b"
51 register "pirqc_routing" = "0x0b"
52 register "pirqd_routing" = "0x0b"
53 register "pirqe_routing" = "0x0b"
54 register "pirqf_routing" = "0x0b"
55 register "pirqg_routing" = "0x0b"
56 register "pirqh_routing" = "0x0b"
57
58 # GPI routing
59 # 0 No effect (default)
60 # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
61 # 2 SCI (if corresponding GPIO_EN bit is also set)
62 register "gpi13_routing" = "2"
63 register "gpi12_routing" = "2"
64 register "gpi8_routing" = "2"
65
Sven Schnellee572ef62011-10-27 13:10:14 +020066 register "sata_ahci" = "0x1"
67 register "sata_ports_implemented" = "0x01"
Sven Schnelled8129f92011-04-20 09:12:17 +000068
69 register "gpe0_en" = "0x11000006"
Sven Schnelle61cd5bf2011-06-23 19:12:25 +020070 register "alt_gp_smi_en" = "0x1000"
Sven Schnelled8129f92011-04-20 09:12:17 +000071
Sven Schnelled2bc1172011-10-23 16:36:22 +020072 register "c4onc3_enable" = "1"
73
Paul Menzel68eff4f2014-03-03 09:18:18 +010074 device pci 1b.0 on # Audio Controller
Sven Schnelled8129f92011-04-20 09:12:17 +000075 subsystemid 0x17aa 0x2010
76 end
77 device pci 1c.0 on # Ethernet
78 subsystemid 0x17aa 0x2001
79 end
80 device pci 1c.1 on end # WLAN
81 device pci 1d.0 on # USB UHCI
82 subsystemid 0x17aa 0x200a
83 end
84 device pci 1d.1 on # USB UHCI
85 subsystemid 0x17aa 0x200a
86 end
87 device pci 1d.2 on # USB UHCI
88 subsystemid 0x17aa 0x200a
89 end
90 device pci 1d.3 on # USB UHCI
91 subsystemid 0x17aa 0x200a
92 end
93 device pci 1d.7 on # USB2 EHCI
94 subsystemid 0x17aa 0x200b
95 end
96 device pci 1e.0 on # PCI Bridge
97 chip southbridge/ti/pci1x2x
98 device pci 00.0 on
99 subsystemid 0x17aa 0x2012
100 end
101 register "scr" = "0x0844d070"
102 register "mrr" = "0x01d01002"
103
104 end
105 end
106 device pci 1f.0 on # PCI-LPC bridge
107 subsystemid 0x17aa 0x2009
108 chip ec/lenovo/pmh7
109 device pnp ff.1 on # dummy
110 end
111
112 register "backlight_enable" = "0x01"
113 register "dock_event_enable" = "0x01"
114 end
115 chip ec/lenovo/h8
116 device pnp ff.2 on # dummy
117 io 0x60 = 0x62
118 io 0x62 = 0x66
119 io 0x64 = 0x1600
120 io 0x66 = 0x1604
121 end
122
123
124 register "config0" = "0xa6"
125 register "config1" = "0x05"
126 register "config2" = "0xa0"
Sven Schnelle14c93ec2011-07-11 14:58:48 +0200127 register "config3" = "0x01"
Sven Schnelled8129f92011-04-20 09:12:17 +0000128
129 register "beepmask0" = "0xfe"
130 register "beepmask1" = "0x96"
Vladimir Serbinenko9a3b9c42014-01-11 20:56:47 +0100131 register "has_power_management_beeps" = "1"
Sven Schnelled8129f92011-04-20 09:12:17 +0000132
133 register "event2_enable" = "0xff"
134 register "event3_enable" = "0xff"
135 register "event4_enable" = "0xf4"
Sven Schnelle8c17a632011-06-23 11:59:48 +0200136 register "event5_enable" = "0x3f"
Sven Schnelled8129f92011-04-20 09:12:17 +0000137 register "event6_enable" = "0x80"
Sven Schnelle8c17a632011-06-23 11:59:48 +0200138 register "event7_enable" = "0x01"
139 register "event8_enable" = "0x01"
140 register "event9_enable" = "0xff"
Sven Schnellef8aa1852011-06-23 13:41:55 +0200141 register "eventa_enable" = "0xff"
142 register "eventb_enable" = "0xff"
Sven Schnelle8c17a632011-06-23 11:59:48 +0200143 register "eventc_enable" = "0xff"
144 register "eventd_enable" = "0xff"
Sven Schnelle95ebe662011-04-28 09:29:06 +0000145 register "eventc_enable" = "0x3c"
Sven Schnelled8129f92011-04-20 09:12:17 +0000146
Sven Schnelled8129f92011-04-20 09:12:17 +0000147 end
148 chip superio/nsc/pc87382
149 device pnp 164e.2 on # IR
150 io 0x60 = 0x2f8
151 end
152
153 device pnp 164e.3 off # Serial Port
154 io 0x60 = 0x3f8
155 end
156
157 device pnp 164e.7 on # GPIO
158 io 0x60 = 0x1680
159 end
160
161 device pnp 164e.19 on # DLPC
162 io 0x60 = 0x164c
163 end
164 end
165
166 chip superio/nsc/pc87384
167 device pnp 2e.0 off #FDC
168 end
169
170 device pnp 2e.1 on # Parallel Port
171 io 0x60 = 0x3bc
172 irq 0x70 = 7
173 end
174
175 device pnp 2e.2 off # Serial Port / IR
176 io 0x60 = 0x2f8
177 irq 0x70 = 4
178 end
179
180 device pnp 2e.3 on # Serial Port
181 io 0x60 = 0x3f8
182 irq 0x70 = 4
183 end
184
185 device pnp 2e.7 on # GPIO
186 io 0x60 = 0x1620
187 end
188
189 device pnp 2e.a off # WDT
190 end
191 end
192 end
Sven Schnelleedabf542011-04-27 19:47:49 +0000193 device pci 1f.1 on # IDE
Sven Schnelled8129f92011-04-20 09:12:17 +0000194 subsystemid 0x17aa 0x200c
195 end
196 device pci 1f.2 on # SATA
197 subsystemid 0x17aa 0x200d
198 end
199 device pci 1f.3 on # SMBUS
200 subsystemid 0x17aa 0x200f
Sven Schnellefe40c502011-10-23 15:54:31 +0200201 chip drivers/ics/954309
202 register "reg0" = "0x2e"
203 register "reg1" = "0xf7"
204 register "reg2" = "0x3c"
205 register "reg3" = "0x20"
206 register "reg4" = "0x01"
207 register "reg5" = "0x00"
208 register "reg6" = "0x1b"
209 register "reg7" = "0x01"
210 register "reg8" = "0x54"
211 register "reg9" = "0xff"
212 register "reg10" = "0xff"
213 register "reg11" = "0x07"
214 device i2c 69 on end
215 end
Vladimir Serbinenko62adc4c2014-01-23 09:06:08 +0100216 # eeprom, 8 virtual devices, same chip
217 chip drivers/i2c/at24rf08c
218 device i2c 54 on end
219 device i2c 55 on end
220 device i2c 56 on end
221 device i2c 57 on end
222 device i2c 5c on end
223 device i2c 5d on end
224 device i2c 5e on end
225 device i2c 5f on end
226 end
Sven Schnelled8129f92011-04-20 09:12:17 +0000227 end
228 end
229 end
230end