Sven Schnelle | d8129f9 | 2011-04-20 09:12:17 +0000 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2007-2009 coresystems GmbH |
| 5 | ## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org> |
| 6 | ## |
| 7 | ## This program is free software; you can redistribute it and/or |
| 8 | ## modify it under the terms of the GNU General Public License as |
| 9 | ## published by the Free Software Foundation; version 2 of |
| 10 | ## the License. |
| 11 | ## |
| 12 | ## This program is distributed in the hope that it will be useful, |
| 13 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | ## GNU General Public License for more details. |
| 16 | ## |
| 17 | ## You should have received a copy of the GNU General Public License |
| 18 | ## along with this program; if not, write to the Free Software |
| 19 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
| 20 | ## MA 02110-1301 USA |
| 21 | ## |
| 22 | |
| 23 | chip northbridge/intel/i945 |
| 24 | |
| 25 | device lapic_cluster 0 on |
| 26 | chip cpu/intel/socket_mFCPGA478 |
| 27 | device lapic 0 on end |
| 28 | end |
| 29 | end |
| 30 | |
| 31 | device pci_domain 0 on |
| 32 | device pci 00.0 on # Host bridge |
| 33 | subsystemid 0x17aa 0x2015 |
| 34 | end |
| 35 | device pci 01.0 on # PCI-e |
| 36 | device pci 00.0 on # VGA |
| 37 | subsystemid 0x17aa 0x20a4 |
| 38 | end |
| 39 | end |
| 40 | |
| 41 | device pci 02.0 on # GMA Graphics controller |
| 42 | subsystemid 0x17aa 0x201a |
| 43 | end |
| 44 | device pci 02.1 on # display controller |
| 45 | subsystemid 0x17aa 0x201a |
| 46 | end |
| 47 | |
| 48 | chip southbridge/intel/i82801gx |
| 49 | register "pirqa_routing" = "0x0b" |
| 50 | register "pirqb_routing" = "0x0b" |
| 51 | register "pirqc_routing" = "0x0b" |
| 52 | register "pirqd_routing" = "0x0b" |
| 53 | register "pirqe_routing" = "0x0b" |
| 54 | register "pirqf_routing" = "0x0b" |
| 55 | register "pirqg_routing" = "0x0b" |
| 56 | register "pirqh_routing" = "0x0b" |
| 57 | |
| 58 | # GPI routing |
| 59 | # 0 No effect (default) |
| 60 | # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) |
| 61 | # 2 SCI (if corresponding GPIO_EN bit is also set) |
| 62 | register "gpi13_routing" = "2" |
| 63 | register "gpi12_routing" = "2" |
| 64 | register "gpi8_routing" = "2" |
| 65 | |
| 66 | register "sata_ahci" = "0x0" |
| 67 | |
| 68 | register "gpe0_en" = "0x11000006" |
Sven Schnelle | 61cd5bf | 2011-06-23 19:12:25 +0200 | [diff] [blame] | 69 | register "alt_gp_smi_en" = "0x1000" |
Sven Schnelle | d8129f9 | 2011-04-20 09:12:17 +0000 | [diff] [blame] | 70 | |
| 71 | device pci 1b.0 on # Audio Cnotroller |
| 72 | subsystemid 0x17aa 0x2010 |
| 73 | end |
| 74 | device pci 1c.0 on # Ethernet |
| 75 | subsystemid 0x17aa 0x2001 |
| 76 | end |
| 77 | device pci 1c.1 on end # WLAN |
| 78 | device pci 1d.0 on # USB UHCI |
| 79 | subsystemid 0x17aa 0x200a |
| 80 | end |
| 81 | device pci 1d.1 on # USB UHCI |
| 82 | subsystemid 0x17aa 0x200a |
| 83 | end |
| 84 | device pci 1d.2 on # USB UHCI |
| 85 | subsystemid 0x17aa 0x200a |
| 86 | end |
| 87 | device pci 1d.3 on # USB UHCI |
| 88 | subsystemid 0x17aa 0x200a |
| 89 | end |
| 90 | device pci 1d.7 on # USB2 EHCI |
| 91 | subsystemid 0x17aa 0x200b |
| 92 | end |
| 93 | device pci 1e.0 on # PCI Bridge |
| 94 | chip southbridge/ti/pci1x2x |
| 95 | device pci 00.0 on |
| 96 | subsystemid 0x17aa 0x2012 |
| 97 | end |
| 98 | register "scr" = "0x0844d070" |
| 99 | register "mrr" = "0x01d01002" |
| 100 | |
| 101 | end |
| 102 | end |
| 103 | device pci 1f.0 on # PCI-LPC bridge |
| 104 | subsystemid 0x17aa 0x2009 |
| 105 | chip ec/lenovo/pmh7 |
| 106 | device pnp ff.1 on # dummy |
| 107 | end |
| 108 | |
| 109 | register "backlight_enable" = "0x01" |
| 110 | register "dock_event_enable" = "0x01" |
| 111 | end |
| 112 | chip ec/lenovo/h8 |
| 113 | device pnp ff.2 on # dummy |
| 114 | io 0x60 = 0x62 |
| 115 | io 0x62 = 0x66 |
| 116 | io 0x64 = 0x1600 |
| 117 | io 0x66 = 0x1604 |
| 118 | end |
| 119 | |
| 120 | |
| 121 | register "config0" = "0xa6" |
| 122 | register "config1" = "0x05" |
| 123 | register "config2" = "0xa0" |
Sven Schnelle | 14c93ec | 2011-07-11 14:58:48 +0200 | [diff] [blame] | 124 | register "config3" = "0x01" |
Sven Schnelle | d8129f9 | 2011-04-20 09:12:17 +0000 | [diff] [blame] | 125 | |
| 126 | register "beepmask0" = "0xfe" |
| 127 | register "beepmask1" = "0x96" |
| 128 | |
| 129 | register "event2_enable" = "0xff" |
| 130 | register "event3_enable" = "0xff" |
| 131 | register "event4_enable" = "0xf4" |
Sven Schnelle | 8c17a63 | 2011-06-23 11:59:48 +0200 | [diff] [blame] | 132 | register "event5_enable" = "0x3f" |
Sven Schnelle | d8129f9 | 2011-04-20 09:12:17 +0000 | [diff] [blame] | 133 | register "event6_enable" = "0x80" |
Sven Schnelle | 8c17a63 | 2011-06-23 11:59:48 +0200 | [diff] [blame] | 134 | register "event7_enable" = "0x01" |
| 135 | register "event8_enable" = "0x01" |
| 136 | register "event9_enable" = "0xff" |
Sven Schnelle | f8aa185 | 2011-06-23 13:41:55 +0200 | [diff] [blame] | 137 | register "eventa_enable" = "0xff" |
| 138 | register "eventb_enable" = "0xff" |
Sven Schnelle | 8c17a63 | 2011-06-23 11:59:48 +0200 | [diff] [blame] | 139 | register "eventc_enable" = "0xff" |
| 140 | register "eventd_enable" = "0xff" |
Sven Schnelle | 95ebe66 | 2011-04-28 09:29:06 +0000 | [diff] [blame] | 141 | register "eventc_enable" = "0x3c" |
Sven Schnelle | d8129f9 | 2011-04-20 09:12:17 +0000 | [diff] [blame] | 142 | |
| 143 | register "wlan_enable" = "0x01" |
| 144 | register "trackpoint_enable" = "0x03" |
| 145 | |
| 146 | end |
| 147 | chip superio/nsc/pc87382 |
| 148 | device pnp 164e.2 on # IR |
| 149 | io 0x60 = 0x2f8 |
| 150 | end |
| 151 | |
| 152 | device pnp 164e.3 off # Serial Port |
| 153 | io 0x60 = 0x3f8 |
| 154 | end |
| 155 | |
| 156 | device pnp 164e.7 on # GPIO |
| 157 | io 0x60 = 0x1680 |
| 158 | end |
| 159 | |
| 160 | device pnp 164e.19 on # DLPC |
| 161 | io 0x60 = 0x164c |
| 162 | end |
| 163 | end |
| 164 | |
| 165 | chip superio/nsc/pc87384 |
| 166 | device pnp 2e.0 off #FDC |
| 167 | end |
| 168 | |
| 169 | device pnp 2e.1 on # Parallel Port |
| 170 | io 0x60 = 0x3bc |
| 171 | irq 0x70 = 7 |
| 172 | end |
| 173 | |
| 174 | device pnp 2e.2 off # Serial Port / IR |
| 175 | io 0x60 = 0x2f8 |
| 176 | irq 0x70 = 4 |
| 177 | end |
| 178 | |
| 179 | device pnp 2e.3 on # Serial Port |
| 180 | io 0x60 = 0x3f8 |
| 181 | irq 0x70 = 4 |
| 182 | end |
| 183 | |
| 184 | device pnp 2e.7 on # GPIO |
| 185 | io 0x60 = 0x1620 |
| 186 | end |
| 187 | |
| 188 | device pnp 2e.a off # WDT |
| 189 | end |
| 190 | end |
| 191 | end |
Sven Schnelle | edabf54 | 2011-04-27 19:47:49 +0000 | [diff] [blame] | 192 | device pci 1f.1 on # IDE |
Sven Schnelle | d8129f9 | 2011-04-20 09:12:17 +0000 | [diff] [blame] | 193 | subsystemid 0x17aa 0x200c |
| 194 | end |
| 195 | device pci 1f.2 on # SATA |
| 196 | subsystemid 0x17aa 0x200d |
| 197 | end |
| 198 | device pci 1f.3 on # SMBUS |
| 199 | subsystemid 0x17aa 0x200f |
Sven Schnelle | fe40c50 | 2011-10-23 15:54:31 +0200 | [diff] [blame^] | 200 | chip drivers/ics/954309 |
| 201 | register "reg0" = "0x2e" |
| 202 | register "reg1" = "0xf7" |
| 203 | register "reg2" = "0x3c" |
| 204 | register "reg3" = "0x20" |
| 205 | register "reg4" = "0x01" |
| 206 | register "reg5" = "0x00" |
| 207 | register "reg6" = "0x1b" |
| 208 | register "reg7" = "0x01" |
| 209 | register "reg8" = "0x54" |
| 210 | register "reg9" = "0xff" |
| 211 | register "reg10" = "0xff" |
| 212 | register "reg11" = "0x07" |
| 213 | device i2c 69 on end |
| 214 | end |
Sven Schnelle | d8129f9 | 2011-04-20 09:12:17 +0000 | [diff] [blame] | 215 | end |
| 216 | end |
| 217 | end |
| 218 | end |