Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; version 2 of the License. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | */ |
| 14 | |
Arthur Heymans | 17ad459 | 2018-08-06 15:35:28 +0200 | [diff] [blame] | 15 | #include <cbmem.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 16 | #include <console/console.h> |
Elyes HAOUAS | 748caed | 2019-12-19 17:02:08 +0100 | [diff] [blame] | 17 | #include <device/pci_def.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 18 | #include <device/pci_ops.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 19 | #include <stdint.h> |
| 20 | #include <device/device.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 21 | #include <boot/tables.h> |
| 22 | #include <arch/acpi.h> |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 23 | #include <northbridge/intel/x4x/iomap.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 24 | #include <northbridge/intel/x4x/chip.h> |
| 25 | #include <northbridge/intel/x4x/x4x.h> |
Kyösti Mälkki | f091f4d | 2019-08-14 03:49:21 +0300 | [diff] [blame] | 26 | #include <cpu/intel/smm_reloc.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 27 | |
Arthur Heymans | 4c4f56a | 2017-02-27 13:46:11 +0100 | [diff] [blame] | 28 | static const int legacy_hole_base_k = 0xa0000 / 1024; |
| 29 | |
Elyes HAOUAS | fea02e1 | 2018-02-08 14:59:03 +0100 | [diff] [blame] | 30 | static void mch_domain_read_resources(struct device *dev) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 31 | { |
Arthur Heymans | 4c65bfc | 2018-04-10 13:34:24 +0200 | [diff] [blame] | 32 | u8 index; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 33 | u64 tom, touud; |
Arthur Heymans | 4c65bfc | 2018-04-10 13:34:24 +0200 | [diff] [blame] | 34 | u32 tomk, tolud, delta_cbmem; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 35 | u32 pcie_config_base, pcie_config_size; |
| 36 | u32 uma_sizek = 0; |
| 37 | |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 38 | const u32 top32memk = 4 * (GiB / KiB); |
| 39 | index = 3; |
| 40 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 41 | pci_domain_read_resources(dev); |
| 42 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 43 | struct device *mch = pcidev_on_root(0, 0); |
Arthur Heymans | c6e13b6 | 2018-06-26 21:06:38 +0200 | [diff] [blame] | 44 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 45 | /* Top of Upper Usable DRAM, including remap */ |
Arthur Heymans | c6e13b6 | 2018-06-26 21:06:38 +0200 | [diff] [blame] | 46 | touud = pci_read_config16(mch, D0F0_TOUUD); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 47 | touud <<= 20; |
| 48 | |
| 49 | /* Top of Lower Usable DRAM */ |
Arthur Heymans | c6e13b6 | 2018-06-26 21:06:38 +0200 | [diff] [blame] | 50 | tolud = pci_read_config16(mch, D0F0_TOLUD) & 0xfff0; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 51 | tolud <<= 16; |
| 52 | |
| 53 | /* Top of Memory - does not account for any UMA */ |
Arthur Heymans | c6e13b6 | 2018-06-26 21:06:38 +0200 | [diff] [blame] | 54 | tom = pci_read_config16(mch, D0F0_TOM) & 0x01ff; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 55 | tom <<= 26; |
| 56 | |
| 57 | printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", |
| 58 | touud, tolud, tom); |
| 59 | |
| 60 | tomk = tolud >> 10; |
| 61 | |
| 62 | /* Graphics memory comes next */ |
Arthur Heymans | 4c4f56a | 2017-02-27 13:46:11 +0100 | [diff] [blame] | 63 | |
Arthur Heymans | c6e13b6 | 2018-06-26 21:06:38 +0200 | [diff] [blame] | 64 | const u16 ggc = pci_read_config16(mch, D0F0_GGC); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 65 | printk(BIOS_DEBUG, "IGD decoded, subtracting "); |
| 66 | |
| 67 | /* Graphics memory */ |
| 68 | const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf); |
| 69 | printk(BIOS_DEBUG, "%uM UMA", gms_sizek >> 10); |
Arthur Heymans | 4c4f56a | 2017-02-27 13:46:11 +0100 | [diff] [blame] | 70 | tomk -= gms_sizek; |
| 71 | uma_sizek += gms_sizek; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 72 | |
| 73 | /* GTT Graphics Stolen Memory Size (GGMS) */ |
| 74 | const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf); |
| 75 | printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10); |
Arthur Heymans | 4c4f56a | 2017-02-27 13:46:11 +0100 | [diff] [blame] | 76 | tomk -= gsm_sizek; |
| 77 | uma_sizek += gsm_sizek; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 78 | |
Arthur Heymans | 4c4f56a | 2017-02-27 13:46:11 +0100 | [diff] [blame] | 79 | printk(BIOS_DEBUG, "TSEG decoded, subtracting "); |
Arthur Heymans | 4c65bfc | 2018-04-10 13:34:24 +0200 | [diff] [blame] | 80 | const u32 tseg_sizek = decode_tseg_size( |
| 81 | pci_read_config8(dev, D0F0_ESMRAMC)) >> 10; |
Arthur Heymans | 4c4f56a | 2017-02-27 13:46:11 +0100 | [diff] [blame] | 82 | uma_sizek += tseg_sizek; |
| 83 | tomk -= tseg_sizek; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 84 | |
Arthur Heymans | 4c4f56a | 2017-02-27 13:46:11 +0100 | [diff] [blame] | 85 | printk(BIOS_DEBUG, "%dM\n", tseg_sizek >> 10); |
| 86 | |
Arthur Heymans | 17ad459 | 2018-08-06 15:35:28 +0200 | [diff] [blame] | 87 | /* cbmem_top can be shifted downwards due to alignment. |
| 88 | Mark the region between cbmem_top and tomk as unusable */ |
| 89 | delta_cbmem = tomk - ((uint32_t)cbmem_top() >> 10); |
| 90 | tomk -= delta_cbmem; |
| 91 | uma_sizek += delta_cbmem; |
| 92 | |
| 93 | printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%xK\n", |
| 94 | delta_cbmem); |
| 95 | |
Arthur Heymans | 4c4f56a | 2017-02-27 13:46:11 +0100 | [diff] [blame] | 96 | printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 97 | |
| 98 | /* Report the memory regions */ |
Arthur Heymans | 4c4f56a | 2017-02-27 13:46:11 +0100 | [diff] [blame] | 99 | ram_resource(dev, index++, 0, legacy_hole_base_k); |
| 100 | mmio_resource(dev, index++, legacy_hole_base_k, |
| 101 | (0xc0000 >> 10) - legacy_hole_base_k); |
| 102 | reserved_ram_resource(dev, index++, 0xc0000 >> 10, |
| 103 | (0x100000 - 0xc0000) >> 10); |
| 104 | ram_resource(dev, index++, 0x100000 >> 10, (tomk - (0x100000 >> 10))); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 105 | |
| 106 | /* |
| 107 | * If >= 4GB installed then memory from TOLUD to 4GB |
| 108 | * is remapped above TOM, TOUUD will account for both |
| 109 | */ |
| 110 | touud >>= 10; /* Convert to KB */ |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 111 | if (touud > top32memk) { |
| 112 | ram_resource(dev, index++, top32memk, touud - top32memk); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 113 | printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 114 | (touud - top32memk) >> 10); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 115 | } |
| 116 | |
| 117 | printk(BIOS_DEBUG, "Adding UMA memory area base=0x%08x " |
Arthur Heymans | 4c4f56a | 2017-02-27 13:46:11 +0100 | [diff] [blame] | 118 | "size=0x%08x\n", tomk << 10, uma_sizek << 10); |
| 119 | uma_resource(dev, index++, tomk, uma_sizek); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 120 | |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 121 | /* Reserve high memory where the NB BARs are up to 4GiB */ |
| 122 | fixed_mem_resource(dev, index++, DEFAULT_HECIBAR >> 10, |
| 123 | top32memk - (DEFAULT_HECIBAR >> 10), |
| 124 | IORESOURCE_RESERVE); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 125 | |
| 126 | if (decode_pciebar(&pcie_config_base, &pcie_config_size)) { |
| 127 | printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " |
| 128 | "size=0x%x\n", pcie_config_base, pcie_config_size); |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 129 | fixed_mem_resource(dev, index++, pcie_config_base >> 10, |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 130 | pcie_config_size >> 10, IORESOURCE_RESERVE); |
| 131 | } |
| 132 | } |
| 133 | |
Elyes HAOUAS | fea02e1 | 2018-02-08 14:59:03 +0100 | [diff] [blame] | 134 | static void mch_domain_set_resources(struct device *dev) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 135 | { |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 136 | struct resource *res; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 137 | |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 138 | for (res = dev->resource_list; res; res = res->next) |
| 139 | report_resource_stored(dev, res, ""); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 140 | |
| 141 | assign_resources(dev->link_list); |
| 142 | } |
| 143 | |
Elyes HAOUAS | fea02e1 | 2018-02-08 14:59:03 +0100 | [diff] [blame] | 144 | static void mch_domain_init(struct device *dev) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 145 | { |
| 146 | u32 reg32; |
| 147 | |
| 148 | /* Enable SERR */ |
| 149 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 150 | reg32 |= PCI_COMMAND_SERR; |
| 151 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 152 | } |
| 153 | |
Arthur Heymans | a8a9f34 | 2017-12-24 08:11:13 +0100 | [diff] [blame] | 154 | static const char *northbridge_acpi_name(const struct device *dev) |
| 155 | { |
| 156 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 157 | return "PCI0"; |
| 158 | |
| 159 | if (dev->path.type != DEVICE_PATH_PCI || dev->bus->secondary != 0) |
| 160 | return NULL; |
| 161 | |
| 162 | switch (dev->path.pci.devfn) { |
| 163 | case PCI_DEVFN(0, 0): |
| 164 | return "MCHC"; |
| 165 | } |
| 166 | |
| 167 | return NULL; |
| 168 | } |
| 169 | |
Arthur Heymans | 4c65bfc | 2018-04-10 13:34:24 +0200 | [diff] [blame] | 170 | void northbridge_write_smram(u8 smram) |
| 171 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 172 | struct device *dev = pcidev_on_root(0, 0); |
Arthur Heymans | 4c65bfc | 2018-04-10 13:34:24 +0200 | [diff] [blame] | 173 | |
| 174 | if (dev == NULL) |
| 175 | die("could not find pci 00:00.0!\n"); |
| 176 | |
| 177 | pci_write_config8(dev, D0F0_SMRAM, smram); |
| 178 | } |
| 179 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 180 | static struct device_operations pci_domain_ops = { |
| 181 | .read_resources = mch_domain_read_resources, |
| 182 | .set_resources = mch_domain_set_resources, |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 183 | .init = mch_domain_init, |
| 184 | .scan_bus = pci_domain_scan_bus, |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 185 | .write_acpi_tables = northbridge_write_acpi_tables, |
| 186 | .acpi_fill_ssdt_generator = generate_cpu_entries, |
Arthur Heymans | a8a9f34 | 2017-12-24 08:11:13 +0100 | [diff] [blame] | 187 | .acpi_name = northbridge_acpi_name, |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 188 | }; |
| 189 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 190 | static struct device_operations cpu_bus_ops = { |
| 191 | .read_resources = DEVICE_NOOP, |
| 192 | .set_resources = DEVICE_NOOP, |
| 193 | .enable_resources = DEVICE_NOOP, |
Kyösti Mälkki | b3267e0 | 2019-08-13 16:44:04 +0300 | [diff] [blame] | 194 | .init = mp_cpu_bus_init, |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 195 | }; |
| 196 | |
Elyes HAOUAS | fea02e1 | 2018-02-08 14:59:03 +0100 | [diff] [blame] | 197 | static void enable_dev(struct device *dev) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 198 | { |
| 199 | /* Set the operations if it is a special bus type */ |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 200 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 201 | dev->ops = &pci_domain_ops; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 202 | else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 203 | dev->ops = &cpu_bus_ops; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 204 | } |
| 205 | |
Arthur Heymans | a854c9d | 2019-11-27 21:53:01 +0100 | [diff] [blame] | 206 | static void hide_pci_fn(const int dev_bit_base, const struct device *dev) |
| 207 | { |
| 208 | if (!dev || dev->enabled) |
| 209 | return; |
| 210 | const unsigned int fn = PCI_FUNC(dev->path.pci.devfn); |
| 211 | const struct device *const d0f0 = pcidev_on_root(0, 0); |
| 212 | pci_update_config32(d0f0, D0F0_DEVEN, ~(1 << (dev_bit_base + fn)), 0); |
| 213 | } |
| 214 | |
| 215 | static void hide_pci_dev(const int dev, int functions, const int dev_bit_base) |
| 216 | { |
| 217 | for (; functions >= 0; functions--) |
| 218 | hide_pci_fn(dev_bit_base, pcidev_on_root(dev, functions)); |
| 219 | } |
| 220 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 221 | static void x4x_init(void *const chip_info) |
| 222 | { |
Kyösti Mälkki | 98a9174 | 2018-05-21 21:29:16 +0300 | [diff] [blame] | 223 | struct device *const d0f0 = pcidev_on_root(0x0, 0); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 224 | |
| 225 | /* Hide internal functions based on devicetree info. */ |
Arthur Heymans | a854c9d | 2019-11-27 21:53:01 +0100 | [diff] [blame] | 226 | hide_pci_dev(6, 0, 13); /* PEG1: only on P45 */ |
| 227 | hide_pci_dev(3, 3, 6); /* ME */ |
| 228 | hide_pci_dev(2, 1, 3); /* IGD */ |
| 229 | hide_pci_dev(1, 0, 1); /* PEG0 */ |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 230 | |
| 231 | const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN); |
| 232 | if (!(deven & (0xf << 6))) |
| 233 | pci_write_config32(d0f0, D0F0_DEVEN, deven & ~(1 << 14)); |
| 234 | } |
| 235 | |
| 236 | struct chip_operations northbridge_intel_x4x_ops = { |
| 237 | CHIP_NAME("Intel 4-Series Northbridge") |
| 238 | .enable_dev = enable_dev, |
| 239 | .init = x4x_init, |
| 240 | }; |