Stefan Reinauer | 1a08f58 | 2009-10-28 16:52:48 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2008 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
Uwe Hermann | 2d2f0c1 | 2009-10-28 17:36:11 +0000 | [diff] [blame] | 8 | * published by the Free Software Foundation; version 2 of the License. |
Stefan Reinauer | 1a08f58 | 2009-10-28 16:52:48 +0000 | [diff] [blame] | 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
Uwe Hermann | 2d2f0c1 | 2009-10-28 17:36:11 +0000 | [diff] [blame] | 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Stefan Reinauer | 1a08f58 | 2009-10-28 16:52:48 +0000 | [diff] [blame] | 18 | */ |
| 19 | |
Myles Watson | 1d6d45e | 2009-11-06 17:02:51 +0000 | [diff] [blame] | 20 | // __PRE_RAM__ means: use "unsigned" for device, not a struct. |
| 21 | #define __PRE_RAM__ |
Stefan Reinauer | 1a08f58 | 2009-10-28 16:52:48 +0000 | [diff] [blame] | 22 | |
Stefan Reinauer | 67cd802 | 2010-01-16 16:35:38 +0000 | [diff] [blame^] | 23 | /* Configuration of the i945 driver */ |
| 24 | #define CHIPSET_I945GC 1 |
| 25 | #define CHANNEL_XOR_RANDOMIZATION 1 |
| 26 | |
Stefan Reinauer | 1a08f58 | 2009-10-28 16:52:48 +0000 | [diff] [blame] | 27 | #include <stdint.h> |
| 28 | #include <string.h> |
| 29 | #include <arch/io.h> |
| 30 | #include <arch/romcc_io.h> |
| 31 | #include <device/pci_def.h> |
| 32 | #include <device/pnp_def.h> |
| 33 | #include <cpu/x86/lapic.h> |
| 34 | |
| 35 | #include "superio/smsc/lpc47m15x/lpc47m15x.h" |
| 36 | |
| 37 | #include "option_table.h" |
| 38 | #include "pc80/mc146818rtc_early.c" |
| 39 | |
| 40 | #include "pc80/serial.c" |
| 41 | #include "arch/i386/lib/console.c" |
| 42 | #include <cpu/x86/bist.h> |
| 43 | |
| 44 | #if CONFIG_USBDEBUG_DIRECT |
| 45 | #define DBGP_DEFAULT 1 |
| 46 | #include "southbridge/intel/i82801gx/i82801gx_usb_debug.c" |
| 47 | #include "pc80/usbdebug_direct_serial.c" |
| 48 | #endif |
| 49 | |
| 50 | #include "lib/ramtest.c" |
| 51 | #include "southbridge/intel/i82801gx/i82801gx_early_smbus.c" |
Stefan Reinauer | 1a08f58 | 2009-10-28 16:52:48 +0000 | [diff] [blame] | 52 | #include "superio/smsc/lpc47m15x/lpc47m15x_early_serial.c" |
| 53 | |
| 54 | #include "northbridge/intel/i945/udelay.c" |
| 55 | |
| 56 | #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) |
| 57 | |
| 58 | #include "southbridge/intel/i82801gx/i82801gx.h" |
| 59 | static void setup_ich7_gpios(void) |
| 60 | { |
| 61 | /* TODO: This is highly board specific and should be moved */ |
| 62 | printk_debug(" GPIOS..."); |
| 63 | /* General Registers */ |
| 64 | outl(0x3f3df7c1, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ |
| 65 | outl(0xc6fcbfc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ |
| 66 | outl(0xecfefdff, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ |
| 67 | /* Output Control Registers */ |
| 68 | outl(0x00040000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ |
| 69 | /* Input Control Registers */ |
| 70 | outl(0x0000a000, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ |
| 71 | outl(0x000000ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ |
| 72 | outl(0x000000bf, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ |
| 73 | outl(0x000300fd, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ |
| 74 | } |
| 75 | |
| 76 | #include "northbridge/intel/i945/early_init.c" |
| 77 | |
| 78 | static inline int spd_read_byte(unsigned device, unsigned address) |
| 79 | { |
| 80 | return smbus_read_byte(device, address); |
| 81 | } |
| 82 | |
Stefan Reinauer | 1a08f58 | 2009-10-28 16:52:48 +0000 | [diff] [blame] | 83 | #include "northbridge/intel/i945/raminit.h" |
| 84 | #include "northbridge/intel/i945/raminit.c" |
| 85 | #include "northbridge/intel/i945/reset_test.c" |
| 86 | #include "northbridge/intel/i945/errata.c" |
Stefan Reinauer | 67cd802 | 2010-01-16 16:35:38 +0000 | [diff] [blame^] | 87 | #include "northbridge/intel/i945/debug.c" |
Stefan Reinauer | 1a08f58 | 2009-10-28 16:52:48 +0000 | [diff] [blame] | 88 | |
| 89 | static void ich7_enable_lpc(void) |
| 90 | { |
| 91 | // Enable Serial IRQ |
| 92 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); |
| 93 | // Set COM1/COM2 decode range |
| 94 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); |
| 95 | // Enable COM1 |
| 96 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x140d); |
| 97 | // Enable SuperIO Power Management Events |
| 98 | pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0681); |
| 99 | } |
| 100 | |
| 101 | |
| 102 | /* This box has two superios, so enabling serial becomes slightly excessive. |
| 103 | * We disable a lot of stuff to make sure that there are no conflicts between |
| 104 | * the two. Also set up the GPIOs from the beginning. This is the "no schematic |
| 105 | * but safe anyways" method. |
| 106 | */ |
| 107 | static void early_superio_config_lpc47m15x(void) |
| 108 | { |
| 109 | device_t dev; |
| 110 | |
| 111 | dev=PNP_DEV(0x2e, LPC47M15X_SP1); |
| 112 | pnp_enter_conf_state(dev); |
| 113 | |
| 114 | pnp_set_logical_device(dev); |
| 115 | pnp_set_enable(dev, 0); |
| 116 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); |
| 117 | pnp_set_irq(dev, PNP_IDX_IRQ0, 4); |
| 118 | pnp_set_enable(dev, 1); |
| 119 | |
| 120 | /* Enable SuperIO PM */ |
| 121 | dev=PNP_DEV(0x2e, LPC47M15X_PME); |
| 122 | pnp_set_logical_device(dev); |
| 123 | pnp_set_enable(dev, 0); |
| 124 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x680); |
| 125 | pnp_set_enable(dev, 1); |
| 126 | |
| 127 | pnp_exit_conf_state(dev); |
| 128 | } |
| 129 | |
| 130 | static void rcba_config(void) |
| 131 | { |
| 132 | /* Set up virtual channel 0 */ |
| 133 | //RCBA32(0x0014) = 0x80000001; |
| 134 | //RCBA32(0x001c) = 0x03128010; |
| 135 | |
| 136 | /* Device 1f interrupt pin register */ |
| 137 | RCBA32(0x3100) = 0x00042210; |
| 138 | /* Device 1d interrupt pin register */ |
| 139 | RCBA32(0x310c) = 0x00214321; |
| 140 | |
| 141 | /* dev irq route register */ |
| 142 | RCBA16(0x3140) = 0x0132; |
| 143 | RCBA16(0x3142) = 0x0146; |
| 144 | RCBA16(0x3144) = 0x0237; |
| 145 | RCBA16(0x3146) = 0x3201; |
| 146 | RCBA16(0x3148) = 0x0146; |
| 147 | |
| 148 | /* Enable IOAPIC */ |
| 149 | RCBA8(0x31ff) = 0x03; |
| 150 | |
| 151 | /* Enable upper 128bytes of CMOS */ |
| 152 | RCBA32(0x3400) = (1 << 2); |
| 153 | |
| 154 | /* Disable unused devices */ |
| 155 | //RCBA32(0x3418) = FD_PCIE6|FD_PCIE5|FD_PCIE4|FD_ACMOD|FD_ACAUD|FD_PATA; |
| 156 | // RCBA32(0x3418) |= (1 << 0); // Required. |
| 157 | // FIXME look me up! |
| 158 | RCBA32(0x3418) = 0x003204e1; |
| 159 | |
| 160 | /* Enable PCIe Root Port Clock Gate */ |
| 161 | // RCBA32(0x341c) = 0x00000001; |
| 162 | } |
| 163 | |
| 164 | static void early_ich7_init(void) |
| 165 | { |
| 166 | uint8_t reg8; |
| 167 | uint32_t reg32; |
| 168 | |
| 169 | // program secondary mlt XXX byte? |
| 170 | pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); |
| 171 | |
| 172 | // reset rtc power status |
| 173 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); |
| 174 | reg8 &= ~(1 << 2); |
| 175 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); |
| 176 | |
| 177 | // usb transient disconnect |
| 178 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); |
| 179 | reg8 |= (3 << 0); |
| 180 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); |
| 181 | |
| 182 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); |
| 183 | reg32 |= (1 << 29) | (1 << 17); |
| 184 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); |
| 185 | |
| 186 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); |
| 187 | reg32 |= (1 << 31) | (1 << 27); |
| 188 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); |
| 189 | |
| 190 | RCBA32(0x0088) = 0x0011d000; |
| 191 | RCBA16(0x01fc) = 0x060f; |
| 192 | RCBA32(0x01f4) = 0x86000040; |
| 193 | RCBA32(0x0214) = 0x10030549; |
| 194 | RCBA32(0x0218) = 0x00020504; |
| 195 | RCBA8(0x0220) = 0xc5; |
| 196 | reg32 = RCBA32(0x3410); |
| 197 | reg32 |= (1 << 6); |
| 198 | RCBA32(0x3410) = reg32; |
| 199 | reg32 = RCBA32(0x3430); |
| 200 | reg32 &= ~(3 << 0); |
| 201 | reg32 |= (1 << 0); |
| 202 | RCBA32(0x3430) = reg32; |
| 203 | RCBA32(0x3418) |= (1 << 0); |
| 204 | RCBA16(0x0200) = 0x2008; |
| 205 | RCBA8(0x2027) = 0x0d; |
| 206 | RCBA16(0x3e08) |= (1 << 7); |
| 207 | RCBA16(0x3e48) |= (1 << 7); |
| 208 | RCBA32(0x3e0e) |= (1 << 7); |
| 209 | RCBA32(0x3e4e) |= (1 << 7); |
| 210 | |
| 211 | // next step only on ich7m b0 and later: |
| 212 | reg32 = RCBA32(0x2034); |
| 213 | reg32 &= ~(0x0f << 16); |
| 214 | reg32 |= (5 << 16); |
| 215 | RCBA32(0x2034) = reg32; |
| 216 | } |
| 217 | |
| 218 | #if CONFIG_USE_FALLBACK_IMAGE == 1 |
| 219 | #include "southbridge/intel/i82801gx/cmos_failover.c" |
| 220 | #endif |
| 221 | |
| 222 | #include <cbmem.h> |
| 223 | |
| 224 | // Now, this needs to be included because it relies on the symbol |
Myles Watson | 1d6d45e | 2009-11-06 17:02:51 +0000 | [diff] [blame] | 225 | // __PRE_RAM__ being set during CAR stage (in order to compile the |
Stefan Reinauer | 1a08f58 | 2009-10-28 16:52:48 +0000 | [diff] [blame] | 226 | // BSS free versions of the functions). Either rewrite the code |
| 227 | // to be always BSS free, or invent a flag that's better suited than |
Myles Watson | 1d6d45e | 2009-11-06 17:02:51 +0000 | [diff] [blame] | 228 | // __PRE_RAM__ to determine whether we're in ram init stage (stage 1) |
Stefan Reinauer | 1a08f58 | 2009-10-28 16:52:48 +0000 | [diff] [blame] | 229 | // |
| 230 | #include "lib/cbmem.c" |
| 231 | |
| 232 | void real_main(unsigned long bist) |
| 233 | { |
| 234 | u32 reg32; |
| 235 | int boot_mode = 0; |
| 236 | |
| 237 | if (bist == 0) { |
| 238 | enable_lapic(); |
| 239 | } |
| 240 | |
| 241 | ich7_enable_lpc(); |
| 242 | early_superio_config_lpc47m15x(); |
| 243 | |
| 244 | /* Set up the console */ |
| 245 | uart_init(); |
| 246 | |
| 247 | #if CONFIG_USBDEBUG_DIRECT |
| 248 | i82801gx_enable_usbdebug_direct(DBGP_DEFAULT); |
| 249 | early_usbdebug_direct_init(); |
| 250 | #endif |
| 251 | |
| 252 | console_init(); |
| 253 | |
| 254 | /* Halt if there was a built in self test failure */ |
| 255 | report_bist_failure(bist); |
| 256 | |
| 257 | if (MCHBAR16(SSKPD) == 0xCAFE) { |
| 258 | printk_debug("soft reset detected.\n"); |
| 259 | boot_mode = 1; |
| 260 | } |
| 261 | |
| 262 | /* Perform some early chipset initialization required |
| 263 | * before RAM initialization can work |
| 264 | */ |
| 265 | i945_early_initialization(); |
| 266 | |
| 267 | /* Read PM1_CNT */ |
| 268 | reg32 = inl(DEFAULT_PMBASE + 0x04); |
| 269 | printk_debug("PM1_CNT: %08x\n", reg32); |
| 270 | if (((reg32 >> 10) & 7) == 5) { |
| 271 | #if CONFIG_HAVE_ACPI_RESUME |
| 272 | printk_debug("Resume from S3 detected.\n"); |
| 273 | boot_mode = 2; |
| 274 | /* Clear SLP_TYPE. This will break stage2 but |
| 275 | * we care for that when we get there. |
| 276 | */ |
| 277 | outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); |
| 278 | #else |
| 279 | printk_debug("Resume from S3 detected, but disabled.\n"); |
| 280 | #endif |
| 281 | } |
| 282 | |
| 283 | /* Enable SPD ROMs and DDR-II DRAM */ |
| 284 | enable_smbus(); |
| 285 | |
| 286 | #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 |
| 287 | dump_spd_registers(); |
| 288 | #endif |
| 289 | |
| 290 | sdram_initialize(boot_mode); |
| 291 | |
| 292 | /* Perform some initialization that must run before stage2 */ |
| 293 | early_ich7_init(); |
| 294 | |
| 295 | /* This should probably go away. Until now it is required |
| 296 | * and mainboard specific |
| 297 | */ |
| 298 | rcba_config(); |
| 299 | |
| 300 | /* Chipset Errata! */ |
| 301 | fixup_i945_errata(); |
| 302 | |
| 303 | /* Initialize the internal PCIe links before we go into stage2 */ |
| 304 | i945_late_initialization(); |
| 305 | |
| 306 | #if !CONFIG_HAVE_ACPI_RESUME |
| 307 | #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 |
| 308 | #if defined(DEBUG_RAM_SETUP) |
| 309 | sdram_dump_mchbar_registers(); |
| 310 | #endif |
| 311 | |
| 312 | { |
| 313 | /* This will not work if TSEG is in place! */ |
| 314 | u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); |
| 315 | |
| 316 | printk_debug("TOM: 0x%08x\n", tom); |
| 317 | ram_check(0x00000000, 0x000a0000); |
| 318 | //ram_check(0x00100000, tom); |
| 319 | } |
| 320 | #endif |
| 321 | #endif |
| 322 | |
| 323 | MCHBAR16(SSKPD) = 0xCAFE; |
| 324 | |
| 325 | #if CONFIG_HAVE_ACPI_RESUME |
| 326 | /* Start address of high memory tables */ |
| 327 | unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; |
| 328 | |
| 329 | /* If there is no high memory area, we didn't boot before, so |
| 330 | * this is not a resume. In that case we just create the cbmem toc. |
| 331 | */ |
| 332 | if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) { |
| 333 | void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); |
| 334 | |
| 335 | /* copy 1MB - 64K to high tables ram_base to prevent memory corruption |
| 336 | * through stage 2. We could keep stuff like stack and heap in high tables |
| 337 | * memory completely, but that's a wonderful clean up task for another |
| 338 | * day. |
| 339 | */ |
| 340 | if (resume_backup_memory) |
| 341 | memcpy(resume_backup_memory, CONFIG_RAMBASE, HIGH_MEMORY_SAVE); |
| 342 | |
| 343 | /* Magic for S3 resume */ |
| 344 | pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); |
| 345 | } |
| 346 | #endif |
| 347 | } |
| 348 | |
| 349 | #include "cpu/intel/model_106cx/cache_as_ram_disable.c" |