blob: b7744cb3491afacf27725acea915eecc4dc9a869 [file] [log] [blame]
Iru Cai03e96a82017-01-26 14:51:47 +08001# This file is part of the coreboot project.
Elyes HAOUAS674ad922020-05-09 13:21:47 +02002# SPDX-License-Identifier: GPL-2.0-or-later
Iru Cai03e96a82017-01-26 14:51:47 +08003
4chip northbridge/intel/sandybridge
5 register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
Iru Cai03e96a82017-01-26 14:51:47 +08006 register "gfx.ndid" = "3"
7 register "gfx.use_spread_spectrum_clock" = "1"
8 register "gpu_cpu_backlight" = "0x00000129"
9 register "gpu_dp_b_hotplug" = "4"
10 register "gpu_dp_c_hotplug" = "4"
11 register "gpu_dp_d_hotplug" = "4"
12 register "gpu_panel_port_select" = "0"
13 register "gpu_panel_power_backlight_off_delay" = "2000"
14 register "gpu_panel_power_backlight_on_delay" = "2000"
15 register "gpu_panel_power_cycle_delay" = "5"
16 register "gpu_panel_power_down_delay" = "230"
17 register "gpu_panel_power_up_delay" = "300"
18 register "gpu_pch_backlight" = "0x02880288"
19 device cpu_cluster 0x0 on
Iru Cai03e96a82017-01-26 14:51:47 +080020 chip cpu/intel/model_206ax
21 register "c1_acpower" = "1"
22 register "c1_battery" = "1"
23 register "c2_acpower" = "3"
24 register "c2_battery" = "3"
25 register "c3_acpower" = "5"
26 register "c3_battery" = "5"
Arthur Heymans7e6946a2019-01-21 17:55:02 +010027 device lapic 0x0 on end
Arthur Heymansb3f23232019-01-21 17:48:55 +010028 device lapic 0xacac off end
Iru Cai03e96a82017-01-26 14:51:47 +080029 end
30 end
31 device domain 0x0 on
Angel Ponsa0a3eab2020-01-01 20:52:11 +010032
Angel Ponsc97802f2020-01-01 21:27:43 +010033 device pci 00.0 on end # Host bridge
Iru Cai03e96a82017-01-26 14:51:47 +080034
Angel Pons42d30052020-01-02 00:57:52 +010035 chip southbridge/intel/bd82x6x # Intel Cougar or Panther Point PCH
Iru Cai03e96a82017-01-26 14:51:47 +080036 register "c2_latency" = "0x0065"
Iru Cai03e96a82017-01-26 14:51:47 +080037 register "pcie_port_coalesce" = "1"
38 register "sata_interface_speed_support" = "0x3"
Iru Cai03e96a82017-01-26 14:51:47 +080039 register "spi_uvscc" = "0x2005"
40 register "spi_lvscc" = "0"
41
Angel Ponsa0a3eab2020-01-01 20:52:11 +010042 device pci 16.0 on end # Management Engine Interface 1
43 device pci 16.1 off end # Management Engine Interface 2
44 device pci 16.2 off end # Management Engine IDE-R
45 device pci 16.3 off end # Management Engine KT
46 device pci 19.0 on end # Intel Gigabit Ethernet
47 device pci 1a.0 on end # USB2 EHCI #2
Angel Ponsc97802f2020-01-01 21:27:43 +010048 device pci 1b.0 on end # HD Audio controller
Angel Ponsa0a3eab2020-01-01 20:52:11 +010049 device pci 1d.0 on end # USB2 EHCI #1
50 device pci 1e.0 off end # PCI bridge
Angel Pons42d30052020-01-02 00:57:52 +010051 device pci 1f.0 on end # LPC bridge
Angel Ponsa0a3eab2020-01-01 20:52:11 +010052 device pci 1f.2 on end # SATA Controller 1
Angel Pons12197db2020-01-01 21:31:21 +010053 device pci 1f.3 on end # SMBus
Angel Ponsa0a3eab2020-01-01 20:52:11 +010054 device pci 1f.5 off end # SATA Controller 2
55 device pci 1f.6 off end # Thermal
Iru Cai03e96a82017-01-26 14:51:47 +080056 end
57 end
58end