mainboard/hp: Add HP Elitebook 2760p
The code is generated by autoport.
The flash chip is socketed beside the WLAN slot. The EHCI debug port
is on right side of the laptop beside the RJ11 connector.
Things that work:
- memory: 0+8G, 4G+8G
- Linux (Linux Mint 18.1 with Linux 4.4)
- native graphics init + SeaBIOS payload with SeaVGABIOS
- all 3 USB ports
- WLAN
- WWAN
- SD card reader
- expresscard
- S3 suspend and resume
- internal flashing after IFD is unlocked and coreboot is flashed
- keyboard, trackpoint and touchpad
- fan control
- AC and battery status
Issues:
- Wacom digitizer does not work (even after I add it in DSDT)
- GRUB payload will freeze (in all Elitebooks, including chainloading GRUB
from SeaBIOS)
Things that are not tested:
- smart card reader
- cable modem
(EC) blobs:
This laptop uses SMSC KBC1126-NU as EC. It needs two blobs in the
flash chip. You can use the tools in util/kbc1126 to extract them
from OEM firmware, and use the following configuration to insert
them to coreboot image:
-> Chipset
-> Add firmware images for KBC1126 firmware
Change-Id: I3ffdb9f9c71f6c9a84e896abc3c424c8dd4bed0e
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/18241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/src/mainboard/hp/2760p/devicetree.cb b/src/mainboard/hp/2760p/devicetree.cb
new file mode 100644
index 0000000..5728ad9
--- /dev/null
+++ b/src/mainboard/hp/2760p/devicetree.cb
@@ -0,0 +1,139 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+chip northbridge/intel/sandybridge
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
+ register "gfx.link_frequency_270_mhz" = "1"
+ register "gfx.ndid" = "3"
+ register "gfx.use_spread_spectrum_clock" = "1"
+ register "gpu_cpu_backlight" = "0x00000129"
+ register "gpu_dp_b_hotplug" = "4"
+ register "gpu_dp_c_hotplug" = "4"
+ register "gpu_dp_d_hotplug" = "4"
+ register "gpu_panel_port_select" = "0"
+ register "gpu_panel_power_backlight_off_delay" = "2000"
+ register "gpu_panel_power_backlight_on_delay" = "2000"
+ register "gpu_panel_power_cycle_delay" = "5"
+ register "gpu_panel_power_down_delay" = "230"
+ register "gpu_panel_power_up_delay" = "300"
+ register "gpu_pch_backlight" = "0x02880288"
+ device cpu_cluster 0x0 on
+ chip cpu/intel/socket_rPGA989
+ device lapic 0x0 on
+ end
+ end
+ chip cpu/intel/model_206ax
+ register "c1_acpower" = "1"
+ register "c1_battery" = "1"
+ register "c2_acpower" = "3"
+ register "c2_battery" = "3"
+ register "c3_acpower" = "5"
+ register "c3_battery" = "5"
+ device lapic 0xacac off
+ end
+ end
+ end
+ device domain 0x0 on
+ device pci 00.0 on # Host bridge Host bridge
+ subsystemid 0x103c 0x162a
+ end
+ device pci 01.0 off # PCIe Bridge for discrete graphics
+ end
+ device pci 02.0 on # Internal graphics VGA controller
+ subsystemid 0x103c 0x162a
+ end
+
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "c2_latency" = "0x0065"
+ register "docking_supported" = "0"
+ register "gen1_dec" = "0x007c0201"
+ register "gen2_dec" = "0x000c0101"
+ register "gen3_dec" = "0x00fcfe01"
+ register "gen4_dec" = "0x007c0281"
+ register "gpi6_routing" = "2"
+ register "p_cnt_throttling_supported" = "1"
+ register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x21"
+
+ register "spi_uvscc" = "0x2005"
+ register "spi_lvscc" = "0"
+
+ device pci 16.0 on # Management Engine Interface 1
+ subsystemid 0x103c 0x162a
+ end
+ device pci 16.1 off # Management Engine Interface 2
+ end
+ device pci 16.2 off # Management Engine IDE-R
+ end
+ device pci 16.3 off # Management Engine KT
+ end
+ device pci 19.0 on # Intel Gigabit Ethernet
+ subsystemid 0x103c 0x162a
+ end
+ device pci 1a.0 on # USB2 EHCI #2
+ subsystemid 0x103c 0x162a
+ end
+ device pci 1b.0 on # High Definition Audio Audio controller
+ subsystemid 0x103c 0x162a
+ end
+ device pci 1c.0 on # PCIe Port #1
+ subsystemid 0x103c 0x162a
+ end
+ device pci 1c.1 on # PCIe Port #2
+ subsystemid 0x103c 0x162a
+ end
+ device pci 1c.2 on # PCIe Port #3
+ subsystemid 0x103c 0x162a
+ end
+ device pci 1c.3 on # WLAN
+ end
+ device pci 1c.4 off # PCIe Port #5
+ end
+ device pci 1c.5 off # PCIe Port #6
+ end
+ device pci 1c.6 off # PCIe Port #7
+ end
+ device pci 1c.7 off # PCIe Port #8
+ end
+ device pci 1d.0 on # USB2 EHCI #1
+ subsystemid 0x103c 0x162a
+ end
+ device pci 1e.0 off # PCI bridge
+ end
+ device pci 1f.0 on # LPC bridge PCI-LPC bridge
+ subsystemid 0x103c 0x162a
+ chip ec/hp/kbc1126
+ register "ec_data_port" = "0x60"
+ register "ec_cmd_port" = "0x64"
+ register "ec_ctrl_reg" = "0xca"
+ register "ec_fan_ctrl_value" = "0x4d"
+ device pnp ff.1 off end
+ end # kbc1126
+ end
+ device pci 1f.2 on # SATA Controller 1
+ subsystemid 0x103c 0x162a
+ end
+ device pci 1f.3 off # SMBus
+ end
+ device pci 1f.5 off # SATA Controller 2
+ end
+ device pci 1f.6 off # Thermal
+ end
+ end
+ end
+end