blob: 639954bcfec375468fb38daf1c43a53fb732ce6a [file] [log] [blame]
Aaron Durbin9a7d7bc2013-09-07 00:41:48 -05001/*
2 * Copyright (c) 2013 Google Inc.
3 *
Aaron Durbin9a7d7bc2013-09-07 00:41:48 -05004 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but without any warranty; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
Aaron Durbin9a7d7bc2013-09-07 00:41:48 -050013 */
14
15/* This file is derived from the flashrom project. */
16#include <stdint.h>
17#include <stdlib.h>
18#include <string.h>
David Hendricksf2612a12014-04-13 16:27:02 -070019#include <bootstate.h>
Aaron Durbin9a7d7bc2013-09-07 00:41:48 -050020#include <delay.h>
21#include <arch/io.h>
22#include <console/console.h>
23#include <device/pci_ids.h>
Furquan Shaikh52896c62016-11-22 11:43:58 -080024#include <spi_flash.h>
Furquan Shaikhc28984d2016-11-20 21:04:00 -080025#include <spi-generic.h>
Aaron Durbin9a7d7bc2013-09-07 00:41:48 -050026
Julius Werner18ea2d32014-10-07 16:42:17 -070027#include <soc/lpc.h>
28#include <soc/pci_devs.h>
Aaron Durbin9a7d7bc2013-09-07 00:41:48 -050029
30#ifdef __SMM__
31#define pci_read_config_byte(dev, reg, targ)\
32 *(targ) = pci_read_config8(dev, reg)
33#define pci_read_config_word(dev, reg, targ)\
34 *(targ) = pci_read_config16(dev, reg)
35#define pci_read_config_dword(dev, reg, targ)\
36 *(targ) = pci_read_config32(dev, reg)
37#define pci_write_config_byte(dev, reg, val)\
38 pci_write_config8(dev, reg, val)
39#define pci_write_config_word(dev, reg, val)\
40 pci_write_config16(dev, reg, val)
41#define pci_write_config_dword(dev, reg, val)\
42 pci_write_config32(dev, reg, val)
43#else /* !__SMM__ */
44#include <device/device.h>
45#include <device/pci.h>
46#define pci_read_config_byte(dev, reg, targ)\
47 *(targ) = pci_read_config8(dev, reg)
48#define pci_read_config_word(dev, reg, targ)\
49 *(targ) = pci_read_config16(dev, reg)
50#define pci_read_config_dword(dev, reg, targ)\
51 *(targ) = pci_read_config32(dev, reg)
52#define pci_write_config_byte(dev, reg, val)\
53 pci_write_config8(dev, reg, val)
54#define pci_write_config_word(dev, reg, val)\
55 pci_write_config16(dev, reg, val)
56#define pci_write_config_dword(dev, reg, val)\
57 pci_write_config32(dev, reg, val)
58#endif /* !__SMM__ */
59
60typedef struct spi_slave ich_spi_slave;
61
62static int ichspi_lock = 0;
63
64typedef struct ich9_spi_regs {
65 uint32_t bfpr;
66 uint16_t hsfs;
67 uint16_t hsfc;
68 uint32_t faddr;
69 uint32_t _reserved0;
70 uint32_t fdata[16];
71 uint32_t frap;
72 uint32_t freg[5];
73 uint32_t _reserved1[3];
74 uint32_t pr[5];
75 uint32_t _reserved2[2];
76 uint8_t ssfs;
77 uint8_t ssfc[3];
78 uint16_t preop;
79 uint16_t optype;
80 uint8_t opmenu[8];
81 uint32_t bbar;
82 uint8_t _reserved3[12];
83 uint32_t fdoc;
84 uint32_t fdod;
85 uint8_t _reserved4[8];
86 uint32_t afc;
87 uint32_t lvscc;
88 uint32_t uvscc;
89 uint8_t _reserved5[4];
90 uint32_t fpb;
91 uint8_t _reserved6[28];
92 uint32_t srdl;
93 uint32_t srdc;
94 uint32_t srd;
95} __attribute__((packed)) ich9_spi_regs;
96
97typedef struct ich_spi_controller {
98 int locked;
99
100 uint8_t *opmenu;
101 int menubytes;
102 uint16_t *preop;
103 uint16_t *optype;
104 uint32_t *addr;
105 uint8_t *data;
106 unsigned databytes;
107 uint8_t *status;
108 uint16_t *control;
109 uint32_t *bbar;
110} ich_spi_controller;
111
112static ich_spi_controller cntlr;
113
114enum {
115 SPIS_SCIP = 0x0001,
116 SPIS_GRANT = 0x0002,
117 SPIS_CDS = 0x0004,
118 SPIS_FCERR = 0x0008,
119 SSFS_AEL = 0x0010,
120 SPIS_LOCK = 0x8000,
121 SPIS_RESERVED_MASK = 0x7ff0,
122 SSFS_RESERVED_MASK = 0x7fe2
123};
124
125enum {
126 SPIC_SCGO = 0x000002,
127 SPIC_ACS = 0x000004,
128 SPIC_SPOP = 0x000008,
129 SPIC_DBC = 0x003f00,
130 SPIC_DS = 0x004000,
131 SPIC_SME = 0x008000,
132 SSFC_SCF_MASK = 0x070000,
133 SSFC_RESERVED = 0xf80000
134};
135
136enum {
137 HSFS_FDONE = 0x0001,
138 HSFS_FCERR = 0x0002,
139 HSFS_AEL = 0x0004,
140 HSFS_BERASE_MASK = 0x0018,
141 HSFS_BERASE_SHIFT = 3,
142 HSFS_SCIP = 0x0020,
143 HSFS_FDOPSS = 0x2000,
144 HSFS_FDV = 0x4000,
145 HSFS_FLOCKDN = 0x8000
146};
147
148enum {
149 HSFC_FGO = 0x0001,
150 HSFC_FCYCLE_MASK = 0x0006,
151 HSFC_FCYCLE_SHIFT = 1,
152 HSFC_FDBC_MASK = 0x3f00,
153 HSFC_FDBC_SHIFT = 8,
154 HSFC_FSMIE = 0x8000
155};
156
157enum {
158 SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0,
159 SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1,
160 SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2,
161 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3
162};
163
164#if CONFIG_DEBUG_SPI_FLASH
165
166static u8 readb_(const void *addr)
167{
168 u8 v = read8((unsigned long)addr);
169 printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
170 v, ((unsigned) addr & 0xffff) - 0xf020);
171 return v;
172}
173
174static u16 readw_(const void *addr)
175{
176 u16 v = read16((unsigned long)addr);
177 printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
178 v, ((unsigned) addr & 0xffff) - 0xf020);
179 return v;
180}
181
182static u32 readl_(const void *addr)
183{
184 u32 v = read32((unsigned long)addr);
185 printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
186 v, ((unsigned) addr & 0xffff) - 0xf020);
187 return v;
188}
189
190static void writeb_(u8 b, const void *addr)
191{
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800192 write8(addr, b);
Aaron Durbin9a7d7bc2013-09-07 00:41:48 -0500193 printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
194 b, ((unsigned) addr & 0xffff) - 0xf020);
195}
196
197static void writew_(u16 b, const void *addr)
198{
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800199 write16(addr, b);
Aaron Durbin9a7d7bc2013-09-07 00:41:48 -0500200 printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
201 b, ((unsigned) addr & 0xffff) - 0xf020);
202}
203
204static void writel_(u32 b, const void *addr)
205{
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800206 write32(addr, b);
Aaron Durbin9a7d7bc2013-09-07 00:41:48 -0500207 printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
208 b, ((unsigned) addr & 0xffff) - 0xf020);
209}
210
211#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
212
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800213#define readb_(a) read8(a)
214#define readw_(a) read16(a)
215#define readl_(a) read32(a)
216#define writeb_(val, addr) write8(addr, val)
217#define writew_(val, addr) write16(addr, val)
218#define writel_(val, addr) write32(addr, val)
Aaron Durbin9a7d7bc2013-09-07 00:41:48 -0500219
220#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */
221
222static void write_reg(const void *value, void *dest, uint32_t size)
223{
224 const uint8_t *bvalue = value;
225 uint8_t *bdest = dest;
226
227 while (size >= 4) {
228 writel_(*(const uint32_t *)bvalue, bdest);
229 bdest += 4; bvalue += 4; size -= 4;
230 }
231 while (size) {
232 writeb_(*bvalue, bdest);
233 bdest++; bvalue++; size--;
234 }
235}
236
237static void read_reg(const void *src, void *value, uint32_t size)
238{
239 const uint8_t *bsrc = src;
240 uint8_t *bvalue = value;
241
242 while (size >= 4) {
243 *(uint32_t *)bvalue = readl_(bsrc);
244 bsrc += 4; bvalue += 4; size -= 4;
245 }
246 while (size) {
247 *bvalue = readb_(bsrc);
248 bsrc++; bvalue++; size--;
249 }
250}
251
252static void ich_set_bbar(uint32_t minaddr)
253{
254 const uint32_t bbar_mask = 0x00ffff00;
255 uint32_t ichspi_bbar;
256
257 minaddr &= bbar_mask;
258 ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask;
259 ichspi_bbar |= minaddr;
260 writel_(ichspi_bbar, cntlr.bbar);
261}
262
Aaron Durbin9a7d7bc2013-09-07 00:41:48 -0500263static ich9_spi_regs *spi_regs(void)
264{
265 device_t dev;
266 uint32_t sbase;
267
268#ifdef __SMM__
269 dev = PCI_DEV(0, LPC_DEV, LPC_FUNC);
270#else
271 dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
272#endif
273 pci_read_config_dword(dev, SBASE, &sbase);
274 sbase &= ~0x1ff;
275
276 return (void *)sbase;
277}
278
279void spi_init(void)
280{
281 ich9_spi_regs *ich9_spi = spi_regs();
282
283 ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN;
284 cntlr.opmenu = ich9_spi->opmenu;
285 cntlr.menubytes = sizeof(ich9_spi->opmenu);
286 cntlr.optype = &ich9_spi->optype;
287 cntlr.addr = &ich9_spi->faddr;
288 cntlr.data = (uint8_t *)ich9_spi->fdata;
289 cntlr.databytes = sizeof(ich9_spi->fdata);
290 cntlr.status = &ich9_spi->ssfs;
291 cntlr.control = (uint16_t *)ich9_spi->ssfc;
292 cntlr.bbar = &ich9_spi->bbar;
293 cntlr.preop = &ich9_spi->preop;
294 ich_set_bbar(0);
295}
296
David Hendricksf2612a12014-04-13 16:27:02 -0700297static void spi_init_cb(void *unused)
298{
299 spi_init();
300}
301
Aaron Durbin9ef9d852015-03-16 17:30:09 -0500302BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL);
David Hendricksf2612a12014-04-13 16:27:02 -0700303
Aaron Durbin9a7d7bc2013-09-07 00:41:48 -0500304typedef struct spi_transaction {
305 const uint8_t *out;
306 uint32_t bytesout;
307 uint8_t *in;
308 uint32_t bytesin;
309 uint8_t type;
310 uint8_t opcode;
311 uint32_t offset;
312} spi_transaction;
313
314static inline void spi_use_out(spi_transaction *trans, unsigned bytes)
315{
316 trans->out += bytes;
317 trans->bytesout -= bytes;
318}
319
320static inline void spi_use_in(spi_transaction *trans, unsigned bytes)
321{
322 trans->in += bytes;
323 trans->bytesin -= bytes;
324}
325
326static void spi_setup_type(spi_transaction *trans)
327{
328 trans->type = 0xFF;
329
330 /* Try to guess spi type from read/write sizes. */
331 if (trans->bytesin == 0) {
332 if (trans->bytesout > 4)
333 /*
334 * If bytesin = 0 and bytesout > 4, we presume this is
335 * a write data operation, which is accompanied by an
336 * address.
337 */
338 trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
339 else
340 trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
341 return;
342 }
343
344 if (trans->bytesout == 1) { /* and bytesin is > 0 */
345 trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
346 return;
347 }
348
349 if (trans->bytesout == 4) { /* and bytesin is > 0 */
350 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
351 }
352
353 /* Fast read command is called with 5 bytes instead of 4 */
354 if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) {
355 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
356 --trans->bytesout;
357 }
358}
359
360static int spi_setup_opcode(spi_transaction *trans)
361{
362 uint16_t optypes;
363 uint8_t opmenu[cntlr.menubytes];
364
365 trans->opcode = trans->out[0];
366 spi_use_out(trans, 1);
367 if (!ichspi_lock) {
368 /* The lock is off, so just use index 0. */
369 writeb_(trans->opcode, cntlr.opmenu);
370 optypes = readw_(cntlr.optype);
371 optypes = (optypes & 0xfffc) | (trans->type & 0x3);
372 writew_(optypes, cntlr.optype);
373 return 0;
374 } else {
375 /* The lock is on. See if what we need is on the menu. */
376 uint8_t optype;
377 uint16_t opcode_index;
378
379 /* Write Enable is handled as atomic prefix */
380 if (trans->opcode == SPI_OPCODE_WREN)
381 return 0;
382
383 read_reg(cntlr.opmenu, opmenu, sizeof(opmenu));
384 for (opcode_index = 0; opcode_index < cntlr.menubytes;
385 opcode_index++) {
386 if (opmenu[opcode_index] == trans->opcode)
387 break;
388 }
389
390 if (opcode_index == cntlr.menubytes) {
391 printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n",
392 trans->opcode);
393 return -1;
394 }
395
396 optypes = readw_(cntlr.optype);
397 optype = (optypes >> (opcode_index * 2)) & 0x3;
398 if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS &&
399 optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS &&
400 trans->bytesout >= 3) {
401 /* We guessed wrong earlier. Fix it up. */
402 trans->type = optype;
403 }
404 if (optype != trans->type) {
405 printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n",
406 optype);
407 return -1;
408 }
409 return opcode_index;
410 }
411}
412
413static int spi_setup_offset(spi_transaction *trans)
414{
415 /* Separate the SPI address and data. */
416 switch (trans->type) {
417 case SPI_OPCODE_TYPE_READ_NO_ADDRESS:
418 case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS:
419 return 0;
420 case SPI_OPCODE_TYPE_READ_WITH_ADDRESS:
421 case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS:
422 trans->offset = ((uint32_t)trans->out[0] << 16) |
423 ((uint32_t)trans->out[1] << 8) |
424 ((uint32_t)trans->out[2] << 0);
425 spi_use_out(trans, 3);
426 return 1;
427 default:
428 printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", trans->type);
429 return -1;
430 }
431}
432
433/*
434 * Wait for up to 60ms til status register bit(s) turn 1 (in case wait_til_set
435 * below is True) or 0. In case the wait was for the bit(s) to set - write
436 * those bits back, which would cause resetting them.
437 *
438 * Return the last read status value on success or -1 on failure.
439 */
440static int ich_status_poll(u16 bitmask, int wait_til_set)
441{
Aaron Durbin4177db52014-02-05 14:55:26 -0600442 int timeout = 40000; /* This will result in 400 ms */
Aaron Durbin9a7d7bc2013-09-07 00:41:48 -0500443 u16 status = 0;
444
445 while (timeout--) {
446 status = readw_(cntlr.status);
447 if (wait_til_set ^ ((status & bitmask) == 0)) {
448 if (wait_til_set)
449 writew_((status & bitmask), cntlr.status);
450 return status;
451 }
452 udelay(10);
453 }
454
455 printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, expected %x\n",
456 status, bitmask);
457 return -1;
458}
459
Kyösti Mälkki11104952014-06-29 16:17:33 +0300460unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len)
461{
462 return min(cntlr.databytes, buf_len);
463}
464
Furquan Shaikh94f86992016-12-01 07:12:32 -0800465static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
466 size_t bytesout, void *din, size_t bytesin)
Aaron Durbin9a7d7bc2013-09-07 00:41:48 -0500467{
468 uint16_t control;
469 int16_t opcode_index;
470 int with_address;
471 int status;
472
473 spi_transaction trans = {
Gabe Black93d9f922014-03-27 21:52:43 -0700474 dout, bytesout,
475 din, bytesin,
Aaron Durbin9a7d7bc2013-09-07 00:41:48 -0500476 0xff, 0xff, 0
477 };
478
479 /* There has to always at least be an opcode. */
Gabe Black93d9f922014-03-27 21:52:43 -0700480 if (!bytesout || !dout) {
Aaron Durbin9a7d7bc2013-09-07 00:41:48 -0500481 printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n");
482 return -1;
483 }
484 /* Make sure if we read something we have a place to put it. */
Gabe Black93d9f922014-03-27 21:52:43 -0700485 if (bytesin != 0 && !din) {
Aaron Durbin9a7d7bc2013-09-07 00:41:48 -0500486 printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n");
487 return -1;
488 }
Aaron Durbin9a7d7bc2013-09-07 00:41:48 -0500489
490 if (ich_status_poll(SPIS_SCIP, 0) == -1)
491 return -1;
492
493 writew_(SPIS_CDS | SPIS_FCERR, cntlr.status);
494
495 spi_setup_type(&trans);
496 if ((opcode_index = spi_setup_opcode(&trans)) < 0)
497 return -1;
498 if ((with_address = spi_setup_offset(&trans)) < 0)
499 return -1;
500
501 if (trans.opcode == SPI_OPCODE_WREN) {
502 /*
503 * Treat Write Enable as Atomic Pre-Op if possible
504 * in order to prevent the Management Engine from
505 * issuing a transaction between WREN and DATA.
506 */
507 if (!ichspi_lock)
508 writew_(trans.opcode, cntlr.preop);
509 return 0;
510 }
511
512 /* Preset control fields */
513 control = SPIC_SCGO | ((opcode_index & 0x07) << 4);
514
515 /* Issue atomic preop cycle if needed */
516 if (readw_(cntlr.preop))
517 control |= SPIC_ACS;
518
519 if (!trans.bytesout && !trans.bytesin) {
520 /* SPI addresses are 24 bit only */
521 if (with_address)
522 writel_(trans.offset & 0x00FFFFFF, cntlr.addr);
523
524 /*
525 * This is a 'no data' command (like Write Enable), its
Martin Roth99a3bba2014-12-07 14:57:26 -0700526 * bytesout size was 1, decremented to zero while executing
Aaron Durbin9a7d7bc2013-09-07 00:41:48 -0500527 * spi_setup_opcode() above. Tell the chip to send the
528 * command.
529 */
530 writew_(control, cntlr.control);
531
532 /* wait for the result */
533 status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1);
534 if (status == -1)
535 return -1;
536
537 if (status & SPIS_FCERR) {
538 printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n");
539 return -1;
540 }
541
542 return 0;
543 }
544
545 /*
Martin Roth99a3bba2014-12-07 14:57:26 -0700546 * Check if this is a write command attempting to transfer more bytes
Aaron Durbin9a7d7bc2013-09-07 00:41:48 -0500547 * than the controller can handle. Iterations for writes are not
548 * supported here because each SPI write command needs to be preceded
549 * and followed by other SPI commands, and this sequence is controlled
550 * by the SPI chip driver.
551 */
552 if (trans.bytesout > cntlr.databytes) {
553 printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use"
Kyösti Mälkki11104952014-06-29 16:17:33 +0300554 " spi_crop_chunk()?\n");
Aaron Durbin9a7d7bc2013-09-07 00:41:48 -0500555 return -1;
556 }
557
558 /*
559 * Read or write up to databytes bytes at a time until everything has
560 * been sent.
561 */
562 while (trans.bytesout || trans.bytesin) {
563 uint32_t data_length;
564
565 /* SPI addresses are 24 bit only */
566 writel_(trans.offset & 0x00FFFFFF, cntlr.addr);
567
568 if (trans.bytesout)
569 data_length = min(trans.bytesout, cntlr.databytes);
570 else
571 data_length = min(trans.bytesin, cntlr.databytes);
572
573 /* Program data into FDATA0 to N */
574 if (trans.bytesout) {
575 write_reg(trans.out, cntlr.data, data_length);
576 spi_use_out(&trans, data_length);
577 if (with_address)
578 trans.offset += data_length;
579 }
580
581 /* Add proper control fields' values */
582 control &= ~((cntlr.databytes - 1) << 8);
583 control |= SPIC_DS;
584 control |= (data_length - 1) << 8;
585
586 /* write it */
587 writew_(control, cntlr.control);
588
589 /* Wait for Cycle Done Status or Flash Cycle Error. */
590 status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1);
591 if (status == -1)
592 return -1;
593
594 if (status & SPIS_FCERR) {
595 printk(BIOS_DEBUG, "ICH SPI: Data transaction error\n");
596 return -1;
597 }
598
599 if (trans.bytesin) {
600 read_reg(cntlr.data, trans.in, data_length);
601 spi_use_in(&trans, data_length);
602 if (with_address)
603 trans.offset += data_length;
604 }
605 }
606
607 /* Clear atomic preop now that xfer is done */
608 writew_(0, cntlr.preop);
609
610 return 0;
611}
Furquan Shaikh94f86992016-12-01 07:12:32 -0800612
613static const struct spi_ctrlr spi_ctrlr = {
614 .xfer = spi_ctrlr_xfer,
Furquan Shaikhc2973d12016-11-29 22:07:42 -0800615 .xfer_vector = spi_xfer_two_vectors,
Furquan Shaikh94f86992016-12-01 07:12:32 -0800616};
617
618int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave)
619{
620 slave->bus = bus;
621 slave->cs = cs;
622 slave->ctrlr = &spi_ctrlr;
623 return 0;
624}