Patrick Georgi | 7333a11 | 2020-05-08 20:48:04 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 2 | |
| 3 | /* |
Zheng Bao | dd4c542 | 2021-10-14 16:14:09 +0800 | [diff] [blame] | 4 | * ROMSIG At ROMBASE + 0x[0,2,4,8]20000: |
zbao | c3b0b72 | 2016-02-19 13:47:31 +0800 | [diff] [blame] | 5 | * 0 4 8 C |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 6 | * +------------+---------------+----------------+------------+ |
| 7 | * | 0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM | |
| 8 | * +------------+---------------+----------------+------------+ |
Zheng Bao | dd4c542 | 2021-10-14 16:14:09 +0800 | [diff] [blame] | 9 | * | PSPDIR ADDR|PSPDIR ADDR(C) | BDT ADDR 0 | BDT ADDR 1 | |
| 10 | * +------------+---------------+----------------+------------+ |
| 11 | * | BDT ADDR 2 | | BDT ADDR 3(C) | | |
| 12 | * +------------+---------------+----------------+------------+ |
| 13 | * (C): Could be a combo header |
| 14 | * |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 15 | * EC ROM should be 64K aligned. |
| 16 | * |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 17 | * PSP directory (Where "PSPDIR ADDR" points) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 18 | * +------------+---------------+----------------+------------+ |
| 19 | * | 'PSP$' | Fletcher | Count | Reserved | |
| 20 | * +------------+---------------+----------------+------------+ |
| 21 | * | 0 | size | Base address | Reserved | Pubkey |
| 22 | * +------------+---------------+----------------+------------+ |
| 23 | * | 1 | size | Base address | Reserved | Bootloader |
| 24 | * +------------+---------------+----------------+------------+ |
| 25 | * | 8 | size | Base address | Reserved | Smu Firmware |
| 26 | * +------------+---------------+----------------+------------+ |
| 27 | * | 3 | size | Base address | Reserved | Recovery Firmware |
| 28 | * +------------+---------------+----------------+------------+ |
| 29 | * | | |
| 30 | * | | |
Zheng Bao | dd4c542 | 2021-10-14 16:14:09 +0800 | [diff] [blame] | 31 | * | Other PSP Firmware | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 32 | * | | |
| 33 | * +------------+---------------+----------------+------------+ |
Zheng Bao | dd4c542 | 2021-10-14 16:14:09 +0800 | [diff] [blame] | 34 | * | 40 | size | Base address | Reserved |---+ |
| 35 | * +------------+---------------+----------------+------------+ | |
| 36 | * :or 48(A/B A): size : Base address : Reserved : | |
| 37 | * + - - + - - + - - + - - + | |
| 38 | * : 4A(A/B B): size : Base address : Reserved : | |
| 39 | * +------------+---------------+----------------+------------+ | |
| 40 | * (A/B A) & (A/B B): Similar as 40, pointing to PSP level 2 | |
| 41 | * for A/B recovery | |
| 42 | * | |
| 43 | * | |
| 44 | * +------------+---------------+----------------+------------+ | |
| 45 | * | '2LP$' | Fletcher | Count | Reserved |<--+ |
| 46 | * +------------+---------------+----------------+------------+ |
| 47 | * | | |
| 48 | * | | |
| 49 | * | PSP Firmware | |
| 50 | * | (2nd-level is not required on all families) | |
| 51 | * | | |
| 52 | * +------------+---------------+----------------+------------+ |
| 53 | * BIOS Directory Table (BDT) is similar |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 54 | * |
zbao | c3b0b72 | 2016-02-19 13:47:31 +0800 | [diff] [blame] | 55 | * PSP Combo directory |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 56 | * +------------+---------------+----------------+------------+ |
zbao | 6e2f3d1 | 2016-02-19 13:34:59 +0800 | [diff] [blame] | 57 | * | 'PSP2' | Fletcher | Count |Look up mode| |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 58 | * +------------+---------------+----------------+------------+ |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 59 | * | R e s e r v e d | |
| 60 | * +------------+---------------+----------------+------------+ |
Zheng Bao | dd4c542 | 2021-10-14 16:14:09 +0800 | [diff] [blame] | 61 | * | ID-Sel | PSP ID | PSPDIR ADDR | | 1st PSP directory |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 62 | * +------------+---------------+----------------+------------+ |
Zheng Bao | dd4c542 | 2021-10-14 16:14:09 +0800 | [diff] [blame] | 63 | * | ID-Sel | PSP ID | PSPDIR ADDR | | 2nd PSP directory |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 64 | * +------------+---------------+----------------+------------+ |
| 65 | * | | |
| 66 | * | Other PSP | |
| 67 | * | | |
| 68 | * +------------+---------------+----------------+------------+ |
Zheng Bao | dd4c542 | 2021-10-14 16:14:09 +0800 | [diff] [blame] | 69 | * BDT Combo is similar |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 70 | */ |
| 71 | |
Elyes Haouas | 7d67a19 | 2022-10-14 09:58:29 +0200 | [diff] [blame] | 72 | #include <commonlib/bsd/helpers.h> |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 73 | #include <fcntl.h> |
| 74 | #include <errno.h> |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 75 | #include <limits.h> |
Martin Roth | 37305e7 | 2020-04-07 14:16:39 -0600 | [diff] [blame] | 76 | #include <stdbool.h> |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 77 | #include <stdio.h> |
| 78 | #include <sys/stat.h> |
| 79 | #include <sys/types.h> |
| 80 | #include <unistd.h> |
| 81 | #include <string.h> |
| 82 | #include <stdlib.h> |
| 83 | #include <getopt.h> |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 84 | #include <libgen.h> |
Idwer Vollering | 93df1d9 | 2020-12-30 00:01:59 +0100 | [diff] [blame] | 85 | #include <stdint.h> |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 86 | |
| 87 | #include "amdfwtool.h" |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 88 | |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 89 | #define AMD_ROMSIG_OFFSET 0x20000 |
| 90 | #define MIN_ROM_KB 256 |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 91 | |
Marshall Dawson | 7c1e142 | 2019-04-11 09:44:43 -0600 | [diff] [blame] | 92 | #define _MAX(A, B) (((A) > (B)) ? (A) : (B)) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 93 | |
Marshall Dawson | ef79fcc | 2019-04-01 10:16:41 -0600 | [diff] [blame] | 94 | #define DEFAULT_SOFT_FUSE_CHAIN "0x1" |
| 95 | |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 96 | #define EFS_FILE_SUFFIX ".efs" |
| 97 | #define TMP_FILE_SUFFIX ".tmp" |
Zheng Bao | 69ea83c | 2023-01-22 21:08:18 +0800 | [diff] [blame] | 98 | #define BODY_FILE_SUFFIX ".body" |
Kangheui Won | 5b84dfd | 2021-12-21 15:45:06 +1100 | [diff] [blame] | 99 | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 100 | /* |
Marshall Dawson | 0e02ce8 | 2019-03-04 16:50:37 -0700 | [diff] [blame] | 101 | * Beginning with Family 15h Models 70h-7F, a.k.a Stoney Ridge, the PSP |
| 102 | * can support an optional "combo" implementation. If the PSP sees the |
| 103 | * PSP2 cookie, it interprets the table as a roadmap to additional PSP |
| 104 | * tables. Using this, support for multiple product generations may be |
| 105 | * built into one image. If the PSP$ cookie is found, the table is a |
| 106 | * normal directory table. |
| 107 | * |
| 108 | * Modern generations supporting the combo directories require the |
| 109 | * pointer to be at offset 0x14 of the Embedded Firmware Structure, |
Zheng Bao | c91867a | 2023-02-26 12:31:31 +0800 | [diff] [blame] | 110 | * regardless of the type of directory used. The --use-combo |
Marshall Dawson | 0e02ce8 | 2019-03-04 16:50:37 -0700 | [diff] [blame] | 111 | * argument enforces this placement. |
| 112 | * |
| 113 | * TODO: Future work may require fully implementing the PSP_COMBO feature. |
zbao | c3b0b72 | 2016-02-19 13:47:31 +0800 | [diff] [blame] | 114 | */ |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 115 | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 116 | /* |
| 117 | * Creates the OSI Fletcher checksum. See 8473-1, Appendix C, section C.3. |
| 118 | * The checksum field of the passed PDU does not need to be reset to zero. |
| 119 | * |
| 120 | * The "Fletcher Checksum" was proposed in a paper by John G. Fletcher of |
| 121 | * Lawrence Livermore Labs. The Fletcher Checksum was proposed as an |
| 122 | * alternative to cyclical redundancy checks because it provides error- |
| 123 | * detection properties similar to cyclical redundancy checks but at the |
| 124 | * cost of a simple summation technique. Its characteristics were first |
| 125 | * published in IEEE Transactions on Communications in January 1982. One |
| 126 | * version has been adopted by ISO for use in the class-4 transport layer |
| 127 | * of the network protocol. |
| 128 | * |
| 129 | * This program expects: |
| 130 | * stdin: The input file to compute a checksum for. The input file |
| 131 | * not be longer than 256 bytes. |
| 132 | * stdout: Copied from the input file with the Fletcher's Checksum |
| 133 | * inserted 8 bytes after the beginning of the file. |
| 134 | * stderr: Used to print out error messages. |
| 135 | */ |
Marshall Dawson | 8a45a4d | 2019-02-24 07:18:44 -0700 | [diff] [blame] | 136 | static uint32_t fletcher32(const void *data, int length) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 137 | { |
| 138 | uint32_t c0; |
| 139 | uint32_t c1; |
| 140 | uint32_t checksum; |
| 141 | int index; |
Marshall Dawson | 8a45a4d | 2019-02-24 07:18:44 -0700 | [diff] [blame] | 142 | const uint16_t *pptr = data; |
| 143 | |
| 144 | length /= 2; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 145 | |
| 146 | c0 = 0xFFFF; |
| 147 | c1 = 0xFFFF; |
| 148 | |
Marshall Dawson | b85ddc5 | 2019-07-23 07:24:30 -0600 | [diff] [blame] | 149 | while (length) { |
| 150 | index = length >= 359 ? 359 : length; |
| 151 | length -= index; |
Zheng Bao | c88f2b5 | 2021-10-14 16:15:11 +0800 | [diff] [blame] | 152 | do { |
| 153 | c0 += *(pptr++); |
| 154 | c1 += c0; |
| 155 | } while (--index); |
Marshall Dawson | b85ddc5 | 2019-07-23 07:24:30 -0600 | [diff] [blame] | 156 | c0 = (c0 & 0xFFFF) + (c0 >> 16); |
| 157 | c1 = (c1 & 0xFFFF) + (c1 >> 16); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 158 | } |
| 159 | |
Marshall Dawson | 8a45a4d | 2019-02-24 07:18:44 -0700 | [diff] [blame] | 160 | /* Sums[0,1] mod 64K + overflow */ |
| 161 | c0 = (c0 & 0xFFFF) + (c0 >> 16); |
| 162 | c1 = (c1 & 0xFFFF) + (c1 >> 16); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 163 | checksum = (c1 << 16) | c0; |
| 164 | |
| 165 | return checksum; |
| 166 | } |
| 167 | |
Martin Roth | 8806f7f | 2016-11-08 10:44:18 -0700 | [diff] [blame] | 168 | static void usage(void) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 169 | { |
Martin Roth | 0e94062 | 2016-11-08 10:37:53 -0700 | [diff] [blame] | 170 | printf("amdfwtool: Create AMD Firmware combination\n"); |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 171 | printf("Usage: amdfwtool [options] --flashsize <size> --output <filename>\n"); |
| 172 | printf("--xhci <FILE> Add XHCI blob\n"); |
| 173 | printf("--imc <FILE> Add IMC blob\n"); |
| 174 | printf("--gec <FILE> Add GEC blob\n"); |
Martin Roth | 0e94062 | 2016-11-08 10:37:53 -0700 | [diff] [blame] | 175 | |
| 176 | printf("\nPSP options:\n"); |
Zheng Bao | 993b43f | 2021-11-10 12:21:46 +0800 | [diff] [blame] | 177 | printf("--use-combo Use the COMBO layout\n"); |
Zheng Bao | e3ebc4f | 2023-03-23 10:52:59 +0800 | [diff] [blame] | 178 | printf("--combo-config1 <config file> Config for 1st combo entry\n"); |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 179 | printf("--multilevel Generate primary and secondary tables\n"); |
| 180 | printf("--nvram <FILE> Add nvram binary\n"); |
| 181 | printf("--soft-fuse Set soft fuse\n"); |
| 182 | printf("--token-unlock Set token unlock\n"); |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 183 | printf("--nvram-base <HEX_VAL> Base address of nvram\n"); |
| 184 | printf("--nvram-size <HEX_VAL> Size of nvram\n"); |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 185 | printf("--whitelist Set if there is a whitelist\n"); |
| 186 | printf("--use-pspsecureos Set if psp secure OS is needed\n"); |
| 187 | printf("--load-mp2-fw Set if load MP2 firmware\n"); |
| 188 | printf("--load-s0i3 Set if load s0i3 firmware\n"); |
| 189 | printf("--verstage <FILE> Add verstage\n"); |
| 190 | printf("--verstage_sig Add verstage signature\n"); |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 191 | printf("--recovery-ab Use the recovery A/B layout\n"); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 192 | printf("\nBIOS options:\n"); |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 193 | printf("--instance <number> Sets instance field for the next BIOS\n"); |
Zheng Bao | 6f0b361 | 2021-04-27 17:19:43 +0800 | [diff] [blame] | 194 | printf(" firmware\n"); |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 195 | printf("--apcb <FILE> Add AGESA PSP customization block\n"); |
| 196 | printf("--apob-base <HEX_VAL> Destination for AGESA PSP output block\n"); |
| 197 | printf("--apob-nv-base <HEX_VAL> Location of S3 resume data\n"); |
| 198 | printf("--apob-nv-size <HEX_VAL> Size of S3 resume data\n"); |
| 199 | printf("--ucode <FILE> Add microcode patch\n"); |
| 200 | printf("--bios-bin <FILE> Add compressed image; auto source address\n"); |
| 201 | printf("--bios-bin-src <HEX_VAL> Address in flash of source if -V not used\n"); |
| 202 | printf("--bios-bin-dest <HEX_VAL> Destination for uncompressed BIOS\n"); |
| 203 | printf("--bios-uncomp-size <HEX> Uncompressed size of BIOS image\n"); |
| 204 | printf("--output <filename> output filename\n"); |
| 205 | printf("--flashsize <HEX_VAL> ROM size in bytes\n"); |
Marshall Dawson | f4b9b41 | 2017-03-17 16:30:51 -0600 | [diff] [blame] | 206 | printf(" size must be larger than %dKB\n", |
Martin Roth | 0e94062 | 2016-11-08 10:37:53 -0700 | [diff] [blame] | 207 | MIN_ROM_KB); |
Marshall Dawson | f4b9b41 | 2017-03-17 16:30:51 -0600 | [diff] [blame] | 208 | printf(" and must a multiple of 1024\n"); |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 209 | printf("--location Location of Directory\n"); |
| 210 | printf("--anywhere Use any 64-byte aligned addr for Directory\n"); |
| 211 | printf("--sharedmem Location of PSP/FW shared memory\n"); |
| 212 | printf("--sharedmem-size Maximum size of the PSP/FW shared memory\n"); |
Zheng Bao | 6f0b361 | 2021-04-27 17:19:43 +0800 | [diff] [blame] | 213 | printf(" area\n"); |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 214 | printf("\nEmbedded Firmware Structure options used by the PSP:\n"); |
| 215 | printf("--spi-speed <HEX_VAL> SPI fast speed to place in EFS Table\n"); |
| 216 | printf(" 0x0 66.66Mhz\n"); |
| 217 | printf(" 0x1 33.33MHz\n"); |
| 218 | printf(" 0x2 22.22MHz\n"); |
| 219 | printf(" 0x3 16.66MHz\n"); |
| 220 | printf(" 0x4 100MHz\n"); |
| 221 | printf(" 0x5 800KHz\n"); |
| 222 | printf("--spi-read-mode <HEX_VAL> SPI read mode to place in EFS Table\n"); |
| 223 | printf(" 0x0 Normal Read (up to 33M)\n"); |
| 224 | printf(" 0x1 Reserved\n"); |
| 225 | printf(" 0x2 Dual IO (1-1-2)\n"); |
| 226 | printf(" 0x3 Quad IO (1-1-4)\n"); |
| 227 | printf(" 0x4 Dual IO (1-2-2)\n"); |
| 228 | printf(" 0x5 Quad IO (1-4-4)\n"); |
| 229 | printf(" 0x6 Normal Read (up to 66M)\n"); |
| 230 | printf(" 0x7 Fast Read\n"); |
| 231 | printf("--spi-micron-flag <HEX_VAL> Micron SPI part support for RV and later SOC\n"); |
| 232 | printf(" 0x0 Micron parts are not used\n"); |
| 233 | printf(" 0x1 Micron parts are always used\n"); |
| 234 | printf(" 0x2 Micron parts optional, this option is only\n"); |
| 235 | printf(" supported with RN/LCN SOC\n"); |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 236 | printf("\nGeneral options:\n"); |
| 237 | printf("-c|--config <config file> Config file\n"); |
| 238 | printf("-d|--debug Print debug message\n"); |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 239 | printf("-h|--help Show this help\n"); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 240 | } |
| 241 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 242 | amd_fw_entry amd_psp_fw_table[] = { |
Kangheui Won | 3c164e1 | 2021-12-03 20:25:05 +1100 | [diff] [blame] | 243 | { .type = AMD_FW_PSP_PUBKEY, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true }, |
Zheng Bao | fb9b784 | 2022-02-24 15:15:50 +0800 | [diff] [blame] | 244 | { .type = AMD_FW_PSP_BOOTLOADER, .level = PSP_BOTH | PSP_LVL2_AB }, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 245 | { .type = AMD_FW_PSP_SECURED_OS, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Arthur Heymans | aafbe13 | 2022-09-30 08:33:28 +0200 | [diff] [blame] | 246 | { .type = AMD_FW_PSP_RECOVERY, .level = PSP_LVL1 }, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 247 | { .type = AMD_FW_PSP_NVRAM, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Arthur Heymans | aafbe13 | 2022-09-30 08:33:28 +0200 | [diff] [blame] | 248 | { .type = AMD_FW_PSP_RTM_PUBKEY, .level = PSP_BOTH }, |
| 249 | { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 250 | { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 251 | { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 2, .level = PSP_BOTH | PSP_LVL2_AB }, |
Kangheui Won | 3c164e1 | 2021-12-03 20:25:05 +1100 | [diff] [blame] | 252 | { .type = AMD_FW_PSP_SECURED_DEBUG, .level = PSP_LVL2 | PSP_LVL2_AB, |
| 253 | .skip_hashing = true }, |
Arthur Heymans | 1f05c80 | 2022-10-04 17:50:21 +0200 | [diff] [blame] | 254 | { .type = AMD_FW_ABL_PUBKEY, .level = PSP_BOTH | PSP_BOTH_AB }, |
Arthur Heymans | aafbe13 | 2022-09-30 08:33:28 +0200 | [diff] [blame] | 255 | { .type = AMD_PSP_FUSE_CHAIN, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 256 | { .type = AMD_FW_PSP_TRUSTLETS, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 257 | { .type = AMD_FW_PSP_TRUSTLETKEY, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 258 | { .type = AMD_FW_PSP_SMU_FIRMWARE2, .level = PSP_BOTH | PSP_LVL2_AB }, |
Arthur Heymans | aafbe13 | 2022-09-30 08:33:28 +0200 | [diff] [blame] | 259 | { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 260 | { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 2, .level = PSP_BOTH | PSP_LVL2_AB }, |
Zheng Bao | 8eba662 | 2022-10-16 20:29:03 +0800 | [diff] [blame] | 261 | { .type = AMD_BOOT_DRIVER, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 262 | { .type = AMD_SOC_DRIVER, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 263 | { .type = AMD_DEBUG_DRIVER, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 264 | { .type = AMD_INTERFACE_DRIVER, .level = PSP_BOTH | PSP_LVL2_AB }, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 265 | { .type = AMD_DEBUG_UNLOCK, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Zheng Bao | 9bb62cb | 2023-03-07 19:48:11 +0800 | [diff] [blame] | 266 | { .type = AMD_HW_IPCFG, .subprog = 0, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 267 | { .type = AMD_HW_IPCFG, .subprog = 1, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Kangheui Won | 3c164e1 | 2021-12-03 20:25:05 +1100 | [diff] [blame] | 268 | { .type = AMD_WRAPPED_IKEK, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true }, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 269 | { .type = AMD_TOKEN_UNLOCK, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 270 | { .type = AMD_SEC_GASKET, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB }, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 271 | { .type = AMD_SEC_GASKET, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, |
Arthur Heymans | aafbe13 | 2022-09-30 08:33:28 +0200 | [diff] [blame] | 272 | { .type = AMD_SEC_GASKET, .subprog = 2, .level = PSP_BOTH | PSP_LVL2_AB }, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 273 | { .type = AMD_MP2_FW, .subprog = 0, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Arthur Heymans | aafbe13 | 2022-09-30 08:33:28 +0200 | [diff] [blame] | 274 | { .type = AMD_MP2_FW, .subprog = 1, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 275 | { .type = AMD_MP2_FW, .subprog = 2, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 276 | { .type = AMD_DRIVER_ENTRIES, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 277 | { .type = AMD_FW_KVM_IMAGE, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Arthur Heymans | 1f05c80 | 2022-10-04 17:50:21 +0200 | [diff] [blame] | 278 | { .type = AMD_FW_MP5, .subprog = 0, .level = PSP_BOTH | PSP_BOTH_AB }, |
| 279 | { .type = AMD_FW_MP5, .subprog = 1, .level = PSP_BOTH | PSP_BOTH_AB }, |
| 280 | { .type = AMD_FW_MP5, .subprog = 2, .level = PSP_BOTH | PSP_BOTH_AB }, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 281 | { .type = AMD_S0I3_DRIVER, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 282 | { .type = AMD_ABL0, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 283 | { .type = AMD_ABL1, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 284 | { .type = AMD_ABL2, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 285 | { .type = AMD_ABL3, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 286 | { .type = AMD_ABL4, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 287 | { .type = AMD_ABL5, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 288 | { .type = AMD_ABL6, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 289 | { .type = AMD_ABL7, .level = PSP_BOTH | PSP_LVL2_AB }, |
Arthur Heymans | 1f05c80 | 2022-10-04 17:50:21 +0200 | [diff] [blame] | 290 | { .type = AMD_SEV_DATA, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 291 | { .type = AMD_SEV_CODE, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Karthikeyan Ramasubramanian | 51f914d | 2022-07-28 16:42:12 -0600 | [diff] [blame] | 292 | { .type = AMD_FW_PSP_WHITELIST, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Arthur Heymans | aafbe13 | 2022-09-30 08:33:28 +0200 | [diff] [blame] | 293 | { .type = AMD_VBIOS_BTLOADER, .level = PSP_BOTH | PSP_LVL2_AB }, |
Arthur Heymans | 1f05c80 | 2022-10-04 17:50:21 +0200 | [diff] [blame] | 294 | { .type = AMD_FW_DXIO, .level = PSP_BOTH | PSP_BOTH_AB }, |
Arthur Heymans | aafbe13 | 2022-09-30 08:33:28 +0200 | [diff] [blame] | 295 | { .type = AMD_FW_USB_PHY, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 296 | { .type = AMD_FW_TOS_SEC_POLICY, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 297 | { .type = AMD_FW_DRTM_TA, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 298 | { .type = AMD_FW_KEYDB_BL, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 299 | { .type = AMD_FW_KEYDB_TOS, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Karthikeyan Ramasubramanian | 234e370 | 2022-07-25 09:49:24 -0600 | [diff] [blame] | 300 | { .type = AMD_FW_PSP_VERSTAGE, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 301 | { .type = AMD_FW_VERSTAGE_SIG, .level = PSP_BOTH | PSP_LVL2_AB }, |
Arthur Heymans | aafbe13 | 2022-09-30 08:33:28 +0200 | [diff] [blame] | 302 | { .type = AMD_RPMC_NVRAM, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 303 | { .type = AMD_FW_SPL, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 304 | { .type = AMD_FW_DMCU_ERAM, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 305 | { .type = AMD_FW_DMCU_ISR, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 306 | { .type = AMD_FW_MSMU, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 307 | { .type = AMD_FW_SPIROM_CFG, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Nikolai Vyssotski | bfc9ca7 | 2023-03-07 15:09:09 -0600 | [diff] [blame] | 308 | { .type = AMD_FW_MPIO, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Zheng Bao | 8eba662 | 2022-10-16 20:29:03 +0800 | [diff] [blame] | 309 | { .type = AMD_FW_PSP_SMUSCS, .level = PSP_BOTH | PSP_LVL2_AB }, |
Arthur Heymans | aafbe13 | 2022-09-30 08:33:28 +0200 | [diff] [blame] | 310 | { .type = AMD_FW_DMCUB, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 311 | { .type = AMD_FW_PSP_BOOTLOADER_AB, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Zheng Bao | 85ee1fd | 2023-01-30 13:52:30 +0800 | [diff] [blame] | 312 | { .type = AMD_RIB, .subprog = 0, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 313 | { .type = AMD_RIB, .subprog = 1, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Arthur Heymans | 1f05c80 | 2022-10-04 17:50:21 +0200 | [diff] [blame] | 314 | { .type = AMD_FW_MPDMA_TF, .level = PSP_BOTH | PSP_BOTH_AB }, |
Arthur Heymans | aafbe13 | 2022-09-30 08:33:28 +0200 | [diff] [blame] | 315 | { .type = AMD_TA_IKEK, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true }, |
Arthur Heymans | 1f05c80 | 2022-10-04 17:50:21 +0200 | [diff] [blame] | 316 | { .type = AMD_FW_GMI3_PHY, .level = PSP_BOTH | PSP_BOTH_AB }, |
| 317 | { .type = AMD_FW_MPDMA_PM, .level = PSP_BOTH | PSP_BOTH_AB }, |
Zheng Bao | 8eba662 | 2022-10-16 20:29:03 +0800 | [diff] [blame] | 318 | { .type = AMD_FW_AMF_SRAM, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 319 | { .type = AMD_FW_AMF_DRAM, .inst = 0, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 320 | { .type = AMD_FW_AMF_DRAM, .inst = 1, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 321 | { .type = AMD_FW_FCFG_TABLE, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 322 | { .type = AMD_FW_AMF_WLAN, .inst = 0, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 323 | { .type = AMD_FW_AMF_WLAN, .inst = 1, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 324 | { .type = AMD_FW_AMF_MFD, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 325 | { .type = AMD_TA_IKEK, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true }, |
| 326 | { .type = AMD_FW_MPCCX, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 327 | { .type = AMD_FW_LSDMA, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 328 | { .type = AMD_FW_C20_MP, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 329 | { .type = AMD_FW_MINIMSMU, .inst = 0, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 330 | { .type = AMD_FW_MINIMSMU, .inst = 1, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 331 | { .type = AMD_FW_SRAM_FW_EXT, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Fred Reitberger | c4f3a33 | 2023-02-07 12:12:40 -0500 | [diff] [blame] | 332 | { .type = AMD_FW_UMSMU, .level = PSP_LVL2 | PSP_LVL2_AB }, |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 333 | { .type = AMD_FW_INVALID }, |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 334 | }; |
| 335 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 336 | amd_fw_entry amd_fw_table[] = { |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 337 | { .type = AMD_FW_XHCI }, |
| 338 | { .type = AMD_FW_IMC }, |
| 339 | { .type = AMD_FW_GEC }, |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 340 | { .type = AMD_FW_INVALID }, |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 341 | }; |
| 342 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 343 | amd_bios_entry amd_bios_table[] = { |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 344 | { .type = AMD_BIOS_RTM_PUBKEY, .inst = 0, .level = BDT_BOTH }, |
Ritul Guru | 9a321f3 | 2022-07-29 11:06:40 +0530 | [diff] [blame] | 345 | { .type = AMD_BIOS_SIG, .inst = 0, .level = BDT_BOTH }, |
Marshall Dawson | 0581bf6 | 2019-09-25 11:03:53 -0600 | [diff] [blame] | 346 | { .type = AMD_BIOS_APCB, .inst = 0, .level = BDT_BOTH }, |
| 347 | { .type = AMD_BIOS_APCB, .inst = 1, .level = BDT_BOTH }, |
| 348 | { .type = AMD_BIOS_APCB, .inst = 2, .level = BDT_BOTH }, |
| 349 | { .type = AMD_BIOS_APCB, .inst = 3, .level = BDT_BOTH }, |
| 350 | { .type = AMD_BIOS_APCB, .inst = 4, .level = BDT_BOTH }, |
Rob Barnes | 18fd26c | 2020-03-03 10:35:02 -0700 | [diff] [blame] | 351 | { .type = AMD_BIOS_APCB, .inst = 5, .level = BDT_BOTH }, |
| 352 | { .type = AMD_BIOS_APCB, .inst = 6, .level = BDT_BOTH }, |
| 353 | { .type = AMD_BIOS_APCB, .inst = 7, .level = BDT_BOTH }, |
| 354 | { .type = AMD_BIOS_APCB, .inst = 8, .level = BDT_BOTH }, |
| 355 | { .type = AMD_BIOS_APCB, .inst = 9, .level = BDT_BOTH }, |
| 356 | { .type = AMD_BIOS_APCB, .inst = 10, .level = BDT_BOTH }, |
| 357 | { .type = AMD_BIOS_APCB, .inst = 11, .level = BDT_BOTH }, |
| 358 | { .type = AMD_BIOS_APCB, .inst = 12, .level = BDT_BOTH }, |
| 359 | { .type = AMD_BIOS_APCB, .inst = 13, .level = BDT_BOTH }, |
| 360 | { .type = AMD_BIOS_APCB, .inst = 14, .level = BDT_BOTH }, |
| 361 | { .type = AMD_BIOS_APCB, .inst = 15, .level = BDT_BOTH }, |
Marshall Dawson | 2dd3b5c | 2020-01-03 17:57:48 -0700 | [diff] [blame] | 362 | { .type = AMD_BIOS_APCB_BK, .inst = 0, .level = BDT_BOTH }, |
| 363 | { .type = AMD_BIOS_APCB_BK, .inst = 1, .level = BDT_BOTH }, |
| 364 | { .type = AMD_BIOS_APCB_BK, .inst = 2, .level = BDT_BOTH }, |
| 365 | { .type = AMD_BIOS_APCB_BK, .inst = 3, .level = BDT_BOTH }, |
| 366 | { .type = AMD_BIOS_APCB_BK, .inst = 4, .level = BDT_BOTH }, |
Rob Barnes | 18fd26c | 2020-03-03 10:35:02 -0700 | [diff] [blame] | 367 | { .type = AMD_BIOS_APCB_BK, .inst = 5, .level = BDT_BOTH }, |
| 368 | { .type = AMD_BIOS_APCB_BK, .inst = 6, .level = BDT_BOTH }, |
| 369 | { .type = AMD_BIOS_APCB_BK, .inst = 7, .level = BDT_BOTH }, |
| 370 | { .type = AMD_BIOS_APCB_BK, .inst = 8, .level = BDT_BOTH }, |
| 371 | { .type = AMD_BIOS_APCB_BK, .inst = 9, .level = BDT_BOTH }, |
| 372 | { .type = AMD_BIOS_APCB_BK, .inst = 10, .level = BDT_BOTH }, |
| 373 | { .type = AMD_BIOS_APCB_BK, .inst = 11, .level = BDT_BOTH }, |
| 374 | { .type = AMD_BIOS_APCB_BK, .inst = 12, .level = BDT_BOTH }, |
| 375 | { .type = AMD_BIOS_APCB_BK, .inst = 13, .level = BDT_BOTH }, |
| 376 | { .type = AMD_BIOS_APCB_BK, .inst = 14, .level = BDT_BOTH }, |
| 377 | { .type = AMD_BIOS_APCB_BK, .inst = 15, .level = BDT_BOTH }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 378 | { .type = AMD_BIOS_APOB, .level = BDT_BOTH }, |
| 379 | { .type = AMD_BIOS_BIN, |
Zheng Bao | 3d426f3 | 2022-10-16 20:34:57 +0800 | [diff] [blame] | 380 | .reset = 1, .copy = 1, .zlib = 1, .inst = 0, .level = BDT_BOTH }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 381 | { .type = AMD_BIOS_APOB_NV, .level = BDT_LVL2 }, |
| 382 | { .type = AMD_BIOS_PMUI, .inst = 1, .subpr = 0, .level = BDT_BOTH }, |
| 383 | { .type = AMD_BIOS_PMUD, .inst = 1, .subpr = 0, .level = BDT_BOTH }, |
Zheng Bao | e220faa | 2022-02-17 17:22:15 +0800 | [diff] [blame] | 384 | { .type = AMD_BIOS_PMUI, .inst = 2, .subpr = 0, .level = BDT_BOTH }, |
| 385 | { .type = AMD_BIOS_PMUD, .inst = 2, .subpr = 0, .level = BDT_BOTH }, |
Arthur Heymans | a83c502 | 2022-10-04 20:37:10 +0200 | [diff] [blame] | 386 | { .type = AMD_BIOS_PMUI, .inst = 3, .subpr = 0, .level = BDT_BOTH }, |
| 387 | { .type = AMD_BIOS_PMUD, .inst = 3, .subpr = 0, .level = BDT_BOTH }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 388 | { .type = AMD_BIOS_PMUI, .inst = 4, .subpr = 0, .level = BDT_BOTH }, |
| 389 | { .type = AMD_BIOS_PMUD, .inst = 4, .subpr = 0, .level = BDT_BOTH }, |
Zheng Bao | 8eba662 | 2022-10-16 20:29:03 +0800 | [diff] [blame] | 390 | { .type = AMD_BIOS_PMUI, .inst = 5, .subpr = 0, .level = BDT_BOTH }, |
| 391 | { .type = AMD_BIOS_PMUD, .inst = 5, .subpr = 0, .level = BDT_BOTH }, |
| 392 | { .type = AMD_BIOS_PMUI, .inst = 6, .subpr = 0, .level = BDT_BOTH }, |
| 393 | { .type = AMD_BIOS_PMUD, .inst = 6, .subpr = 0, .level = BDT_BOTH }, |
| 394 | { .type = AMD_BIOS_PMUI, .inst = 7, .subpr = 0, .level = BDT_BOTH }, |
| 395 | { .type = AMD_BIOS_PMUD, .inst = 7, .subpr = 0, .level = BDT_BOTH }, |
Arthur Heymans | a83c502 | 2022-10-04 20:37:10 +0200 | [diff] [blame] | 396 | { .type = AMD_BIOS_PMUI, .inst = 9, .subpr = 0, .level = BDT_BOTH }, |
| 397 | { .type = AMD_BIOS_PMUD, .inst = 9, .subpr = 0, .level = BDT_BOTH }, |
| 398 | { .type = AMD_BIOS_PMUI, .inst = 10, .subpr = 0, .level = BDT_BOTH }, |
| 399 | { .type = AMD_BIOS_PMUD, .inst = 10, .subpr = 0, .level = BDT_BOTH }, |
Zheng Bao | 8eba662 | 2022-10-16 20:29:03 +0800 | [diff] [blame] | 400 | { .type = AMD_BIOS_PMUI, .inst = 11, .subpr = 0, .level = BDT_BOTH }, |
| 401 | { .type = AMD_BIOS_PMUD, .inst = 11, .subpr = 0, .level = BDT_BOTH }, |
| 402 | { .type = AMD_BIOS_PMUI, .inst = 12, .subpr = 0, .level = BDT_BOTH }, |
| 403 | { .type = AMD_BIOS_PMUD, .inst = 12, .subpr = 0, .level = BDT_BOTH }, |
| 404 | { .type = AMD_BIOS_PMUI, .inst = 13, .subpr = 0, .level = BDT_BOTH }, |
| 405 | { .type = AMD_BIOS_PMUD, .inst = 13, .subpr = 0, .level = BDT_BOTH }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 406 | { .type = AMD_BIOS_PMUI, .inst = 1, .subpr = 1, .level = BDT_BOTH }, |
| 407 | { .type = AMD_BIOS_PMUD, .inst = 1, .subpr = 1, .level = BDT_BOTH }, |
Zheng Bao | e220faa | 2022-02-17 17:22:15 +0800 | [diff] [blame] | 408 | { .type = AMD_BIOS_PMUI, .inst = 2, .subpr = 1, .level = BDT_BOTH }, |
| 409 | { .type = AMD_BIOS_PMUD, .inst = 2, .subpr = 1, .level = BDT_BOTH }, |
Arthur Heymans | a83c502 | 2022-10-04 20:37:10 +0200 | [diff] [blame] | 410 | { .type = AMD_BIOS_PMUI, .inst = 3, .subpr = 1, .level = BDT_BOTH }, |
| 411 | { .type = AMD_BIOS_PMUD, .inst = 3, .subpr = 1, .level = BDT_BOTH }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 412 | { .type = AMD_BIOS_PMUI, .inst = 4, .subpr = 1, .level = BDT_BOTH }, |
| 413 | { .type = AMD_BIOS_PMUD, .inst = 4, .subpr = 1, .level = BDT_BOTH }, |
Zheng Bao | 8eba662 | 2022-10-16 20:29:03 +0800 | [diff] [blame] | 414 | { .type = AMD_BIOS_PMUI, .inst = 5, .subpr = 1, .level = BDT_BOTH }, |
| 415 | { .type = AMD_BIOS_PMUD, .inst = 5, .subpr = 1, .level = BDT_BOTH }, |
| 416 | { .type = AMD_BIOS_PMUI, .inst = 6, .subpr = 1, .level = BDT_BOTH }, |
| 417 | { .type = AMD_BIOS_PMUD, .inst = 6, .subpr = 1, .level = BDT_BOTH }, |
| 418 | { .type = AMD_BIOS_PMUI, .inst = 7, .subpr = 1, .level = BDT_BOTH }, |
| 419 | { .type = AMD_BIOS_PMUD, .inst = 7, .subpr = 1, .level = BDT_BOTH }, |
Arthur Heymans | a83c502 | 2022-10-04 20:37:10 +0200 | [diff] [blame] | 420 | { .type = AMD_BIOS_PMUI, .inst = 9, .subpr = 1, .level = BDT_BOTH }, |
| 421 | { .type = AMD_BIOS_PMUD, .inst = 9, .subpr = 1, .level = BDT_BOTH }, |
| 422 | { .type = AMD_BIOS_PMUI, .inst = 10, .subpr = 1, .level = BDT_BOTH }, |
| 423 | { .type = AMD_BIOS_PMUD, .inst = 10, .subpr = 1, .level = BDT_BOTH }, |
Zheng Bao | 8eba662 | 2022-10-16 20:29:03 +0800 | [diff] [blame] | 424 | { .type = AMD_BIOS_PMUI, .inst = 11, .subpr = 1, .level = BDT_BOTH }, |
| 425 | { .type = AMD_BIOS_PMUD, .inst = 11, .subpr = 1, .level = BDT_BOTH }, |
| 426 | { .type = AMD_BIOS_PMUI, .inst = 12, .subpr = 1, .level = BDT_BOTH }, |
| 427 | { .type = AMD_BIOS_PMUD, .inst = 12, .subpr = 1, .level = BDT_BOTH }, |
| 428 | { .type = AMD_BIOS_PMUI, .inst = 13, .subpr = 1, .level = BDT_BOTH }, |
| 429 | { .type = AMD_BIOS_PMUD, .inst = 13, .subpr = 1, .level = BDT_BOTH }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 430 | { .type = AMD_BIOS_UCODE, .inst = 0, .level = BDT_LVL2 }, |
| 431 | { .type = AMD_BIOS_UCODE, .inst = 1, .level = BDT_LVL2 }, |
| 432 | { .type = AMD_BIOS_UCODE, .inst = 2, .level = BDT_LVL2 }, |
Arthur Heymans | a83c502 | 2022-10-04 20:37:10 +0200 | [diff] [blame] | 433 | { .type = AMD_BIOS_UCODE, .inst = 3, .level = BDT_LVL2 }, |
| 434 | { .type = AMD_BIOS_UCODE, .inst = 4, .level = BDT_LVL2 }, |
| 435 | { .type = AMD_BIOS_UCODE, .inst = 5, .level = BDT_LVL2 }, |
| 436 | { .type = AMD_BIOS_UCODE, .inst = 6, .level = BDT_LVL2 }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 437 | { .type = AMD_BIOS_MP2_CFG, .level = BDT_LVL2 }, |
Martin Roth | 9455474 | 2020-04-14 14:59:36 -0600 | [diff] [blame] | 438 | { .type = AMD_BIOS_PSP_SHARED_MEM, .inst = 0, .level = BDT_BOTH }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 439 | { .type = AMD_BIOS_INVALID }, |
| 440 | }; |
| 441 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 442 | typedef struct _context { |
| 443 | char *rom; /* target buffer, size of flash device */ |
| 444 | uint32_t rom_size; /* size of flash device */ |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 445 | uint32_t address_mode; /* 0:abs address; 1:relative to flash; 2: relative to table */ |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 446 | uint32_t current; /* pointer within flash & proxy buffer */ |
Zheng Bao | c26108f | 2023-02-17 11:01:07 +0800 | [diff] [blame] | 447 | uint32_t current_pointer_saved; |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 448 | uint32_t current_table; |
Zheng Bao | 8dd34bd | 2023-03-09 21:09:58 +0800 | [diff] [blame] | 449 | void *amd_psp_fw_table_clean; |
| 450 | void *amd_bios_table_clean; |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 451 | } context; |
| 452 | |
| 453 | #define RUN_BASE(ctx) (0xFFFFFFFF - (ctx).rom_size + 1) |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 454 | #define RUN_OFFSET_MODE(ctx, offset, mode) \ |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 455 | ((mode) == AMD_ADDR_PHYSICAL ? RUN_BASE(ctx) + (offset) : \ |
| 456 | ((mode) == AMD_ADDR_REL_BIOS ? (offset) : \ |
Zheng Bao | c38f764 | 2023-02-21 10:43:08 +0800 | [diff] [blame] | 457 | ((mode) == AMD_ADDR_REL_TAB ? (offset) - (ctx).current_table : (offset)))) |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 458 | #define RUN_OFFSET(ctx, offset) RUN_OFFSET_MODE((ctx), (offset), (ctx).address_mode) |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 459 | #define RUN_TO_OFFSET(ctx, run) ((ctx).address_mode == AMD_ADDR_PHYSICAL ? \ |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 460 | (run) - RUN_BASE(ctx) : (run)) /* TODO: */ |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 461 | #define RUN_CURRENT(ctx) RUN_OFFSET((ctx), (ctx).current) |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 462 | /* The mode in entry can not be higher than the header's. |
| 463 | For example, if table mode is 0, all the entry mode will be 0. */ |
| 464 | #define RUN_CURRENT_MODE(ctx, mode) RUN_OFFSET_MODE((ctx), (ctx).current, \ |
| 465 | (ctx).address_mode < (mode) ? (ctx).address_mode : (mode)) |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 466 | #define BUFF_OFFSET(ctx, offset) ((void *)((ctx).rom + (offset))) |
| 467 | #define BUFF_CURRENT(ctx) BUFF_OFFSET((ctx), (ctx).current) |
| 468 | #define BUFF_TO_RUN(ctx, ptr) RUN_OFFSET((ctx), ((char *)(ptr) - (ctx).rom)) |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 469 | #define BUFF_TO_RUN_MODE(ctx, ptr, mode) RUN_OFFSET_MODE((ctx), ((char *)(ptr) - (ctx).rom), \ |
| 470 | (ctx).address_mode < (mode) ? (ctx).address_mode : (mode)) |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 471 | #define BUFF_ROOM(ctx) ((ctx).rom_size - (ctx).current) |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 472 | /* Only set the address mode in entry if the table is mode 2. */ |
| 473 | #define SET_ADDR_MODE(table, mode) \ |
| 474 | ((table)->header.additional_info_fields.address_mode == \ |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 475 | AMD_ADDR_REL_TAB ? (mode) : 0) |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 476 | #define SET_ADDR_MODE_BY_TABLE(table) \ |
| 477 | SET_ADDR_MODE((table), (table)->header.additional_info_fields.address_mode) |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 478 | |
Zheng Bao | 7c5ad88 | 2023-02-19 13:02:52 +0800 | [diff] [blame] | 479 | |
| 480 | static void free_psp_firmware_filenames(amd_fw_entry *fw_table) |
| 481 | { |
| 482 | amd_fw_entry *index; |
| 483 | |
| 484 | for (index = fw_table; index->type != AMD_FW_INVALID; index++) { |
| 485 | if (index->filename && |
| 486 | index->type != AMD_FW_VERSTAGE_SIG && |
| 487 | index->type != AMD_FW_PSP_VERSTAGE && |
| 488 | index->type != AMD_FW_SPL && |
| 489 | index->type != AMD_FW_PSP_WHITELIST) { |
| 490 | free(index->filename); |
| 491 | index->filename = NULL; |
| 492 | } |
| 493 | } |
| 494 | } |
| 495 | |
| 496 | static void free_bdt_firmware_filenames(amd_bios_entry *fw_table) |
| 497 | { |
| 498 | amd_bios_entry *index; |
| 499 | |
| 500 | for (index = fw_table; index->type != AMD_BIOS_INVALID; index++) { |
| 501 | if (index->filename && |
| 502 | index->type != AMD_BIOS_APCB && |
| 503 | index->type != AMD_BIOS_BIN && |
| 504 | index->type != AMD_BIOS_APCB_BK && |
| 505 | index->type != AMD_BIOS_UCODE) { |
| 506 | free(index->filename); |
| 507 | index->filename = NULL; |
| 508 | } |
| 509 | } |
| 510 | } |
| 511 | |
| 512 | static void amdfwtool_cleanup(context *ctx) |
| 513 | { |
| 514 | free(ctx->rom); |
| 515 | ctx->rom = NULL; |
| 516 | |
| 517 | /* Free the filename. */ |
| 518 | free_psp_firmware_filenames(amd_psp_fw_table); |
| 519 | free_bdt_firmware_filenames(amd_bios_table); |
Zheng Bao | 8dd34bd | 2023-03-09 21:09:58 +0800 | [diff] [blame] | 520 | |
| 521 | free(ctx->amd_psp_fw_table_clean); |
| 522 | ctx->amd_psp_fw_table_clean = NULL; |
| 523 | free(ctx->amd_bios_table_clean); |
| 524 | ctx->amd_bios_table_clean = NULL; |
Zheng Bao | 7c5ad88 | 2023-02-19 13:02:52 +0800 | [diff] [blame] | 525 | } |
| 526 | |
Zheng Bao | 5164e4b | 2021-10-30 12:09:07 +0800 | [diff] [blame] | 527 | void assert_fw_entry(uint32_t count, uint32_t max, context *ctx) |
| 528 | { |
| 529 | if (count >= max) { |
| 530 | fprintf(stderr, "Error: BIOS entries (%d) exceeds max allowed items " |
| 531 | "(%d)\n", count, max); |
Zheng Bao | 7c5ad88 | 2023-02-19 13:02:52 +0800 | [diff] [blame] | 532 | amdfwtool_cleanup(ctx); |
Zheng Bao | 5164e4b | 2021-10-30 12:09:07 +0800 | [diff] [blame] | 533 | exit(1); |
| 534 | } |
| 535 | } |
| 536 | |
Zheng Bao | c26108f | 2023-02-17 11:01:07 +0800 | [diff] [blame] | 537 | static void set_current_pointer(context *ctx, uint32_t value) |
| 538 | { |
| 539 | if (ctx->current_pointer_saved != 0xFFFFFFFF && |
| 540 | ctx->current_pointer_saved != ctx->current) { |
| 541 | fprintf(stderr, "Error: The pointer is changed elsewhere\n"); |
Zheng Bao | 7c5ad88 | 2023-02-19 13:02:52 +0800 | [diff] [blame] | 542 | amdfwtool_cleanup(ctx); |
Zheng Bao | c26108f | 2023-02-17 11:01:07 +0800 | [diff] [blame] | 543 | exit(1); |
| 544 | } |
| 545 | |
| 546 | ctx->current = value; |
| 547 | |
| 548 | if (ctx->current > ctx->rom_size) { |
| 549 | fprintf(stderr, "Error: Packing data causes overflow\n"); |
Zheng Bao | 7c5ad88 | 2023-02-19 13:02:52 +0800 | [diff] [blame] | 550 | amdfwtool_cleanup(ctx); |
Zheng Bao | c26108f | 2023-02-17 11:01:07 +0800 | [diff] [blame] | 551 | exit(1); |
| 552 | } |
| 553 | |
| 554 | ctx->current_pointer_saved = ctx->current; |
| 555 | } |
| 556 | |
| 557 | static void adjust_current_pointer(context *ctx, uint32_t add, uint32_t align) |
| 558 | { |
| 559 | /* Get */ |
| 560 | set_current_pointer(ctx, ALIGN_UP(ctx->current + add, align)); |
| 561 | } |
| 562 | |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 563 | static void *new_psp_dir(context *ctx, int multi) |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 564 | { |
| 565 | void *ptr; |
| 566 | |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 567 | /* |
| 568 | * Force both onto boundary when multi. Primary table is after |
| 569 | * updatable table, so alignment ensures primary can stay intact |
| 570 | * if secondary is reprogrammed. |
| 571 | */ |
| 572 | if (multi) |
Zheng Bao | c26108f | 2023-02-17 11:01:07 +0800 | [diff] [blame] | 573 | adjust_current_pointer(ctx, 0, TABLE_ERASE_ALIGNMENT); |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 574 | else |
Zheng Bao | c26108f | 2023-02-17 11:01:07 +0800 | [diff] [blame] | 575 | adjust_current_pointer(ctx, 0, TABLE_ALIGNMENT); |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 576 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 577 | ptr = BUFF_CURRENT(*ctx); |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 578 | ((psp_directory_header *)ptr)->num_entries = 0; |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 579 | ((psp_directory_header *)ptr)->additional_info = 0; |
| 580 | ((psp_directory_header *)ptr)->additional_info_fields.address_mode = ctx->address_mode; |
Zheng Bao | c26108f | 2023-02-17 11:01:07 +0800 | [diff] [blame] | 581 | adjust_current_pointer(ctx, |
| 582 | sizeof(psp_directory_header) + MAX_PSP_ENTRIES * sizeof(psp_directory_entry), |
| 583 | 1); |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 584 | return ptr; |
| 585 | } |
| 586 | |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 587 | static void *new_ish_dir(context *ctx) |
| 588 | { |
| 589 | void *ptr; |
Zheng Bao | c26108f | 2023-02-17 11:01:07 +0800 | [diff] [blame] | 590 | adjust_current_pointer(ctx, 0, TABLE_ALIGNMENT); |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 591 | ptr = BUFF_CURRENT(*ctx); |
Zheng Bao | c26108f | 2023-02-17 11:01:07 +0800 | [diff] [blame] | 592 | adjust_current_pointer(ctx, TABLE_ALIGNMENT, 1); |
| 593 | |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 594 | return ptr; |
| 595 | } |
| 596 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 597 | static void *new_combo_dir(context *ctx) |
| 598 | { |
| 599 | void *ptr; |
| 600 | |
Zheng Bao | c26108f | 2023-02-17 11:01:07 +0800 | [diff] [blame] | 601 | adjust_current_pointer(ctx, 0, TABLE_ALIGNMENT); |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 602 | ptr = BUFF_CURRENT(*ctx); |
Zheng Bao | c26108f | 2023-02-17 11:01:07 +0800 | [diff] [blame] | 603 | adjust_current_pointer(ctx, |
| 604 | sizeof(psp_combo_header) + MAX_COMBO_ENTRIES * sizeof(psp_combo_entry), |
| 605 | 1); |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 606 | return ptr; |
| 607 | } |
| 608 | |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 609 | static void fill_dir_header(void *directory, uint32_t count, uint32_t cookie, context *ctx) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 610 | { |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 611 | psp_combo_directory *cdir = directory; |
| 612 | psp_directory_table *dir = directory; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 613 | bios_directory_table *bdir = directory; |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 614 | uint32_t table_size = 0; |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 615 | |
| 616 | if (!count) |
| 617 | return; |
Zheng Bao | b035f58 | 2021-05-27 11:26:12 +0800 | [diff] [blame] | 618 | if (ctx == NULL || directory == NULL) { |
| 619 | fprintf(stderr, "Calling %s with NULL pointers\n", __func__); |
| 620 | return; |
| 621 | } |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 622 | |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 623 | /* The table size needs to be 0x1000 aligned. So align the end of table. */ |
Zheng Bao | c26108f | 2023-02-17 11:01:07 +0800 | [diff] [blame] | 624 | adjust_current_pointer(ctx, 0, TABLE_ALIGNMENT); |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 625 | |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 626 | switch (cookie) { |
| 627 | case PSP2_COOKIE: |
Zheng Bao | 84fb9ea | 2022-08-18 15:54:47 +0800 | [diff] [blame] | 628 | case BHD2_COOKIE: |
Marshall Dawson | a378c22 | 2019-03-04 16:52:07 -0700 | [diff] [blame] | 629 | cdir->header.cookie = cookie; |
Zheng Bao | fd51af6 | 2022-08-18 15:26:39 +0800 | [diff] [blame] | 630 | /* lookup mode is hardcoded for now. */ |
| 631 | cdir->header.lookup = 1; |
Marshall Dawson | a378c22 | 2019-03-04 16:52:07 -0700 | [diff] [blame] | 632 | cdir->header.num_entries = count; |
| 633 | cdir->header.reserved[0] = 0; |
| 634 | cdir->header.reserved[1] = 0; |
| 635 | /* checksum everything that comes after the Checksum field */ |
| 636 | cdir->header.checksum = fletcher32(&cdir->header.num_entries, |
| 637 | count * sizeof(psp_combo_entry) |
| 638 | + sizeof(cdir->header.num_entries) |
| 639 | + sizeof(cdir->header.lookup) |
| 640 | + 2 * sizeof(cdir->header.reserved[0])); |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 641 | break; |
| 642 | case PSP_COOKIE: |
| 643 | case PSPL2_COOKIE: |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 644 | table_size = ctx->current - ctx->current_table; |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 645 | if ((table_size % TABLE_ALIGNMENT) != 0) { |
| 646 | fprintf(stderr, "The PSP table size should be 4K aligned\n"); |
Zheng Bao | 7c5ad88 | 2023-02-19 13:02:52 +0800 | [diff] [blame] | 647 | amdfwtool_cleanup(ctx); |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 648 | exit(1); |
| 649 | } |
Marshall Dawson | a378c22 | 2019-03-04 16:52:07 -0700 | [diff] [blame] | 650 | dir->header.cookie = cookie; |
| 651 | dir->header.num_entries = count; |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 652 | dir->header.additional_info_fields.dir_size = table_size / TABLE_ALIGNMENT; |
| 653 | dir->header.additional_info_fields.spi_block_size = 1; |
| 654 | dir->header.additional_info_fields.base_addr = 0; |
Marshall Dawson | a378c22 | 2019-03-04 16:52:07 -0700 | [diff] [blame] | 655 | /* checksum everything that comes after the Checksum field */ |
| 656 | dir->header.checksum = fletcher32(&dir->header.num_entries, |
Marshall Dawson | 8a45a4d | 2019-02-24 07:18:44 -0700 | [diff] [blame] | 657 | count * sizeof(psp_directory_entry) |
Marshall Dawson | a378c22 | 2019-03-04 16:52:07 -0700 | [diff] [blame] | 658 | + sizeof(dir->header.num_entries) |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 659 | + sizeof(dir->header.additional_info)); |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 660 | break; |
Zheng Bao | 96a3371 | 2021-06-11 15:54:40 +0800 | [diff] [blame] | 661 | case BHD_COOKIE: |
| 662 | case BHDL2_COOKIE: |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 663 | table_size = ctx->current - ctx->current_table; |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 664 | if ((table_size % TABLE_ALIGNMENT) != 0) { |
| 665 | fprintf(stderr, "The BIOS table size should be 4K aligned\n"); |
Zheng Bao | 7c5ad88 | 2023-02-19 13:02:52 +0800 | [diff] [blame] | 666 | amdfwtool_cleanup(ctx); |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 667 | exit(1); |
| 668 | } |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 669 | bdir->header.cookie = cookie; |
| 670 | bdir->header.num_entries = count; |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 671 | bdir->header.additional_info_fields.dir_size = table_size / TABLE_ALIGNMENT; |
| 672 | bdir->header.additional_info_fields.spi_block_size = 1; |
| 673 | bdir->header.additional_info_fields.base_addr = 0; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 674 | /* checksum everything that comes after the Checksum field */ |
| 675 | bdir->header.checksum = fletcher32(&bdir->header.num_entries, |
| 676 | count * sizeof(bios_directory_entry) |
| 677 | + sizeof(bdir->header.num_entries) |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 678 | + sizeof(bdir->header.additional_info)); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 679 | break; |
Marshall Dawson | a378c22 | 2019-03-04 16:52:07 -0700 | [diff] [blame] | 680 | } |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 681 | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 682 | } |
| 683 | |
Zheng Bao | 2f6b7d5 | 2023-02-11 22:27:49 +0800 | [diff] [blame] | 684 | static void fill_psp_directory_to_efs(embedded_firmware *amd_romsig, void *pspdir, |
| 685 | context *ctx, amd_cb_config *cb_config) |
| 686 | { |
| 687 | switch (cb_config->soc_id) { |
| 688 | case PLATFORM_UNKNOWN: |
| 689 | amd_romsig->psp_directory = |
| 690 | BUFF_TO_RUN_MODE(*ctx, pspdir, AMD_ADDR_REL_BIOS); |
| 691 | break; |
| 692 | case PLATFORM_CEZANNE: |
| 693 | case PLATFORM_MENDOCINO: |
| 694 | case PLATFORM_PHOENIX: |
| 695 | case PLATFORM_GLINDA: |
| 696 | case PLATFORM_CARRIZO: |
| 697 | case PLATFORM_STONEYRIDGE: |
| 698 | case PLATFORM_RAVEN: |
| 699 | case PLATFORM_PICASSO: |
| 700 | case PLATFORM_LUCIENNE: |
| 701 | case PLATFORM_RENOIR: |
| 702 | default: |
| 703 | /* for combo, it is also combo_psp_directory */ |
| 704 | amd_romsig->new_psp_directory = |
| 705 | BUFF_TO_RUN_MODE(*ctx, pspdir, AMD_ADDR_REL_BIOS); |
| 706 | break; |
| 707 | } |
| 708 | } |
| 709 | |
| 710 | static void fill_bios_directory_to_efs(embedded_firmware *amd_romsig, void *biosdir, |
| 711 | context *ctx, amd_cb_config *cb_config) |
| 712 | { |
| 713 | switch (cb_config->soc_id) { |
| 714 | case PLATFORM_RENOIR: |
| 715 | case PLATFORM_LUCIENNE: |
| 716 | case PLATFORM_CEZANNE: |
| 717 | if (!cb_config->recovery_ab) |
| 718 | amd_romsig->bios3_entry = |
| 719 | BUFF_TO_RUN_MODE(*ctx, biosdir, AMD_ADDR_REL_BIOS); |
| 720 | break; |
| 721 | case PLATFORM_MENDOCINO: |
| 722 | case PLATFORM_PHOENIX: |
| 723 | case PLATFORM_GLINDA: |
| 724 | break; |
| 725 | case PLATFORM_CARRIZO: |
| 726 | case PLATFORM_STONEYRIDGE: |
| 727 | case PLATFORM_RAVEN: |
| 728 | case PLATFORM_PICASSO: |
| 729 | default: |
| 730 | amd_romsig->bios1_entry = |
| 731 | BUFF_TO_RUN_MODE(*ctx, biosdir, AMD_ADDR_REL_BIOS); |
| 732 | break; |
| 733 | } |
| 734 | } |
| 735 | |
Marshall Dawson | 8e0dca0 | 2019-02-27 18:40:49 -0700 | [diff] [blame] | 736 | static ssize_t copy_blob(void *dest, const char *src_file, size_t room) |
| 737 | { |
| 738 | int fd; |
| 739 | struct stat fd_stat; |
| 740 | ssize_t bytes; |
| 741 | |
| 742 | fd = open(src_file, O_RDONLY); |
| 743 | if (fd < 0) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 744 | fprintf(stderr, "Error opening file: %s: %s\n", |
Eric Peers | af50567 | 2020-03-05 16:04:15 -0700 | [diff] [blame] | 745 | src_file, strerror(errno)); |
Marshall Dawson | 8e0dca0 | 2019-02-27 18:40:49 -0700 | [diff] [blame] | 746 | return -1; |
| 747 | } |
| 748 | |
| 749 | if (fstat(fd, &fd_stat)) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 750 | fprintf(stderr, "fstat error: %s\n", strerror(errno)); |
Jacob Garber | 967f862 | 2019-07-02 10:35:10 -0600 | [diff] [blame] | 751 | close(fd); |
Marshall Dawson | 8e0dca0 | 2019-02-27 18:40:49 -0700 | [diff] [blame] | 752 | return -2; |
| 753 | } |
| 754 | |
Zheng Bao | 6d402ac | 2020-10-01 16:16:30 +0800 | [diff] [blame] | 755 | if ((size_t)fd_stat.st_size > room) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 756 | fprintf(stderr, "Error: %s will not fit. Exiting.\n", src_file); |
Jacob Garber | 967f862 | 2019-07-02 10:35:10 -0600 | [diff] [blame] | 757 | close(fd); |
Marshall Dawson | 8e0dca0 | 2019-02-27 18:40:49 -0700 | [diff] [blame] | 758 | return -3; |
| 759 | } |
| 760 | |
| 761 | bytes = read(fd, dest, (size_t)fd_stat.st_size); |
| 762 | close(fd); |
| 763 | if (bytes != (ssize_t)fd_stat.st_size) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 764 | fprintf(stderr, "Error while reading %s\n", src_file); |
Marshall Dawson | 8e0dca0 | 2019-02-27 18:40:49 -0700 | [diff] [blame] | 765 | return -4; |
| 766 | } |
| 767 | |
| 768 | return bytes; |
| 769 | } |
| 770 | |
Zheng Bao | eb0404e | 2021-10-14 15:09:09 +0800 | [diff] [blame] | 771 | static uint32_t get_psp_id(enum platform soc_id) |
| 772 | { |
| 773 | uint32_t psp_id; |
| 774 | switch (soc_id) { |
| 775 | case PLATFORM_RAVEN: |
| 776 | case PLATFORM_PICASSO: |
| 777 | psp_id = 0xBC0A0000; |
| 778 | break; |
| 779 | case PLATFORM_RENOIR: |
| 780 | case PLATFORM_LUCIENNE: |
| 781 | psp_id = 0xBC0C0000; |
| 782 | break; |
| 783 | case PLATFORM_CEZANNE: |
| 784 | psp_id = 0xBC0C0140; |
| 785 | break; |
| 786 | case PLATFORM_MENDOCINO: |
| 787 | psp_id = 0xBC0D0900; |
| 788 | break; |
| 789 | case PLATFORM_STONEYRIDGE: |
| 790 | psp_id = 0x10220B00; |
| 791 | break; |
Zheng Bao | de6f198 | 2022-10-16 20:32:43 +0800 | [diff] [blame] | 792 | case PLATFORM_GLINDA: |
| 793 | psp_id = 0xBC0E0200; |
| 794 | break; |
| 795 | case PLATFORM_PHOENIX: |
| 796 | psp_id = 0xBC0D0400; |
| 797 | break; |
Zheng Bao | 3d7623f | 2022-08-17 11:52:30 +0800 | [diff] [blame] | 798 | case PLATFORM_CARRIZO: |
Zheng Bao | eb0404e | 2021-10-14 15:09:09 +0800 | [diff] [blame] | 799 | default: |
| 800 | psp_id = 0; |
| 801 | break; |
| 802 | } |
| 803 | return psp_id; |
| 804 | } |
| 805 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 806 | static void integrate_firmwares(context *ctx, |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 807 | embedded_firmware *romsig, |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 808 | amd_fw_entry *fw_table) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 809 | { |
Richard Spiegel | 137484d | 2018-01-17 10:23:19 -0700 | [diff] [blame] | 810 | ssize_t bytes; |
Zheng Bao | 6d402ac | 2020-10-01 16:16:30 +0800 | [diff] [blame] | 811 | uint32_t i; |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 812 | |
Zheng Bao | c26108f | 2023-02-17 11:01:07 +0800 | [diff] [blame] | 813 | adjust_current_pointer(ctx, 0, BLOB_ALIGNMENT); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 814 | |
Martin Roth | cd15bc8 | 2016-11-08 11:34:02 -0700 | [diff] [blame] | 815 | for (i = 0; fw_table[i].type != AMD_FW_INVALID; i++) { |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 816 | if (fw_table[i].filename != NULL) { |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 817 | switch (fw_table[i].type) { |
| 818 | case AMD_FW_IMC: |
Zheng Bao | c26108f | 2023-02-17 11:01:07 +0800 | [diff] [blame] | 819 | adjust_current_pointer(ctx, 0, 0x10000U); |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 820 | romsig->imc_entry = RUN_CURRENT(*ctx); |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 821 | break; |
| 822 | case AMD_FW_GEC: |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 823 | romsig->gec_entry = RUN_CURRENT(*ctx); |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 824 | break; |
| 825 | case AMD_FW_XHCI: |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 826 | romsig->xhci_entry = RUN_CURRENT(*ctx); |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 827 | break; |
| 828 | default: |
| 829 | /* Error */ |
| 830 | break; |
| 831 | } |
| 832 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 833 | bytes = copy_blob(BUFF_CURRENT(*ctx), |
| 834 | fw_table[i].filename, BUFF_ROOM(*ctx)); |
Marshall Dawson | 02bd773 | 2019-03-13 14:43:17 -0600 | [diff] [blame] | 835 | if (bytes < 0) { |
Zheng Bao | 7c5ad88 | 2023-02-19 13:02:52 +0800 | [diff] [blame] | 836 | amdfwtool_cleanup(ctx); |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 837 | exit(1); |
| 838 | } |
| 839 | |
Zheng Bao | c26108f | 2023-02-17 11:01:07 +0800 | [diff] [blame] | 840 | adjust_current_pointer(ctx, bytes, BLOB_ALIGNMENT); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 841 | } |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 842 | } |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 843 | } |
| 844 | |
Zheng Bao | 9e90807 | 2020-10-28 11:39:13 +0800 | [diff] [blame] | 845 | /* For debugging */ |
| 846 | static void dump_psp_firmwares(amd_fw_entry *fw_table) |
| 847 | { |
| 848 | amd_fw_entry *index; |
| 849 | |
| 850 | printf("PSP firmware components:"); |
| 851 | for (index = fw_table; index->type != AMD_FW_INVALID; index++) { |
| 852 | if (index->filename) |
Zheng Bao | 826f1c4 | 2021-05-25 16:26:55 +0800 | [diff] [blame] | 853 | printf(" %2x: %s\n", index->type, index->filename); |
Zheng Bao | 9e90807 | 2020-10-28 11:39:13 +0800 | [diff] [blame] | 854 | } |
| 855 | } |
| 856 | |
| 857 | static void dump_bdt_firmwares(amd_bios_entry *fw_table) |
| 858 | { |
| 859 | amd_bios_entry *index; |
| 860 | |
| 861 | printf("BIOS Directory Table (BDT) components:"); |
| 862 | for (index = fw_table; index->type != AMD_BIOS_INVALID; index++) { |
| 863 | if (index->filename) |
Zheng Bao | 826f1c4 | 2021-05-25 16:26:55 +0800 | [diff] [blame] | 864 | printf(" %2x: %s\n", index->type, index->filename); |
Zheng Bao | 9e90807 | 2020-10-28 11:39:13 +0800 | [diff] [blame] | 865 | } |
| 866 | } |
| 867 | |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 868 | static void integrate_psp_ab(context *ctx, psp_directory_table *pspdir, |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 869 | psp_directory_table *pspdir2, ish_directory_table *ish, |
| 870 | amd_fw_type ab, enum platform soc_id) |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 871 | { |
| 872 | uint32_t count; |
| 873 | uint32_t current_table_save; |
| 874 | |
| 875 | current_table_save = ctx->current_table; |
| 876 | ctx->current_table = (char *)pspdir - ctx->rom; |
| 877 | count = pspdir->header.num_entries; |
| 878 | assert_fw_entry(count, MAX_PSP_ENTRIES, ctx); |
| 879 | pspdir->entries[count].type = (uint8_t)ab; |
| 880 | pspdir->entries[count].subprog = 0; |
| 881 | pspdir->entries[count].rsvd = 0; |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 882 | if (ish != NULL) { |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 883 | ish->pl2_location = BUFF_TO_RUN_MODE(*ctx, pspdir2, AMD_ADDR_REL_BIOS); |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 884 | ish->boot_priority = ab == AMD_FW_RECOVERYAB_A ? 0xFFFFFFFF : 1; |
| 885 | ish->update_retry_count = 2; |
| 886 | ish->glitch_retry_count = 0; |
| 887 | ish->psp_id = get_psp_id(soc_id); |
| 888 | ish->checksum = fletcher32(&ish->boot_priority, |
| 889 | sizeof(ish_directory_table) - sizeof(uint32_t)); |
| 890 | pspdir->entries[count].addr = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 891 | BUFF_TO_RUN_MODE(*ctx, ish, AMD_ADDR_REL_BIOS); |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 892 | pspdir->entries[count].address_mode = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 893 | SET_ADDR_MODE(pspdir, AMD_ADDR_REL_BIOS); |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 894 | pspdir->entries[count].size = TABLE_ALIGNMENT; |
| 895 | } else { |
| 896 | pspdir->entries[count].addr = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 897 | BUFF_TO_RUN_MODE(*ctx, pspdir2, AMD_ADDR_REL_BIOS); |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 898 | pspdir->entries[count].address_mode = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 899 | SET_ADDR_MODE(pspdir, AMD_ADDR_REL_BIOS); |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 900 | pspdir->entries[count].size = pspdir2->header.num_entries * |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 901 | sizeof(psp_directory_entry) + |
| 902 | sizeof(psp_directory_header); |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 903 | } |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 904 | |
| 905 | count++; |
| 906 | pspdir->header.num_entries = count; |
| 907 | ctx->current_table = current_table_save; |
| 908 | } |
| 909 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 910 | static void integrate_psp_firmwares(context *ctx, |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 911 | psp_directory_table *pspdir, |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 912 | psp_directory_table *pspdir2, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 913 | psp_directory_table *pspdir2_b, |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 914 | amd_fw_entry *fw_table, |
Zheng Bao | 2079589 | 2021-08-20 14:58:22 +0800 | [diff] [blame] | 915 | uint32_t cookie, |
| 916 | amd_cb_config *cb_config) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 917 | { |
Richard Spiegel | 137484d | 2018-01-17 10:23:19 -0700 | [diff] [blame] | 918 | ssize_t bytes; |
Marshall Dawson | c38c0c9 | 2019-02-23 16:41:35 -0700 | [diff] [blame] | 919 | unsigned int i, count; |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 920 | int level; |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 921 | uint32_t size; |
| 922 | uint64_t addr; |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 923 | uint32_t current_table_save; |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 924 | bool recovery_ab = cb_config->recovery_ab; |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 925 | ish_directory_table *ish_a_dir = NULL, *ish_b_dir = NULL; |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 926 | |
| 927 | /* This function can create a primary table, a secondary table, or a |
| 928 | * flattened table which contains all applicable types. These if-else |
| 929 | * statements infer what the caller intended. If a 2nd-level cookie |
| 930 | * is passed, clearly a 2nd-level table is intended. However, a |
| 931 | * 1st-level cookie may indicate level 1 or flattened. If the caller |
| 932 | * passes a pointer to a 2nd-level table, then assume not flat. |
| 933 | */ |
Zheng Bao | ba3af5e | 2021-11-04 18:56:47 +0800 | [diff] [blame] | 934 | if (!cb_config->multi_level) |
Zheng Bao | 2079589 | 2021-08-20 14:58:22 +0800 | [diff] [blame] | 935 | level = PSP_BOTH; |
| 936 | else if (cookie == PSPL2_COOKIE) |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 937 | level = PSP_LVL2; |
| 938 | else if (pspdir2) |
| 939 | level = PSP_LVL1; |
| 940 | else |
| 941 | level = PSP_BOTH; |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 942 | |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 943 | if (recovery_ab) { |
| 944 | if (cookie == PSPL2_COOKIE) |
| 945 | level = PSP_LVL2_AB; |
| 946 | else if (pspdir2) |
| 947 | level = PSP_LVL1_AB; |
| 948 | else |
| 949 | level = PSP_BOTH_AB; |
| 950 | } |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 951 | current_table_save = ctx->current_table; |
| 952 | ctx->current_table = (char *)pspdir - ctx->rom; |
Zheng Bao | c26108f | 2023-02-17 11:01:07 +0800 | [diff] [blame] | 953 | adjust_current_pointer(ctx, 0, TABLE_ALIGNMENT); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 954 | |
Marshall Dawson | c38c0c9 | 2019-02-23 16:41:35 -0700 | [diff] [blame] | 955 | for (i = 0, count = 0; fw_table[i].type != AMD_FW_INVALID; i++) { |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 956 | if (!(fw_table[i].level & level)) |
| 957 | continue; |
| 958 | |
Zheng Bao | 5164e4b | 2021-10-30 12:09:07 +0800 | [diff] [blame] | 959 | assert_fw_entry(count, MAX_PSP_ENTRIES, ctx); |
| 960 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 961 | if (fw_table[i].type == AMD_TOKEN_UNLOCK) { |
| 962 | if (!fw_table[i].other) |
| 963 | continue; |
Zheng Bao | c26108f | 2023-02-17 11:01:07 +0800 | [diff] [blame] | 964 | adjust_current_pointer(ctx, 0, ERASE_ALIGNMENT); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 965 | pspdir->entries[count].type = fw_table[i].type; |
| 966 | pspdir->entries[count].size = 4096; /* TODO: doc? */ |
| 967 | pspdir->entries[count].addr = RUN_CURRENT(*ctx); |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 968 | pspdir->entries[count].address_mode = SET_ADDR_MODE_BY_TABLE(pspdir); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 969 | pspdir->entries[count].subprog = fw_table[i].subprog; |
| 970 | pspdir->entries[count].rsvd = 0; |
Zheng Bao | c26108f | 2023-02-17 11:01:07 +0800 | [diff] [blame] | 971 | adjust_current_pointer(ctx, 4096, 0x100U); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 972 | count++; |
| 973 | } else if (fw_table[i].type == AMD_PSP_FUSE_CHAIN) { |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 974 | pspdir->entries[count].type = fw_table[i].type; |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 975 | pspdir->entries[count].subprog = fw_table[i].subprog; |
| 976 | pspdir->entries[count].rsvd = 0; |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 977 | pspdir->entries[count].size = 0xFFFFFFFF; |
Marshall Dawson | ef79fcc | 2019-04-01 10:16:41 -0600 | [diff] [blame] | 978 | pspdir->entries[count].addr = fw_table[i].other; |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 979 | pspdir->entries[count].address_mode = 0; |
Marshall Dawson | c38c0c9 | 2019-02-23 16:41:35 -0700 | [diff] [blame] | 980 | count++; |
Marshall Dawson | 7c1e142 | 2019-04-11 09:44:43 -0600 | [diff] [blame] | 981 | } else if (fw_table[i].type == AMD_FW_PSP_NVRAM) { |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 982 | if (fw_table[i].filename == NULL) { |
| 983 | if (fw_table[i].size == 0) |
| 984 | continue; |
| 985 | size = fw_table[i].size; |
| 986 | addr = fw_table[i].dest; |
Elyes Haouas | 7d67a19 | 2022-10-14 09:58:29 +0200 | [diff] [blame] | 987 | if (addr != ALIGN_UP(addr, ERASE_ALIGNMENT)) { |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 988 | fprintf(stderr, |
| 989 | "Error: PSP NVRAM section not aligned with erase block size.\n\n"); |
Zheng Bao | 7c5ad88 | 2023-02-19 13:02:52 +0800 | [diff] [blame] | 990 | amdfwtool_cleanup(ctx); |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 991 | exit(1); |
| 992 | } |
| 993 | } else { |
Zheng Bao | c26108f | 2023-02-17 11:01:07 +0800 | [diff] [blame] | 994 | adjust_current_pointer(ctx, 0, ERASE_ALIGNMENT); |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 995 | bytes = copy_blob(BUFF_CURRENT(*ctx), |
| 996 | fw_table[i].filename, BUFF_ROOM(*ctx)); |
| 997 | if (bytes <= 0) { |
Zheng Bao | 7c5ad88 | 2023-02-19 13:02:52 +0800 | [diff] [blame] | 998 | amdfwtool_cleanup(ctx); |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 999 | exit(1); |
| 1000 | } |
| 1001 | |
Elyes Haouas | 7d67a19 | 2022-10-14 09:58:29 +0200 | [diff] [blame] | 1002 | size = ALIGN_UP(bytes, ERASE_ALIGNMENT); |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 1003 | addr = RUN_CURRENT(*ctx); |
Zheng Bao | c26108f | 2023-02-17 11:01:07 +0800 | [diff] [blame] | 1004 | adjust_current_pointer(ctx, bytes, BLOB_ERASE_ALIGNMENT); |
Marshall Dawson | 7c1e142 | 2019-04-11 09:44:43 -0600 | [diff] [blame] | 1005 | } |
| 1006 | |
| 1007 | pspdir->entries[count].type = fw_table[i].type; |
| 1008 | pspdir->entries[count].subprog = fw_table[i].subprog; |
| 1009 | pspdir->entries[count].rsvd = 0; |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 1010 | pspdir->entries[count].size = size; |
| 1011 | pspdir->entries[count].addr = addr; |
| 1012 | |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1013 | pspdir->entries[count].address_mode = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 1014 | SET_ADDR_MODE(pspdir, AMD_ADDR_REL_BIOS); |
Marshall Dawson | 7c1e142 | 2019-04-11 09:44:43 -0600 | [diff] [blame] | 1015 | |
Marshall Dawson | 7c1e142 | 2019-04-11 09:44:43 -0600 | [diff] [blame] | 1016 | count++; |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 1017 | } else if (fw_table[i].filename != NULL) { |
Kangheui Won | 3c164e1 | 2021-12-03 20:25:05 +1100 | [diff] [blame] | 1018 | if (fw_table[i].addr_signed) { |
| 1019 | pspdir->entries[count].addr = |
| 1020 | RUN_OFFSET(*ctx, fw_table[i].addr_signed); |
| 1021 | pspdir->entries[count].address_mode = |
| 1022 | SET_ADDR_MODE_BY_TABLE(pspdir); |
| 1023 | bytes = fw_table[i].file_size; |
| 1024 | } else { |
| 1025 | bytes = copy_blob(BUFF_CURRENT(*ctx), |
| 1026 | fw_table[i].filename, BUFF_ROOM(*ctx)); |
| 1027 | if (bytes < 0) { |
Zheng Bao | 7c5ad88 | 2023-02-19 13:02:52 +0800 | [diff] [blame] | 1028 | amdfwtool_cleanup(ctx); |
Kangheui Won | 3c164e1 | 2021-12-03 20:25:05 +1100 | [diff] [blame] | 1029 | exit(1); |
| 1030 | } |
| 1031 | pspdir->entries[count].addr = RUN_CURRENT(*ctx); |
| 1032 | pspdir->entries[count].address_mode = |
| 1033 | SET_ADDR_MODE_BY_TABLE(pspdir); |
Zheng Bao | c26108f | 2023-02-17 11:01:07 +0800 | [diff] [blame] | 1034 | adjust_current_pointer(ctx, bytes, BLOB_ALIGNMENT); |
Marshall Dawson | 8e0dca0 | 2019-02-27 18:40:49 -0700 | [diff] [blame] | 1035 | } |
| 1036 | |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 1037 | pspdir->entries[count].type = fw_table[i].type; |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1038 | pspdir->entries[count].subprog = fw_table[i].subprog; |
| 1039 | pspdir->entries[count].rsvd = 0; |
Fred Reitberger | 75191be | 2023-03-07 11:00:49 -0500 | [diff] [blame] | 1040 | pspdir->entries[count].inst = fw_table[i].inst; |
Marshall Dawson | 8e0dca0 | 2019-02-27 18:40:49 -0700 | [diff] [blame] | 1041 | pspdir->entries[count].size = (uint32_t)bytes; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1042 | |
Marshall Dawson | c38c0c9 | 2019-02-23 16:41:35 -0700 | [diff] [blame] | 1043 | count++; |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 1044 | } else { |
| 1045 | /* This APU doesn't have this firmware. */ |
| 1046 | } |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1047 | } |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1048 | |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1049 | if (recovery_ab && (pspdir2 != NULL)) { |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 1050 | if (cb_config->need_ish) { /* Need ISH */ |
| 1051 | ish_a_dir = new_ish_dir(ctx); |
| 1052 | if (pspdir2_b != NULL) |
| 1053 | ish_b_dir = new_ish_dir(ctx); |
| 1054 | } |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1055 | pspdir->header.num_entries = count; |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 1056 | integrate_psp_ab(ctx, pspdir, pspdir2, ish_a_dir, |
Zheng Bao | 4bf6f49 | 2023-01-25 22:37:29 +0800 | [diff] [blame] | 1057 | AMD_FW_RECOVERYAB_A, cb_config->soc_id); |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1058 | if (pspdir2_b != NULL) |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 1059 | integrate_psp_ab(ctx, pspdir, pspdir2_b, ish_b_dir, |
Zheng Bao | 4bf6f49 | 2023-01-25 22:37:29 +0800 | [diff] [blame] | 1060 | AMD_FW_RECOVERYAB_B, cb_config->soc_id); |
Karthikeyan Ramasubramanian | ad06bae | 2022-04-08 14:19:55 -0600 | [diff] [blame] | 1061 | else |
Karthikeyan Ramasubramanian | e5af14a | 2022-08-02 11:34:48 -0600 | [diff] [blame] | 1062 | integrate_psp_ab(ctx, pspdir, pspdir2, ish_a_dir, |
Zheng Bao | 4bf6f49 | 2023-01-25 22:37:29 +0800 | [diff] [blame] | 1063 | AMD_FW_RECOVERYAB_B, cb_config->soc_id); |
Karthikeyan Ramasubramanian | ad06bae | 2022-04-08 14:19:55 -0600 | [diff] [blame] | 1064 | |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1065 | count = pspdir->header.num_entries; |
| 1066 | } else if (pspdir2 != NULL) { |
Zheng Bao | 5164e4b | 2021-10-30 12:09:07 +0800 | [diff] [blame] | 1067 | assert_fw_entry(count, MAX_PSP_ENTRIES, ctx); |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 1068 | pspdir->entries[count].type = AMD_FW_L2_PTR; |
| 1069 | pspdir->entries[count].subprog = 0; |
| 1070 | pspdir->entries[count].rsvd = 0; |
| 1071 | pspdir->entries[count].size = sizeof(pspdir2->header) |
| 1072 | + pspdir2->header.num_entries |
| 1073 | * sizeof(psp_directory_entry); |
| 1074 | |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1075 | pspdir->entries[count].addr = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 1076 | BUFF_TO_RUN_MODE(*ctx, pspdir2, AMD_ADDR_REL_BIOS); |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1077 | pspdir->entries[count].address_mode = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 1078 | SET_ADDR_MODE(pspdir, AMD_ADDR_REL_BIOS); |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 1079 | count++; |
| 1080 | } |
| 1081 | |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 1082 | fill_dir_header(pspdir, count, cookie, ctx); |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1083 | ctx->current_table = current_table_save; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1084 | } |
| 1085 | |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1086 | static void add_psp_firmware_entry(context *ctx, |
| 1087 | psp_directory_table *pspdir, |
| 1088 | void *table, amd_fw_type type, uint32_t size) |
| 1089 | { |
| 1090 | uint32_t count = pspdir->header.num_entries; |
| 1091 | uint32_t index; |
| 1092 | uint32_t current_table_save; |
| 1093 | |
| 1094 | current_table_save = ctx->current_table; |
| 1095 | ctx->current_table = (char *)pspdir - ctx->rom; |
| 1096 | |
| 1097 | /* If there is an entry of "type", replace it. */ |
| 1098 | for (index = 0; index < count; index++) { |
| 1099 | if (pspdir->entries[index].type == (uint8_t)type) |
| 1100 | break; |
| 1101 | } |
| 1102 | |
| 1103 | assert_fw_entry(count, MAX_PSP_ENTRIES, ctx); |
| 1104 | pspdir->entries[index].type = (uint8_t)type; |
| 1105 | pspdir->entries[index].subprog = 0; |
| 1106 | pspdir->entries[index].rsvd = 0; |
| 1107 | pspdir->entries[index].addr = BUFF_TO_RUN(*ctx, table); |
| 1108 | pspdir->entries[index].address_mode = SET_ADDR_MODE_BY_TABLE(pspdir); |
| 1109 | pspdir->entries[index].size = size; |
| 1110 | if (index == count) |
| 1111 | count++; |
| 1112 | |
| 1113 | pspdir->header.num_entries = count; |
| 1114 | pspdir->header.checksum = fletcher32(&pspdir->header.num_entries, |
| 1115 | count * sizeof(psp_directory_entry) |
| 1116 | + sizeof(pspdir->header.num_entries) |
| 1117 | + sizeof(pspdir->header.additional_info)); |
| 1118 | |
| 1119 | ctx->current_table = current_table_save; |
| 1120 | } |
| 1121 | |
Zheng Bao | ba3af5e | 2021-11-04 18:56:47 +0800 | [diff] [blame] | 1122 | static void *new_bios_dir(context *ctx, bool multi) |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1123 | { |
| 1124 | void *ptr; |
| 1125 | |
| 1126 | /* |
| 1127 | * Force both onto boundary when multi. Primary table is after |
| 1128 | * updatable table, so alignment ensures primary can stay intact |
| 1129 | * if secondary is reprogrammed. |
| 1130 | */ |
| 1131 | if (multi) |
Zheng Bao | c26108f | 2023-02-17 11:01:07 +0800 | [diff] [blame] | 1132 | adjust_current_pointer(ctx, 0, TABLE_ERASE_ALIGNMENT); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1133 | else |
Zheng Bao | c26108f | 2023-02-17 11:01:07 +0800 | [diff] [blame] | 1134 | adjust_current_pointer(ctx, 0, TABLE_ALIGNMENT); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1135 | ptr = BUFF_CURRENT(*ctx); |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1136 | ((bios_directory_hdr *) ptr)->additional_info = 0; |
| 1137 | ((bios_directory_hdr *) ptr)->additional_info_fields.address_mode = ctx->address_mode; |
| 1138 | ctx->current_table = ctx->current; |
Zheng Bao | c26108f | 2023-02-17 11:01:07 +0800 | [diff] [blame] | 1139 | adjust_current_pointer(ctx, |
| 1140 | sizeof(bios_directory_hdr) + MAX_BIOS_ENTRIES * sizeof(bios_directory_entry), |
| 1141 | 1); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1142 | return ptr; |
| 1143 | } |
| 1144 | |
| 1145 | static int locate_bdt2_bios(bios_directory_table *level2, |
| 1146 | uint64_t *source, uint32_t *size) |
| 1147 | { |
Zheng Bao | 6d402ac | 2020-10-01 16:16:30 +0800 | [diff] [blame] | 1148 | uint32_t i; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1149 | |
| 1150 | *source = 0; |
| 1151 | *size = 0; |
| 1152 | if (!level2) |
| 1153 | return 0; |
| 1154 | |
| 1155 | for (i = 0 ; i < level2->header.num_entries ; i++) { |
| 1156 | if (level2->entries[i].type == AMD_BIOS_BIN) { |
| 1157 | *source = level2->entries[i].source; |
| 1158 | *size = level2->entries[i].size; |
| 1159 | return 1; |
| 1160 | } |
| 1161 | } |
| 1162 | return 0; |
| 1163 | } |
| 1164 | |
| 1165 | static int have_bios_tables(amd_bios_entry *table) |
| 1166 | { |
| 1167 | int i; |
| 1168 | |
| 1169 | for (i = 0 ; table[i].type != AMD_BIOS_INVALID; i++) { |
| 1170 | if (table[i].level & BDT_LVL1 && table[i].filename) |
| 1171 | return 1; |
| 1172 | } |
| 1173 | return 0; |
| 1174 | } |
| 1175 | |
Marshall Dawson | c4a8c48 | 2020-01-21 17:17:59 -0700 | [diff] [blame] | 1176 | static int find_bios_entry(amd_bios_type type) |
| 1177 | { |
| 1178 | int i; |
| 1179 | |
| 1180 | for (i = 0; amd_bios_table[i].type != AMD_BIOS_INVALID; i++) { |
| 1181 | if (amd_bios_table[i].type == type) |
| 1182 | return i; |
| 1183 | } |
| 1184 | return -1; |
| 1185 | } |
| 1186 | |
Karthikeyan Ramasubramanian | 8d88561 | 2023-03-09 17:39:31 -0700 | [diff] [blame] | 1187 | static void add_bios_apcb_bk_entry(bios_directory_table *biosdir, unsigned int idx, |
| 1188 | int inst, uint32_t size, uint64_t source) |
| 1189 | { |
| 1190 | int i; |
| 1191 | |
| 1192 | for (i = 0; amd_bios_table[i].type != AMD_BIOS_INVALID; i++) { |
| 1193 | if (amd_bios_table[i].type == AMD_BIOS_APCB_BK && |
| 1194 | amd_bios_table[i].inst == inst) |
| 1195 | break; |
| 1196 | } |
| 1197 | |
| 1198 | if (amd_bios_table[i].type != AMD_BIOS_APCB_BK) |
| 1199 | return; |
| 1200 | |
| 1201 | biosdir->entries[idx].type = amd_bios_table[i].type; |
| 1202 | biosdir->entries[idx].region_type = amd_bios_table[i].region_type; |
| 1203 | biosdir->entries[idx].dest = amd_bios_table[i].dest ? |
| 1204 | amd_bios_table[i].dest : (uint64_t)-1; |
| 1205 | biosdir->entries[idx].reset = amd_bios_table[i].reset; |
| 1206 | biosdir->entries[idx].copy = amd_bios_table[i].copy; |
| 1207 | biosdir->entries[idx].ro = amd_bios_table[i].ro; |
| 1208 | biosdir->entries[idx].compressed = amd_bios_table[i].zlib; |
| 1209 | biosdir->entries[idx].inst = amd_bios_table[i].inst; |
| 1210 | biosdir->entries[idx].subprog = amd_bios_table[i].subpr; |
| 1211 | biosdir->entries[idx].size = size; |
| 1212 | biosdir->entries[idx].source = source; |
| 1213 | biosdir->entries[idx].address_mode = SET_ADDR_MODE_BY_TABLE(biosdir); |
| 1214 | } |
| 1215 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1216 | static void integrate_bios_firmwares(context *ctx, |
| 1217 | bios_directory_table *biosdir, |
| 1218 | bios_directory_table *biosdir2, |
| 1219 | amd_bios_entry *fw_table, |
Zheng Bao | 2079589 | 2021-08-20 14:58:22 +0800 | [diff] [blame] | 1220 | uint32_t cookie, |
| 1221 | amd_cb_config *cb_config) |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1222 | { |
| 1223 | ssize_t bytes; |
Martin Roth | ec93313 | 2019-07-13 20:03:34 -0600 | [diff] [blame] | 1224 | unsigned int i, count; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1225 | int level; |
Marshall Dawson | c4a8c48 | 2020-01-21 17:17:59 -0700 | [diff] [blame] | 1226 | int apob_idx; |
Martin Roth | eca423b | 2020-09-01 10:54:11 -0600 | [diff] [blame] | 1227 | uint32_t size; |
| 1228 | uint64_t source; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1229 | |
| 1230 | /* This function can create a primary table, a secondary table, or a |
| 1231 | * flattened table which contains all applicable types. These if-else |
| 1232 | * statements infer what the caller intended. If a 2nd-level cookie |
| 1233 | * is passed, clearly a 2nd-level table is intended. However, a |
| 1234 | * 1st-level cookie may indicate level 1 or flattened. If the caller |
| 1235 | * passes a pointer to a 2nd-level table, then assume not flat. |
| 1236 | */ |
Zheng Bao | ba3af5e | 2021-11-04 18:56:47 +0800 | [diff] [blame] | 1237 | if (!cb_config->multi_level) |
Zheng Bao | 2079589 | 2021-08-20 14:58:22 +0800 | [diff] [blame] | 1238 | level = BDT_BOTH; |
Zheng Bao | 96a3371 | 2021-06-11 15:54:40 +0800 | [diff] [blame] | 1239 | else if (cookie == BHDL2_COOKIE) |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1240 | level = BDT_LVL2; |
| 1241 | else if (biosdir2) |
| 1242 | level = BDT_LVL1; |
| 1243 | else |
| 1244 | level = BDT_BOTH; |
| 1245 | |
Zheng Bao | c26108f | 2023-02-17 11:01:07 +0800 | [diff] [blame] | 1246 | adjust_current_pointer(ctx, 0, TABLE_ALIGNMENT); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1247 | |
| 1248 | for (i = 0, count = 0; fw_table[i].type != AMD_BIOS_INVALID; i++) { |
| 1249 | if (!(fw_table[i].level & level)) |
| 1250 | continue; |
| 1251 | if (fw_table[i].filename == NULL && ( |
Ritul Guru | 9a321f3 | 2022-07-29 11:06:40 +0530 | [diff] [blame] | 1252 | fw_table[i].type != AMD_BIOS_SIG && |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1253 | fw_table[i].type != AMD_BIOS_APOB && |
| 1254 | fw_table[i].type != AMD_BIOS_APOB_NV && |
| 1255 | fw_table[i].type != AMD_BIOS_L2_PTR && |
Martin Roth | 9455474 | 2020-04-14 14:59:36 -0600 | [diff] [blame] | 1256 | fw_table[i].type != AMD_BIOS_BIN && |
| 1257 | fw_table[i].type != AMD_BIOS_PSP_SHARED_MEM)) |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1258 | continue; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1259 | |
| 1260 | /* BIOS Directory items may have additional requirements */ |
| 1261 | |
Ritul Guru | 9a321f3 | 2022-07-29 11:06:40 +0530 | [diff] [blame] | 1262 | /* SIG needs a size, else no choice but to skip */ |
| 1263 | if (fw_table[i].type == AMD_BIOS_SIG && !fw_table[i].size) |
| 1264 | continue; |
| 1265 | |
Martin Roth | 48dd9fe | 2020-07-29 16:32:25 -0600 | [diff] [blame] | 1266 | /* Check APOB_NV requirements */ |
| 1267 | if (fw_table[i].type == AMD_BIOS_APOB_NV) { |
| 1268 | if (!fw_table[i].size && !fw_table[i].src) |
| 1269 | continue; /* APOB_NV not used */ |
| 1270 | if (fw_table[i].src && !fw_table[i].size) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1271 | fprintf(stderr, "Error: APOB NV address provided, but no size\n"); |
Zheng Bao | 7c5ad88 | 2023-02-19 13:02:52 +0800 | [diff] [blame] | 1272 | amdfwtool_cleanup(ctx); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1273 | exit(1); |
| 1274 | } |
Martin Roth | 48dd9fe | 2020-07-29 16:32:25 -0600 | [diff] [blame] | 1275 | /* If the APOB isn't used, APOB_NV isn't used either */ |
Marshall Dawson | c4a8c48 | 2020-01-21 17:17:59 -0700 | [diff] [blame] | 1276 | apob_idx = find_bios_entry(AMD_BIOS_APOB); |
Martin Roth | 48dd9fe | 2020-07-29 16:32:25 -0600 | [diff] [blame] | 1277 | if (apob_idx < 0 || !fw_table[apob_idx].dest) |
| 1278 | continue; /* APOV NV not supported */ |
Marshall Dawson | c4a8c48 | 2020-01-21 17:17:59 -0700 | [diff] [blame] | 1279 | } |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1280 | |
| 1281 | /* APOB_DATA needs destination */ |
| 1282 | if (fw_table[i].type == AMD_BIOS_APOB && !fw_table[i].dest) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1283 | fprintf(stderr, "Error: APOB destination not provided\n"); |
Zheng Bao | 7c5ad88 | 2023-02-19 13:02:52 +0800 | [diff] [blame] | 1284 | amdfwtool_cleanup(ctx); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1285 | exit(1); |
| 1286 | } |
| 1287 | |
| 1288 | /* BIOS binary must have destination and uncompressed size. If |
| 1289 | * no filename given, then user must provide a source address. |
| 1290 | */ |
| 1291 | if (fw_table[i].type == AMD_BIOS_BIN) { |
| 1292 | if (!fw_table[i].dest || !fw_table[i].size) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1293 | fprintf(stderr, "Error: BIOS binary destination and uncompressed size are required\n"); |
Zheng Bao | 7c5ad88 | 2023-02-19 13:02:52 +0800 | [diff] [blame] | 1294 | amdfwtool_cleanup(ctx); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1295 | exit(1); |
| 1296 | } |
| 1297 | if (!fw_table[i].filename && !fw_table[i].src) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1298 | fprintf(stderr, "Error: BIOS binary assumed outside amdfw.rom but no source address given\n"); |
Zheng Bao | 7c5ad88 | 2023-02-19 13:02:52 +0800 | [diff] [blame] | 1299 | amdfwtool_cleanup(ctx); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1300 | exit(1); |
| 1301 | } |
| 1302 | } |
| 1303 | |
Martin Roth | 9455474 | 2020-04-14 14:59:36 -0600 | [diff] [blame] | 1304 | /* PSP_SHARED_MEM needs a destination and size */ |
| 1305 | if (fw_table[i].type == AMD_BIOS_PSP_SHARED_MEM && |
| 1306 | (!fw_table[i].dest || !fw_table[i].size)) |
| 1307 | continue; |
Zheng Bao | 5164e4b | 2021-10-30 12:09:07 +0800 | [diff] [blame] | 1308 | assert_fw_entry(count, MAX_BIOS_ENTRIES, ctx); |
Martin Roth | 9455474 | 2020-04-14 14:59:36 -0600 | [diff] [blame] | 1309 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1310 | biosdir->entries[count].type = fw_table[i].type; |
| 1311 | biosdir->entries[count].region_type = fw_table[i].region_type; |
| 1312 | biosdir->entries[count].dest = fw_table[i].dest ? |
| 1313 | fw_table[i].dest : (uint64_t)-1; |
| 1314 | biosdir->entries[count].reset = fw_table[i].reset; |
| 1315 | biosdir->entries[count].copy = fw_table[i].copy; |
| 1316 | biosdir->entries[count].ro = fw_table[i].ro; |
| 1317 | biosdir->entries[count].compressed = fw_table[i].zlib; |
| 1318 | biosdir->entries[count].inst = fw_table[i].inst; |
| 1319 | biosdir->entries[count].subprog = fw_table[i].subpr; |
| 1320 | |
| 1321 | switch (fw_table[i].type) { |
Ritul Guru | 9a321f3 | 2022-07-29 11:06:40 +0530 | [diff] [blame] | 1322 | case AMD_BIOS_SIG: |
| 1323 | /* Reserve size bytes within amdfw.rom */ |
| 1324 | biosdir->entries[count].size = fw_table[i].size; |
| 1325 | biosdir->entries[count].source = RUN_CURRENT(*ctx); |
| 1326 | biosdir->entries[count].address_mode = |
| 1327 | SET_ADDR_MODE_BY_TABLE(biosdir); |
| 1328 | memset(BUFF_CURRENT(*ctx), 0xff, |
| 1329 | biosdir->entries[count].size); |
Zheng Bao | c26108f | 2023-02-17 11:01:07 +0800 | [diff] [blame] | 1330 | adjust_current_pointer(ctx, biosdir->entries[count].size, 0x100U); |
Ritul Guru | 9a321f3 | 2022-07-29 11:06:40 +0530 | [diff] [blame] | 1331 | break; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1332 | case AMD_BIOS_APOB: |
| 1333 | biosdir->entries[count].size = fw_table[i].size; |
| 1334 | biosdir->entries[count].source = fw_table[i].src; |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1335 | biosdir->entries[count].address_mode = SET_ADDR_MODE_BY_TABLE(biosdir); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1336 | break; |
| 1337 | case AMD_BIOS_APOB_NV: |
| 1338 | if (fw_table[i].src) { |
| 1339 | /* If source is given, use that and its size */ |
| 1340 | biosdir->entries[count].source = fw_table[i].src; |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1341 | biosdir->entries[count].address_mode = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 1342 | SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1343 | biosdir->entries[count].size = fw_table[i].size; |
| 1344 | } else { |
| 1345 | /* Else reserve size bytes within amdfw.rom */ |
Zheng Bao | c26108f | 2023-02-17 11:01:07 +0800 | [diff] [blame] | 1346 | adjust_current_pointer(ctx, 0, ERASE_ALIGNMENT); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1347 | biosdir->entries[count].source = RUN_CURRENT(*ctx); |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1348 | biosdir->entries[count].address_mode = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 1349 | SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS); |
Elyes Haouas | 7d67a19 | 2022-10-14 09:58:29 +0200 | [diff] [blame] | 1350 | biosdir->entries[count].size = ALIGN_UP( |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1351 | fw_table[i].size, ERASE_ALIGNMENT); |
| 1352 | memset(BUFF_CURRENT(*ctx), 0xff, |
| 1353 | biosdir->entries[count].size); |
Zheng Bao | c26108f | 2023-02-17 11:01:07 +0800 | [diff] [blame] | 1354 | adjust_current_pointer(ctx, biosdir->entries[count].size, 1); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1355 | } |
| 1356 | break; |
| 1357 | case AMD_BIOS_BIN: |
| 1358 | /* Don't make a 2nd copy, point to the same one */ |
Martin Roth | eca423b | 2020-09-01 10:54:11 -0600 | [diff] [blame] | 1359 | if (level == BDT_LVL1 && locate_bdt2_bios(biosdir2, &source, &size)) { |
| 1360 | biosdir->entries[count].source = source; |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1361 | biosdir->entries[count].address_mode = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 1362 | SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS); |
Martin Roth | eca423b | 2020-09-01 10:54:11 -0600 | [diff] [blame] | 1363 | biosdir->entries[count].size = size; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1364 | break; |
Martin Roth | eca423b | 2020-09-01 10:54:11 -0600 | [diff] [blame] | 1365 | } |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1366 | |
| 1367 | /* level 2, or level 1 and no copy found in level 2 */ |
| 1368 | biosdir->entries[count].source = fw_table[i].src; |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1369 | biosdir->entries[count].address_mode = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 1370 | SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1371 | biosdir->entries[count].dest = fw_table[i].dest; |
| 1372 | biosdir->entries[count].size = fw_table[i].size; |
| 1373 | |
| 1374 | if (!fw_table[i].filename) |
| 1375 | break; |
| 1376 | |
| 1377 | bytes = copy_blob(BUFF_CURRENT(*ctx), |
| 1378 | fw_table[i].filename, BUFF_ROOM(*ctx)); |
| 1379 | if (bytes <= 0) { |
Zheng Bao | 7c5ad88 | 2023-02-19 13:02:52 +0800 | [diff] [blame] | 1380 | amdfwtool_cleanup(ctx); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1381 | exit(1); |
| 1382 | } |
| 1383 | |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1384 | biosdir->entries[count].source = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 1385 | RUN_CURRENT_MODE(*ctx, AMD_ADDR_REL_BIOS); |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1386 | biosdir->entries[count].address_mode = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 1387 | SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1388 | |
Zheng Bao | c26108f | 2023-02-17 11:01:07 +0800 | [diff] [blame] | 1389 | adjust_current_pointer(ctx, bytes, 0x100U); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1390 | break; |
Martin Roth | 9455474 | 2020-04-14 14:59:36 -0600 | [diff] [blame] | 1391 | case AMD_BIOS_PSP_SHARED_MEM: |
| 1392 | biosdir->entries[count].dest = fw_table[i].dest; |
| 1393 | biosdir->entries[count].size = fw_table[i].size; |
| 1394 | break; |
| 1395 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1396 | default: /* everything else is copied from input */ |
| 1397 | if (fw_table[i].type == AMD_BIOS_APCB || |
| 1398 | fw_table[i].type == AMD_BIOS_APCB_BK) |
Zheng Bao | c26108f | 2023-02-17 11:01:07 +0800 | [diff] [blame] | 1399 | adjust_current_pointer(ctx, 0, ERASE_ALIGNMENT); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1400 | bytes = copy_blob(BUFF_CURRENT(*ctx), |
| 1401 | fw_table[i].filename, BUFF_ROOM(*ctx)); |
| 1402 | if (bytes <= 0) { |
Zheng Bao | 7c5ad88 | 2023-02-19 13:02:52 +0800 | [diff] [blame] | 1403 | amdfwtool_cleanup(ctx); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1404 | exit(1); |
| 1405 | } |
| 1406 | |
| 1407 | biosdir->entries[count].size = (uint32_t)bytes; |
| 1408 | biosdir->entries[count].source = RUN_CURRENT(*ctx); |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1409 | biosdir->entries[count].address_mode = SET_ADDR_MODE_BY_TABLE(biosdir); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1410 | |
Zheng Bao | c26108f | 2023-02-17 11:01:07 +0800 | [diff] [blame] | 1411 | adjust_current_pointer(ctx, bytes, 0x100U); |
Karthikeyan Ramasubramanian | 8d88561 | 2023-03-09 17:39:31 -0700 | [diff] [blame] | 1412 | if (fw_table[i].type == AMD_BIOS_APCB && !cb_config->have_apcb_bk) { |
| 1413 | size = biosdir->entries[count].size; |
| 1414 | source = biosdir->entries[count].source; |
| 1415 | count++; |
| 1416 | add_bios_apcb_bk_entry(biosdir, count, fw_table[i].inst, size, source); |
| 1417 | } |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1418 | break; |
| 1419 | } |
| 1420 | |
| 1421 | count++; |
| 1422 | } |
| 1423 | |
| 1424 | if (biosdir2) { |
Zheng Bao | 5164e4b | 2021-10-30 12:09:07 +0800 | [diff] [blame] | 1425 | assert_fw_entry(count, MAX_BIOS_ENTRIES, ctx); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1426 | biosdir->entries[count].type = AMD_BIOS_L2_PTR; |
Zheng Bao | e8e6043 | 2021-05-24 16:11:12 +0800 | [diff] [blame] | 1427 | biosdir->entries[count].region_type = 0; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1428 | biosdir->entries[count].size = |
| 1429 | + MAX_BIOS_ENTRIES |
| 1430 | * sizeof(bios_directory_entry); |
| 1431 | biosdir->entries[count].source = |
| 1432 | BUFF_TO_RUN(*ctx, biosdir2); |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1433 | biosdir->entries[count].address_mode = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 1434 | SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1435 | biosdir->entries[count].subprog = 0; |
| 1436 | biosdir->entries[count].inst = 0; |
| 1437 | biosdir->entries[count].copy = 0; |
| 1438 | biosdir->entries[count].compressed = 0; |
| 1439 | biosdir->entries[count].dest = -1; |
| 1440 | biosdir->entries[count].reset = 0; |
| 1441 | biosdir->entries[count].ro = 0; |
| 1442 | count++; |
| 1443 | } |
| 1444 | |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 1445 | fill_dir_header(biosdir, count, cookie, ctx); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1446 | } |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1447 | |
| 1448 | enum { |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1449 | AMDFW_OPT_CONFIG = 'c', |
| 1450 | AMDFW_OPT_DEBUG = 'd', |
| 1451 | AMDFW_OPT_HELP = 'h', |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1452 | |
| 1453 | AMDFW_OPT_XHCI = 128, |
| 1454 | AMDFW_OPT_IMC, |
| 1455 | AMDFW_OPT_GEC, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1456 | AMDFW_OPT_RECOVERY_AB, |
Karthikeyan Ramasubramanian | ad06bae | 2022-04-08 14:19:55 -0600 | [diff] [blame] | 1457 | AMDFW_OPT_RECOVERY_AB_SINGLE_COPY, |
Zheng Bao | 993b43f | 2021-11-10 12:21:46 +0800 | [diff] [blame] | 1458 | AMDFW_OPT_USE_COMBO, |
Zheng Bao | 0e3d18b | 2023-03-07 15:28:57 +0800 | [diff] [blame] | 1459 | AMDFW_OPT_COMBO1_CONFIG, |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1460 | AMDFW_OPT_MULTILEVEL, |
| 1461 | AMDFW_OPT_NVRAM, |
| 1462 | |
| 1463 | AMDFW_OPT_FUSE, |
| 1464 | AMDFW_OPT_UNLOCK, |
| 1465 | AMDFW_OPT_WHITELIST, |
| 1466 | AMDFW_OPT_USE_PSPSECUREOS, |
| 1467 | AMDFW_OPT_LOAD_MP2FW, |
| 1468 | AMDFW_OPT_LOAD_S0I3, |
Zheng Bao | 6c5ec8e | 2022-02-11 11:51:26 +0800 | [diff] [blame] | 1469 | AMDFW_OPT_SPL_TABLE, |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1470 | AMDFW_OPT_VERSTAGE, |
| 1471 | AMDFW_OPT_VERSTAGE_SIG, |
| 1472 | |
| 1473 | AMDFW_OPT_INSTANCE, |
| 1474 | AMDFW_OPT_APCB, |
| 1475 | AMDFW_OPT_APOBBASE, |
| 1476 | AMDFW_OPT_BIOSBIN, |
| 1477 | AMDFW_OPT_BIOSBIN_SOURCE, |
| 1478 | AMDFW_OPT_BIOSBIN_DEST, |
| 1479 | AMDFW_OPT_BIOS_UNCOMP_SIZE, |
Karthikeyan Ramasubramanian | bd9dd42 | 2022-12-22 15:45:56 -0700 | [diff] [blame] | 1480 | AMDFW_OPT_BIOSBIN_UNCOMP, |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1481 | AMDFW_OPT_UCODE, |
| 1482 | AMDFW_OPT_APOB_NVBASE, |
| 1483 | AMDFW_OPT_APOB_NVSIZE, |
| 1484 | |
| 1485 | AMDFW_OPT_OUTPUT, |
| 1486 | AMDFW_OPT_FLASHSIZE, |
| 1487 | AMDFW_OPT_LOCATION, |
| 1488 | AMDFW_OPT_ANYWHERE, |
| 1489 | AMDFW_OPT_SHAREDMEM, |
| 1490 | AMDFW_OPT_SHAREDMEM_SIZE, |
Kangheui Won | 3c164e1 | 2021-12-03 20:25:05 +1100 | [diff] [blame] | 1491 | AMDFW_OPT_SIGNED_OUTPUT, |
| 1492 | AMDFW_OPT_SIGNED_ADDR, |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 1493 | AMDFW_OPT_BODY_LOCATION, |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1494 | /* begin after ASCII characters */ |
| 1495 | LONGOPT_SPI_READ_MODE = 256, |
| 1496 | LONGOPT_SPI_SPEED = 257, |
| 1497 | LONGOPT_SPI_MICRON_FLAG = 258, |
Ritul Guru | 9a321f3 | 2022-07-29 11:06:40 +0530 | [diff] [blame] | 1498 | LONGOPT_BIOS_SIG = 259, |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 1499 | LONGOPT_NVRAM_BASE = 260, |
| 1500 | LONGOPT_NVRAM_SIZE = 261, |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1501 | }; |
| 1502 | |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1503 | static char const optstring[] = {AMDFW_OPT_CONFIG, ':', |
Zheng Bao | 994ff52 | 2023-03-09 11:43:55 +0800 | [diff] [blame] | 1504 | AMDFW_OPT_DEBUG, AMDFW_OPT_HELP |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1505 | }; |
Marc Jones | 90099b6 | 2016-09-20 21:05:45 -0600 | [diff] [blame] | 1506 | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1507 | static struct option long_options[] = { |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1508 | {"xhci", required_argument, 0, AMDFW_OPT_XHCI }, |
| 1509 | {"imc", required_argument, 0, AMDFW_OPT_IMC }, |
| 1510 | {"gec", required_argument, 0, AMDFW_OPT_GEC }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1511 | /* PSP Directory Table items */ |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1512 | {"recovery-ab", no_argument, 0, AMDFW_OPT_RECOVERY_AB }, |
Karthikeyan Ramasubramanian | ad06bae | 2022-04-08 14:19:55 -0600 | [diff] [blame] | 1513 | {"recovery-ab-single-copy", no_argument, 0, AMDFW_OPT_RECOVERY_AB_SINGLE_COPY }, |
Zheng Bao | 993b43f | 2021-11-10 12:21:46 +0800 | [diff] [blame] | 1514 | {"use-combo", no_argument, 0, AMDFW_OPT_USE_COMBO }, |
Zheng Bao | 0e3d18b | 2023-03-07 15:28:57 +0800 | [diff] [blame] | 1515 | {"combo-config1", required_argument, 0, AMDFW_OPT_COMBO1_CONFIG }, |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1516 | {"multilevel", no_argument, 0, AMDFW_OPT_MULTILEVEL }, |
| 1517 | {"nvram", required_argument, 0, AMDFW_OPT_NVRAM }, |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 1518 | {"nvram-base", required_argument, 0, LONGOPT_NVRAM_BASE }, |
| 1519 | {"nvram-size", required_argument, 0, LONGOPT_NVRAM_SIZE }, |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1520 | {"soft-fuse", required_argument, 0, AMDFW_OPT_FUSE }, |
| 1521 | {"token-unlock", no_argument, 0, AMDFW_OPT_UNLOCK }, |
| 1522 | {"whitelist", required_argument, 0, AMDFW_OPT_WHITELIST }, |
| 1523 | {"use-pspsecureos", no_argument, 0, AMDFW_OPT_USE_PSPSECUREOS }, |
| 1524 | {"load-mp2-fw", no_argument, 0, AMDFW_OPT_LOAD_MP2FW }, |
| 1525 | {"load-s0i3", no_argument, 0, AMDFW_OPT_LOAD_S0I3 }, |
Zheng Bao | 6c5ec8e | 2022-02-11 11:51:26 +0800 | [diff] [blame] | 1526 | {"spl-table", required_argument, 0, AMDFW_OPT_SPL_TABLE }, |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1527 | {"verstage", required_argument, 0, AMDFW_OPT_VERSTAGE }, |
| 1528 | {"verstage_sig", required_argument, 0, AMDFW_OPT_VERSTAGE_SIG }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1529 | /* BIOS Directory Table items */ |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1530 | {"instance", required_argument, 0, AMDFW_OPT_INSTANCE }, |
| 1531 | {"apcb", required_argument, 0, AMDFW_OPT_APCB }, |
| 1532 | {"apob-base", required_argument, 0, AMDFW_OPT_APOBBASE }, |
| 1533 | {"bios-bin", required_argument, 0, AMDFW_OPT_BIOSBIN }, |
| 1534 | {"bios-bin-src", required_argument, 0, AMDFW_OPT_BIOSBIN_SOURCE }, |
| 1535 | {"bios-bin-dest", required_argument, 0, AMDFW_OPT_BIOSBIN_DEST }, |
| 1536 | {"bios-uncomp-size", required_argument, 0, AMDFW_OPT_BIOS_UNCOMP_SIZE }, |
Karthikeyan Ramasubramanian | bd9dd42 | 2022-12-22 15:45:56 -0700 | [diff] [blame] | 1537 | {"bios-bin-uncomp", no_argument, 0, AMDFW_OPT_BIOSBIN_UNCOMP }, |
Ritul Guru | 9a321f3 | 2022-07-29 11:06:40 +0530 | [diff] [blame] | 1538 | {"bios-sig-size", required_argument, 0, LONGOPT_BIOS_SIG }, |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1539 | {"ucode", required_argument, 0, AMDFW_OPT_UCODE }, |
| 1540 | {"apob-nv-base", required_argument, 0, AMDFW_OPT_APOB_NVBASE }, |
| 1541 | {"apob-nv-size", required_argument, 0, AMDFW_OPT_APOB_NVSIZE }, |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1542 | /* Embedded Firmware Structure items*/ |
| 1543 | {"spi-read-mode", required_argument, 0, LONGOPT_SPI_READ_MODE }, |
| 1544 | {"spi-speed", required_argument, 0, LONGOPT_SPI_SPEED }, |
| 1545 | {"spi-micron-flag", required_argument, 0, LONGOPT_SPI_MICRON_FLAG }, |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 1546 | {"body-location", required_argument, 0, AMDFW_OPT_BODY_LOCATION }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1547 | /* other */ |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1548 | {"output", required_argument, 0, AMDFW_OPT_OUTPUT }, |
| 1549 | {"flashsize", required_argument, 0, AMDFW_OPT_FLASHSIZE }, |
| 1550 | {"location", required_argument, 0, AMDFW_OPT_LOCATION }, |
| 1551 | {"anywhere", no_argument, 0, AMDFW_OPT_ANYWHERE }, |
| 1552 | {"sharedmem", required_argument, 0, AMDFW_OPT_SHAREDMEM }, |
| 1553 | {"sharedmem-size", required_argument, 0, AMDFW_OPT_SHAREDMEM_SIZE }, |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1554 | |
Kangheui Won | 3c164e1 | 2021-12-03 20:25:05 +1100 | [diff] [blame] | 1555 | {"signed-output", required_argument, 0, AMDFW_OPT_SIGNED_OUTPUT }, |
| 1556 | {"signed-addr", required_argument, 0, AMDFW_OPT_SIGNED_ADDR }, |
| 1557 | |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1558 | {"config", required_argument, 0, AMDFW_OPT_CONFIG }, |
| 1559 | {"debug", no_argument, 0, AMDFW_OPT_DEBUG }, |
| 1560 | {"help", no_argument, 0, AMDFW_OPT_HELP }, |
Marshall Dawson | f4b9b41 | 2017-03-17 16:30:51 -0600 | [diff] [blame] | 1561 | {NULL, 0, 0, 0 } |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1562 | }; |
| 1563 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1564 | void register_fw_fuse(char *str) |
Marshall Dawson | ef79fcc | 2019-04-01 10:16:41 -0600 | [diff] [blame] | 1565 | { |
Zheng Bao | 6d402ac | 2020-10-01 16:16:30 +0800 | [diff] [blame] | 1566 | uint32_t i; |
Marshall Dawson | ef79fcc | 2019-04-01 10:16:41 -0600 | [diff] [blame] | 1567 | |
| 1568 | for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) { |
| 1569 | if (amd_psp_fw_table[i].type != AMD_PSP_FUSE_CHAIN) |
| 1570 | continue; |
| 1571 | |
| 1572 | amd_psp_fw_table[i].other = strtoull(str, NULL, 16); |
| 1573 | return; |
| 1574 | } |
| 1575 | } |
| 1576 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1577 | static void register_fw_token_unlock(void) |
| 1578 | { |
Zheng Bao | 6d402ac | 2020-10-01 16:16:30 +0800 | [diff] [blame] | 1579 | uint32_t i; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1580 | |
| 1581 | for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) { |
| 1582 | if (amd_psp_fw_table[i].type != AMD_TOKEN_UNLOCK) |
| 1583 | continue; |
| 1584 | |
| 1585 | amd_psp_fw_table[i].other = 1; |
| 1586 | return; |
| 1587 | } |
| 1588 | } |
| 1589 | |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1590 | static void register_fw_filename(amd_fw_type type, uint8_t sub, char filename[]) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1591 | { |
Martin Roth | 8806f7f | 2016-11-08 10:44:18 -0700 | [diff] [blame] | 1592 | unsigned int i; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1593 | |
Martin Roth | cd15bc8 | 2016-11-08 11:34:02 -0700 | [diff] [blame] | 1594 | for (i = 0; i < sizeof(amd_fw_table) / sizeof(amd_fw_entry); i++) { |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1595 | if (amd_fw_table[i].type == type) { |
| 1596 | amd_fw_table[i].filename = filename; |
| 1597 | return; |
| 1598 | } |
| 1599 | } |
| 1600 | |
Marshall Dawson | 0e02ce8 | 2019-03-04 16:50:37 -0700 | [diff] [blame] | 1601 | for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) { |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1602 | if (amd_psp_fw_table[i].type != type) |
| 1603 | continue; |
| 1604 | |
| 1605 | if (amd_psp_fw_table[i].subprog == sub) { |
Marshall Dawson | 0e02ce8 | 2019-03-04 16:50:37 -0700 | [diff] [blame] | 1606 | amd_psp_fw_table[i].filename = filename; |
| 1607 | return; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1608 | } |
| 1609 | } |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1610 | } |
| 1611 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1612 | static void register_bdt_data(amd_bios_type type, int sub, int ins, char name[]) |
| 1613 | { |
Zheng Bao | 6d402ac | 2020-10-01 16:16:30 +0800 | [diff] [blame] | 1614 | uint32_t i; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1615 | |
| 1616 | for (i = 0; i < sizeof(amd_bios_table) / sizeof(amd_bios_entry); i++) { |
| 1617 | if (amd_bios_table[i].type == type |
| 1618 | && amd_bios_table[i].inst == ins |
| 1619 | && amd_bios_table[i].subpr == sub) { |
| 1620 | amd_bios_table[i].filename = name; |
| 1621 | return; |
| 1622 | } |
| 1623 | } |
| 1624 | } |
| 1625 | |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 1626 | static void register_amd_psp_fw_addr(amd_fw_type type, int sub, |
| 1627 | char *dst_str, char *size_str) |
| 1628 | { |
| 1629 | unsigned int i; |
| 1630 | |
| 1631 | for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) { |
| 1632 | if (amd_psp_fw_table[i].type != type) |
| 1633 | continue; |
| 1634 | |
| 1635 | if (amd_psp_fw_table[i].subprog == sub) { |
| 1636 | if (dst_str) |
| 1637 | amd_psp_fw_table[i].dest = strtoull(dst_str, NULL, 16); |
| 1638 | if (size_str) |
| 1639 | amd_psp_fw_table[i].size = strtoul(size_str, NULL, 16); |
| 1640 | return; |
| 1641 | } |
| 1642 | } |
| 1643 | } |
| 1644 | |
| 1645 | static void register_bios_fw_addr(amd_bios_type type, char *src_str, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1646 | char *dst_str, char *size_str) |
| 1647 | { |
Zheng Bao | 6d402ac | 2020-10-01 16:16:30 +0800 | [diff] [blame] | 1648 | uint32_t i; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1649 | for (i = 0; i < sizeof(amd_bios_table) / sizeof(amd_bios_entry); i++) { |
| 1650 | if (amd_bios_table[i].type != type) |
| 1651 | continue; |
| 1652 | |
| 1653 | if (src_str) |
| 1654 | amd_bios_table[i].src = strtoull(src_str, NULL, 16); |
| 1655 | if (dst_str) |
| 1656 | amd_bios_table[i].dest = strtoull(dst_str, NULL, 16); |
| 1657 | if (size_str) |
| 1658 | amd_bios_table[i].size = strtoul(size_str, NULL, 16); |
| 1659 | |
| 1660 | return; |
| 1661 | } |
| 1662 | } |
| 1663 | |
Zheng Bao | c3007f3 | 2022-04-03 12:53:51 +0800 | [diff] [blame] | 1664 | static int set_efs_table(uint8_t soc_id, amd_cb_config *cb_config, |
| 1665 | embedded_firmware *amd_romsig, uint8_t efs_spi_readmode, |
| 1666 | uint8_t efs_spi_speed, uint8_t efs_spi_micron_flag) |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1667 | { |
| 1668 | if ((efs_spi_readmode == 0xFF) || (efs_spi_speed == 0xFF)) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1669 | fprintf(stderr, "Error: EFS read mode and SPI speed must be set\n"); |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1670 | return 1; |
| 1671 | } |
Zheng Bao | c3007f3 | 2022-04-03 12:53:51 +0800 | [diff] [blame] | 1672 | |
| 1673 | /* amd_romsig->efs_gen introduced after RAVEN/PICASSO. |
| 1674 | * Leave as 0xffffffff for first gen */ |
| 1675 | if (cb_config->second_gen) { |
| 1676 | amd_romsig->efs_gen.gen = EFS_SECOND_GEN; |
| 1677 | amd_romsig->efs_gen.reserved = 0; |
| 1678 | } else { |
Zheng Bao | 487d045 | 2022-04-03 12:50:07 +0800 | [diff] [blame] | 1679 | amd_romsig->efs_gen.gen = EFS_BEFORE_SECOND_GEN; |
| 1680 | amd_romsig->efs_gen.reserved = ~0; |
Zheng Bao | c3007f3 | 2022-04-03 12:53:51 +0800 | [diff] [blame] | 1681 | } |
| 1682 | |
| 1683 | switch (soc_id) { |
Zheng Bao | 3d7623f | 2022-08-17 11:52:30 +0800 | [diff] [blame] | 1684 | case PLATFORM_CARRIZO: |
Zheng Bao | c3007f3 | 2022-04-03 12:53:51 +0800 | [diff] [blame] | 1685 | case PLATFORM_STONEYRIDGE: |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1686 | amd_romsig->spi_readmode_f15_mod_60_6f = efs_spi_readmode; |
| 1687 | amd_romsig->fast_speed_new_f15_mod_60_6f = efs_spi_speed; |
| 1688 | break; |
| 1689 | case PLATFORM_RAVEN: |
| 1690 | case PLATFORM_PICASSO: |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1691 | amd_romsig->spi_readmode_f17_mod_00_2f = efs_spi_readmode; |
| 1692 | amd_romsig->spi_fastspeed_f17_mod_00_2f = efs_spi_speed; |
| 1693 | switch (efs_spi_micron_flag) { |
| 1694 | case 0: |
| 1695 | amd_romsig->qpr_dummy_cycle_f17_mod_00_2f = 0xff; |
| 1696 | break; |
| 1697 | case 1: |
| 1698 | amd_romsig->qpr_dummy_cycle_f17_mod_00_2f = 0xa; |
| 1699 | break; |
| 1700 | default: |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1701 | fprintf(stderr, "Error: EFS Micron flag must be correctly set.\n\n"); |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1702 | return 1; |
| 1703 | } |
| 1704 | break; |
| 1705 | case PLATFORM_RENOIR: |
| 1706 | case PLATFORM_LUCIENNE: |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 1707 | case PLATFORM_CEZANNE: |
Zheng Bao | 535ec53 | 2021-08-12 16:30:19 +0800 | [diff] [blame] | 1708 | case PLATFORM_MENDOCINO: |
Zheng Bao | de6f198 | 2022-10-16 20:32:43 +0800 | [diff] [blame] | 1709 | case PLATFORM_PHOENIX: |
| 1710 | case PLATFORM_GLINDA: |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1711 | amd_romsig->spi_readmode_f17_mod_30_3f = efs_spi_readmode; |
| 1712 | amd_romsig->spi_fastspeed_f17_mod_30_3f = efs_spi_speed; |
| 1713 | switch (efs_spi_micron_flag) { |
| 1714 | case 0: |
| 1715 | amd_romsig->micron_detect_f17_mod_30_3f = 0xff; |
| 1716 | break; |
| 1717 | case 1: |
| 1718 | amd_romsig->micron_detect_f17_mod_30_3f = 0xaa; |
| 1719 | break; |
| 1720 | case 2: |
| 1721 | amd_romsig->micron_detect_f17_mod_30_3f = 0x55; |
| 1722 | break; |
| 1723 | default: |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1724 | fprintf(stderr, "Error: EFS Micron flag must be correctly set.\n\n"); |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1725 | return 1; |
| 1726 | } |
| 1727 | break; |
| 1728 | case PLATFORM_UNKNOWN: |
| 1729 | default: |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1730 | fprintf(stderr, "Error: Invalid SOC name.\n\n"); |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1731 | return 1; |
| 1732 | } |
| 1733 | return 0; |
| 1734 | } |
| 1735 | |
Zheng Bao | 69ea83c | 2023-01-22 21:08:18 +0800 | [diff] [blame] | 1736 | static ssize_t write_body(char *output, void *body_offset, ssize_t body_size, context *ctx) |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 1737 | { |
Zheng Bao | 69ea83c | 2023-01-22 21:08:18 +0800 | [diff] [blame] | 1738 | char body_name[PATH_MAX], body_tmp_name[PATH_MAX]; |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 1739 | int ret; |
| 1740 | int fd; |
| 1741 | ssize_t bytes = -1; |
| 1742 | |
| 1743 | /* Create a tmp file and rename it at the end so that make does not get confused |
| 1744 | if amdfwtool is killed for some unexpected reasons. */ |
Zheng Bao | 69ea83c | 2023-01-22 21:08:18 +0800 | [diff] [blame] | 1745 | ret = snprintf(body_tmp_name, sizeof(body_tmp_name), "%s%s%s", |
| 1746 | output, BODY_FILE_SUFFIX, TMP_FILE_SUFFIX); |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 1747 | if (ret < 0) { |
Zheng Bao | 69ea83c | 2023-01-22 21:08:18 +0800 | [diff] [blame] | 1748 | fprintf(stderr, "Error %s forming BODY tmp file name: %d\n", |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 1749 | strerror(errno), ret); |
Zheng Bao | 7c5ad88 | 2023-02-19 13:02:52 +0800 | [diff] [blame] | 1750 | amdfwtool_cleanup(ctx); |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 1751 | exit(1); |
Zheng Bao | 69ea83c | 2023-01-22 21:08:18 +0800 | [diff] [blame] | 1752 | } else if ((unsigned int)ret >= sizeof(body_tmp_name)) { |
| 1753 | fprintf(stderr, "BODY File name %d > %zu\n", ret, sizeof(body_tmp_name)); |
Zheng Bao | 7c5ad88 | 2023-02-19 13:02:52 +0800 | [diff] [blame] | 1754 | amdfwtool_cleanup(ctx); |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 1755 | exit(1); |
| 1756 | } |
| 1757 | |
Zheng Bao | 69ea83c | 2023-01-22 21:08:18 +0800 | [diff] [blame] | 1758 | fd = open(body_tmp_name, O_RDWR | O_CREAT | O_TRUNC, 0666); |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 1759 | if (fd < 0) { |
Zheng Bao | 69ea83c | 2023-01-22 21:08:18 +0800 | [diff] [blame] | 1760 | fprintf(stderr, "Error: Opening %s file: %s\n", body_tmp_name, strerror(errno)); |
Zheng Bao | 7c5ad88 | 2023-02-19 13:02:52 +0800 | [diff] [blame] | 1761 | amdfwtool_cleanup(ctx); |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 1762 | exit(1); |
| 1763 | } |
| 1764 | |
Zheng Bao | 69ea83c | 2023-01-22 21:08:18 +0800 | [diff] [blame] | 1765 | bytes = write_from_buf_to_file(fd, body_offset, body_size); |
| 1766 | if (bytes != body_size) { |
| 1767 | fprintf(stderr, "Error: Writing to file %s failed\n", body_tmp_name); |
Zheng Bao | 7c5ad88 | 2023-02-19 13:02:52 +0800 | [diff] [blame] | 1768 | amdfwtool_cleanup(ctx); |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 1769 | exit(1); |
| 1770 | } |
| 1771 | close(fd); |
| 1772 | |
| 1773 | /* Rename the tmp file */ |
Zheng Bao | 69ea83c | 2023-01-22 21:08:18 +0800 | [diff] [blame] | 1774 | ret = snprintf(body_name, sizeof(body_name), "%s%s", output, BODY_FILE_SUFFIX); |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 1775 | if (ret < 0) { |
Zheng Bao | 69ea83c | 2023-01-22 21:08:18 +0800 | [diff] [blame] | 1776 | fprintf(stderr, "Error %s forming BODY file name: %d\n", strerror(errno), ret); |
Zheng Bao | 7c5ad88 | 2023-02-19 13:02:52 +0800 | [diff] [blame] | 1777 | amdfwtool_cleanup(ctx); |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 1778 | exit(1); |
| 1779 | } |
| 1780 | |
Zheng Bao | 69ea83c | 2023-01-22 21:08:18 +0800 | [diff] [blame] | 1781 | if (rename(body_tmp_name, body_name)) { |
| 1782 | fprintf(stderr, "Error: renaming file %s to %s\n", body_tmp_name, body_name); |
Zheng Bao | 7c5ad88 | 2023-02-19 13:02:52 +0800 | [diff] [blame] | 1783 | amdfwtool_cleanup(ctx); |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 1784 | exit(1); |
| 1785 | } |
| 1786 | |
| 1787 | return bytes; |
| 1788 | } |
| 1789 | |
Zheng Bao | 994ff52 | 2023-03-09 11:43:55 +0800 | [diff] [blame] | 1790 | void open_process_config(char *config, amd_cb_config *cb_config, int debug) |
Zheng Bao | 39cae56 | 2023-03-07 18:37:43 +0800 | [diff] [blame] | 1791 | { |
| 1792 | FILE *config_handle; |
| 1793 | |
| 1794 | if (config) { |
| 1795 | config_handle = fopen(config, "r"); |
| 1796 | if (config_handle == NULL) { |
| 1797 | fprintf(stderr, "Can not open file %s for reading: %s\n", |
| 1798 | config, strerror(errno)); |
| 1799 | exit(1); |
| 1800 | } |
Zheng Bao | 994ff52 | 2023-03-09 11:43:55 +0800 | [diff] [blame] | 1801 | if (process_config(config_handle, cb_config) == 0) { |
Zheng Bao | 39cae56 | 2023-03-07 18:37:43 +0800 | [diff] [blame] | 1802 | fprintf(stderr, "Configuration file %s parsing error\n", |
| 1803 | config); |
| 1804 | fclose(config_handle); |
| 1805 | exit(1); |
| 1806 | } |
| 1807 | fclose(config_handle); |
| 1808 | } |
| 1809 | |
| 1810 | /* For debug. */ |
| 1811 | if (debug) { |
| 1812 | dump_psp_firmwares(amd_psp_fw_table); |
| 1813 | dump_bdt_firmwares(amd_bios_table); |
| 1814 | } |
| 1815 | } |
| 1816 | |
Karthikeyan Ramasubramanian | 225b4b3 | 2023-03-08 10:24:50 -0700 | [diff] [blame] | 1817 | static bool is_initial_alignment_required(enum platform soc_id) |
| 1818 | { |
| 1819 | switch (soc_id) { |
| 1820 | case PLATFORM_MENDOCINO: |
| 1821 | case PLATFORM_PHOENIX: |
| 1822 | case PLATFORM_GLINDA: |
| 1823 | return false; |
| 1824 | default: |
| 1825 | return true; |
| 1826 | } |
| 1827 | } |
| 1828 | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1829 | int main(int argc, char **argv) |
| 1830 | { |
Marshall Dawson | 0e02ce8 | 2019-03-04 16:50:37 -0700 | [diff] [blame] | 1831 | int c; |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 1832 | int retval = 0; |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 1833 | char *tmp; |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 1834 | embedded_firmware *amd_romsig; |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1835 | psp_directory_table *pspdir = NULL; |
| 1836 | psp_directory_table *pspdir2 = NULL; |
| 1837 | psp_directory_table *pspdir2_b = NULL; |
Zheng Bao | 84fb9ea | 2022-08-18 15:54:47 +0800 | [diff] [blame] | 1838 | psp_combo_directory *psp_combo_dir = NULL, *bhd_combo_dir = NULL; |
Zheng Bao | 0e3d18b | 2023-03-07 15:28:57 +0800 | [diff] [blame] | 1839 | char *combo_config[MAX_COMBO_ENTRIES] = { 0 }; |
| 1840 | int combo_index = 0; |
Marshall Dawson | ef79fcc | 2019-04-01 10:16:41 -0600 | [diff] [blame] | 1841 | int fuse_defined = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1842 | int targetfd; |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1843 | char *output = NULL, *config = NULL; |
Zheng Bao | 9c8ce3e | 2020-09-28 10:36:29 +0800 | [diff] [blame] | 1844 | context ctx = { 0 }; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1845 | /* Values cleared after each firmware or parameter, regardless if N/A */ |
| 1846 | uint8_t sub = 0, instance = 0; |
Zheng Bao | 99945dc | 2023-01-02 10:55:56 +0800 | [diff] [blame] | 1847 | uint32_t body_location = 0; |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 1848 | uint32_t efs_location = 0; |
Martin Roth | 37305e7 | 2020-04-07 14:16:39 -0600 | [diff] [blame] | 1849 | bool any_location = 0; |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 1850 | uint32_t romsig_offset; |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 1851 | uint32_t rom_base_address; |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1852 | uint8_t efs_spi_readmode = 0xff; |
| 1853 | uint8_t efs_spi_speed = 0xff; |
| 1854 | uint8_t efs_spi_micron_flag = 0xff; |
Kangheui Won | 3c164e1 | 2021-12-03 20:25:05 +1100 | [diff] [blame] | 1855 | const char *signed_output_file = NULL; |
| 1856 | uint64_t signed_start_addr = 0x0; |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1857 | |
Fred Reitberger | f36b013 | 2022-06-29 13:54:57 -0400 | [diff] [blame] | 1858 | amd_cb_config cb_config = { 0 }; |
Zheng Bao | 9e90807 | 2020-10-28 11:39:13 +0800 | [diff] [blame] | 1859 | int debug = 0; |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1860 | |
Zheng Bao | c26108f | 2023-02-17 11:01:07 +0800 | [diff] [blame] | 1861 | ctx.current_pointer_saved = 0xFFFFFFFF; |
| 1862 | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1863 | while (1) { |
| 1864 | int optindex = 0; |
Karthikeyan Ramasubramanian | bd9dd42 | 2022-12-22 15:45:56 -0700 | [diff] [blame] | 1865 | int bios_tbl_index = -1; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1866 | |
| 1867 | c = getopt_long(argc, argv, optstring, long_options, &optindex); |
| 1868 | |
| 1869 | if (c == -1) |
| 1870 | break; |
| 1871 | |
| 1872 | switch (c) { |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1873 | case AMDFW_OPT_XHCI: |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1874 | register_fw_filename(AMD_FW_XHCI, sub, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1875 | sub = instance = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1876 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1877 | case AMDFW_OPT_IMC: |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1878 | register_fw_filename(AMD_FW_IMC, sub, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1879 | sub = instance = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1880 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1881 | case AMDFW_OPT_GEC: |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1882 | register_fw_filename(AMD_FW_GEC, sub, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1883 | sub = instance = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1884 | break; |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1885 | case AMDFW_OPT_RECOVERY_AB: |
| 1886 | cb_config.recovery_ab = true; |
| 1887 | break; |
Karthikeyan Ramasubramanian | ad06bae | 2022-04-08 14:19:55 -0600 | [diff] [blame] | 1888 | case AMDFW_OPT_RECOVERY_AB_SINGLE_COPY: |
| 1889 | cb_config.recovery_ab = true; |
| 1890 | cb_config.recovery_ab_single_copy = true; |
| 1891 | break; |
Zheng Bao | 993b43f | 2021-11-10 12:21:46 +0800 | [diff] [blame] | 1892 | case AMDFW_OPT_USE_COMBO: |
| 1893 | cb_config.use_combo = true; |
| 1894 | break; |
Zheng Bao | 0e3d18b | 2023-03-07 15:28:57 +0800 | [diff] [blame] | 1895 | case AMDFW_OPT_COMBO1_CONFIG: |
| 1896 | cb_config.use_combo = true; |
Zheng Bao | 7391722 | 2023-03-15 16:14:03 +0800 | [diff] [blame] | 1897 | assert_fw_entry(1, MAX_COMBO_ENTRIES, &ctx); |
Zheng Bao | 0e3d18b | 2023-03-07 15:28:57 +0800 | [diff] [blame] | 1898 | combo_config[1] = optarg; |
| 1899 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1900 | case AMDFW_OPT_MULTILEVEL: |
Zheng Bao | ba3af5e | 2021-11-04 18:56:47 +0800 | [diff] [blame] | 1901 | cb_config.multi_level = true; |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 1902 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1903 | case AMDFW_OPT_UNLOCK: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1904 | register_fw_token_unlock(); |
Zheng Bao | ba3af5e | 2021-11-04 18:56:47 +0800 | [diff] [blame] | 1905 | cb_config.unlock_secure = true; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1906 | sub = instance = 0; |
| 1907 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1908 | case AMDFW_OPT_USE_PSPSECUREOS: |
Zheng Bao | ba3af5e | 2021-11-04 18:56:47 +0800 | [diff] [blame] | 1909 | cb_config.use_secureos = true; |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1910 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1911 | case AMDFW_OPT_INSTANCE: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1912 | instance = strtoul(optarg, &tmp, 16); |
| 1913 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1914 | case AMDFW_OPT_LOAD_MP2FW: |
Zheng Bao | ba3af5e | 2021-11-04 18:56:47 +0800 | [diff] [blame] | 1915 | cb_config.load_mp2_fw = true; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1916 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1917 | case AMDFW_OPT_NVRAM: |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1918 | register_fw_filename(AMD_FW_PSP_NVRAM, sub, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1919 | sub = instance = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1920 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1921 | case AMDFW_OPT_FUSE: |
Marshall Dawson | ef79fcc | 2019-04-01 10:16:41 -0600 | [diff] [blame] | 1922 | register_fw_fuse(optarg); |
| 1923 | fuse_defined = 1; |
| 1924 | sub = 0; |
| 1925 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1926 | case AMDFW_OPT_APCB: |
Karthikeyan Ramasubramanian | 8d88561 | 2023-03-09 17:39:31 -0700 | [diff] [blame] | 1927 | if ((instance & 0xF0) == 0) { |
Zheng Bao | 5caca94 | 2020-12-04 16:39:38 +0800 | [diff] [blame] | 1928 | register_bdt_data(AMD_BIOS_APCB, sub, instance & 0xF, optarg); |
Karthikeyan Ramasubramanian | 8d88561 | 2023-03-09 17:39:31 -0700 | [diff] [blame] | 1929 | } else { |
Zheng Bao | 5caca94 | 2020-12-04 16:39:38 +0800 | [diff] [blame] | 1930 | register_bdt_data(AMD_BIOS_APCB_BK, sub, |
| 1931 | instance & 0xF, optarg); |
Karthikeyan Ramasubramanian | 8d88561 | 2023-03-09 17:39:31 -0700 | [diff] [blame] | 1932 | cb_config.have_apcb_bk = 1; |
| 1933 | } |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1934 | sub = instance = 0; |
| 1935 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1936 | case AMDFW_OPT_APOBBASE: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1937 | /* APOB destination */ |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 1938 | register_bios_fw_addr(AMD_BIOS_APOB, 0, optarg, 0); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1939 | sub = instance = 0; |
| 1940 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1941 | case AMDFW_OPT_APOB_NVBASE: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1942 | /* APOB NV source */ |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 1943 | register_bios_fw_addr(AMD_BIOS_APOB_NV, optarg, 0, 0); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1944 | sub = instance = 0; |
| 1945 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1946 | case AMDFW_OPT_APOB_NVSIZE: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1947 | /* APOB NV size */ |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 1948 | register_bios_fw_addr(AMD_BIOS_APOB_NV, 0, 0, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1949 | sub = instance = 0; |
| 1950 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1951 | case AMDFW_OPT_BIOSBIN: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1952 | register_bdt_data(AMD_BIOS_BIN, sub, instance, optarg); |
| 1953 | sub = instance = 0; |
| 1954 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1955 | case AMDFW_OPT_BIOSBIN_SOURCE: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1956 | /* BIOS source */ |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 1957 | register_bios_fw_addr(AMD_BIOS_BIN, optarg, 0, 0); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1958 | sub = instance = 0; |
| 1959 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1960 | case AMDFW_OPT_BIOSBIN_DEST: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1961 | /* BIOS destination */ |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 1962 | register_bios_fw_addr(AMD_BIOS_BIN, 0, optarg, 0); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1963 | sub = instance = 0; |
| 1964 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1965 | case AMDFW_OPT_BIOS_UNCOMP_SIZE: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1966 | /* BIOS destination size */ |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 1967 | register_bios_fw_addr(AMD_BIOS_BIN, 0, 0, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1968 | sub = instance = 0; |
| 1969 | break; |
Karthikeyan Ramasubramanian | bd9dd42 | 2022-12-22 15:45:56 -0700 | [diff] [blame] | 1970 | case AMDFW_OPT_BIOSBIN_UNCOMP: |
| 1971 | bios_tbl_index = find_bios_entry(AMD_BIOS_BIN); |
| 1972 | if (bios_tbl_index != -1) |
| 1973 | amd_bios_table[bios_tbl_index].zlib = 0; |
| 1974 | break; |
Ritul Guru | 9a321f3 | 2022-07-29 11:06:40 +0530 | [diff] [blame] | 1975 | case LONGOPT_BIOS_SIG: |
| 1976 | /* BIOS signature size */ |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 1977 | register_bios_fw_addr(AMD_BIOS_SIG, 0, 0, optarg); |
Ritul Guru | 9a321f3 | 2022-07-29 11:06:40 +0530 | [diff] [blame] | 1978 | sub = instance = 0; |
| 1979 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1980 | case AMDFW_OPT_UCODE: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1981 | register_bdt_data(AMD_BIOS_UCODE, sub, |
| 1982 | instance, optarg); |
| 1983 | sub = instance = 0; |
| 1984 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1985 | case AMDFW_OPT_LOAD_S0I3: |
Zheng Bao | ba3af5e | 2021-11-04 18:56:47 +0800 | [diff] [blame] | 1986 | cb_config.s0i3 = true; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1987 | break; |
Zheng Bao | 6c5ec8e | 2022-02-11 11:51:26 +0800 | [diff] [blame] | 1988 | case AMDFW_OPT_SPL_TABLE: |
| 1989 | register_fw_filename(AMD_FW_SPL, sub, optarg); |
| 1990 | sub = instance = 0; |
| 1991 | cb_config.have_mb_spl = true; |
| 1992 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1993 | case AMDFW_OPT_WHITELIST: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1994 | register_fw_filename(AMD_FW_PSP_WHITELIST, sub, optarg); |
| 1995 | sub = instance = 0; |
Zheng Bao | ba3af5e | 2021-11-04 18:56:47 +0800 | [diff] [blame] | 1996 | cb_config.have_whitelist = true; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1997 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1998 | case AMDFW_OPT_VERSTAGE: |
Martin Roth | d3ce8c8 | 2019-07-13 20:13:07 -0600 | [diff] [blame] | 1999 | register_fw_filename(AMD_FW_PSP_VERSTAGE, sub, optarg); |
| 2000 | sub = instance = 0; |
| 2001 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2002 | case AMDFW_OPT_VERSTAGE_SIG: |
Martin Roth | b1f648f | 2020-09-01 09:36:59 -0600 | [diff] [blame] | 2003 | register_fw_filename(AMD_FW_VERSTAGE_SIG, sub, optarg); |
| 2004 | sub = instance = 0; |
| 2005 | break; |
Kangheui Won | 3c164e1 | 2021-12-03 20:25:05 +1100 | [diff] [blame] | 2006 | case AMDFW_OPT_SIGNED_OUTPUT: |
| 2007 | signed_output_file = optarg; |
| 2008 | sub = instance = 0; |
| 2009 | break; |
| 2010 | case AMDFW_OPT_SIGNED_ADDR: |
| 2011 | signed_start_addr = strtoull(optarg, NULL, 10); |
| 2012 | sub = instance = 0; |
| 2013 | break; |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 2014 | case LONGOPT_SPI_READ_MODE: |
| 2015 | efs_spi_readmode = strtoull(optarg, NULL, 16); |
| 2016 | sub = instance = 0; |
| 2017 | break; |
| 2018 | case LONGOPT_SPI_SPEED: |
| 2019 | efs_spi_speed = strtoull(optarg, NULL, 16); |
| 2020 | sub = instance = 0; |
| 2021 | break; |
| 2022 | case LONGOPT_SPI_MICRON_FLAG: |
| 2023 | efs_spi_micron_flag = strtoull(optarg, NULL, 16); |
| 2024 | sub = instance = 0; |
| 2025 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2026 | case AMDFW_OPT_OUTPUT: |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 2027 | output = optarg; |
| 2028 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2029 | case AMDFW_OPT_FLASHSIZE: |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 2030 | ctx.rom_size = (uint32_t)strtoul(optarg, &tmp, 16); |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 2031 | if (*tmp != '\0') { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 2032 | fprintf(stderr, "Error: ROM size specified" |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 2033 | " incorrectly (%s)\n\n", optarg); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 2034 | retval = 1; |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 2035 | } |
| 2036 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2037 | case AMDFW_OPT_LOCATION: |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 2038 | efs_location = (uint32_t)strtoul(optarg, &tmp, 16); |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 2039 | if (*tmp != '\0') { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 2040 | fprintf(stderr, "Error: Directory Location specified" |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 2041 | " incorrectly (%s)\n\n", optarg); |
| 2042 | retval = 1; |
| 2043 | } |
Zheng Bao | 99945dc | 2023-01-02 10:55:56 +0800 | [diff] [blame] | 2044 | if (body_location == 0) |
| 2045 | body_location = efs_location; |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 2046 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2047 | case AMDFW_OPT_ANYWHERE: |
Martin Roth | 37305e7 | 2020-04-07 14:16:39 -0600 | [diff] [blame] | 2048 | any_location = 1; |
| 2049 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2050 | case AMDFW_OPT_SHAREDMEM: |
Martin Roth | 9455474 | 2020-04-14 14:59:36 -0600 | [diff] [blame] | 2051 | /* shared memory destination */ |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 2052 | register_bios_fw_addr(AMD_BIOS_PSP_SHARED_MEM, 0, optarg, 0); |
Martin Roth | 9455474 | 2020-04-14 14:59:36 -0600 | [diff] [blame] | 2053 | sub = instance = 0; |
| 2054 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2055 | case AMDFW_OPT_SHAREDMEM_SIZE: |
Martin Roth | 9455474 | 2020-04-14 14:59:36 -0600 | [diff] [blame] | 2056 | /* shared memory size */ |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 2057 | register_bios_fw_addr(AMD_BIOS_PSP_SHARED_MEM, NULL, NULL, optarg); |
Martin Roth | 9455474 | 2020-04-14 14:59:36 -0600 | [diff] [blame] | 2058 | sub = instance = 0; |
| 2059 | break; |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 2060 | case LONGOPT_NVRAM_BASE: |
| 2061 | /* PSP NV base */ |
| 2062 | register_amd_psp_fw_addr(AMD_FW_PSP_NVRAM, sub, optarg, 0); |
| 2063 | sub = instance = 0; |
| 2064 | break; |
| 2065 | case LONGOPT_NVRAM_SIZE: |
| 2066 | /* PSP NV size */ |
| 2067 | register_amd_psp_fw_addr(AMD_FW_PSP_NVRAM, sub, 0, optarg); |
| 2068 | sub = instance = 0; |
| 2069 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2070 | case AMDFW_OPT_CONFIG: |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 2071 | config = optarg; |
| 2072 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2073 | case AMDFW_OPT_DEBUG: |
Zheng Bao | 9e90807 | 2020-10-28 11:39:13 +0800 | [diff] [blame] | 2074 | debug = 1; |
| 2075 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2076 | case AMDFW_OPT_HELP: |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 2077 | usage(); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 2078 | return 0; |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 2079 | case AMDFW_OPT_BODY_LOCATION: |
Zheng Bao | 99945dc | 2023-01-02 10:55:56 +0800 | [diff] [blame] | 2080 | body_location = (uint32_t)strtoul(optarg, &tmp, 16); |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 2081 | if (*tmp != '\0') { |
| 2082 | fprintf(stderr, "Error: Body Location specified" |
| 2083 | " incorrectly (%s)\n\n", optarg); |
| 2084 | retval = 1; |
| 2085 | } |
| 2086 | break; |
| 2087 | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 2088 | default: |
| 2089 | break; |
| 2090 | } |
| 2091 | } |
| 2092 | |
Zheng Bao | 8dd34bd | 2023-03-09 21:09:58 +0800 | [diff] [blame] | 2093 | if (cb_config.use_combo) { |
| 2094 | ctx.amd_psp_fw_table_clean = malloc(sizeof(amd_psp_fw_table)); |
| 2095 | ctx.amd_bios_table_clean = malloc(sizeof(amd_bios_table)); |
| 2096 | memcpy(ctx.amd_psp_fw_table_clean, amd_psp_fw_table, sizeof(amd_psp_fw_table)); |
| 2097 | memcpy(ctx.amd_bios_table_clean, amd_bios_table, sizeof(amd_bios_table)); |
| 2098 | } |
| 2099 | |
Zheng Bao | 994ff52 | 2023-03-09 11:43:55 +0800 | [diff] [blame] | 2100 | open_process_config(config, &cb_config, debug); |
Zheng Bao | 9e90807 | 2020-10-28 11:39:13 +0800 | [diff] [blame] | 2101 | |
Marshall Dawson | ef79fcc | 2019-04-01 10:16:41 -0600 | [diff] [blame] | 2102 | if (!fuse_defined) |
| 2103 | register_fw_fuse(DEFAULT_SOFT_FUSE_CHAIN); |
| 2104 | |
Zheng Bao | 994ff52 | 2023-03-09 11:43:55 +0800 | [diff] [blame] | 2105 | if (!output) { |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 2106 | fprintf(stderr, "Error: Output value is not specified.\n\n"); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 2107 | retval = 1; |
| 2108 | } |
| 2109 | |
Zheng Bao | a7731cc | 2023-03-11 09:27:53 +0800 | [diff] [blame] | 2110 | if (ctx.rom_size % 1024 != 0) { |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 2111 | fprintf(stderr, "Error: ROM Size (%d bytes) should be a multiple of" |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 2112 | " 1024 bytes.\n\n", ctx.rom_size); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 2113 | retval = 1; |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 2114 | } |
| 2115 | |
Zheng Bao | a7731cc | 2023-03-11 09:27:53 +0800 | [diff] [blame] | 2116 | if (ctx.rom_size < MIN_ROM_KB * 1024) { |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 2117 | fprintf(stderr, "Error: ROM Size (%dKB) must be at least %dKB.\n\n", |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 2118 | ctx.rom_size / 1024, MIN_ROM_KB); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 2119 | retval = 1; |
| 2120 | } |
| 2121 | |
| 2122 | if (retval) { |
| 2123 | usage(); |
| 2124 | return retval; |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 2125 | } |
| 2126 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 2127 | printf(" AMDFWTOOL Using ROM size of %dKB\n", ctx.rom_size / 1024); |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 2128 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 2129 | rom_base_address = 0xFFFFFFFF - ctx.rom_size + 1; |
Zheng Bao | 9770df1 | 2023-02-14 13:23:35 +0800 | [diff] [blame] | 2130 | |
| 2131 | if (efs_location & 0xFF000000) |
| 2132 | efs_location = efs_location - rom_base_address; |
| 2133 | if (body_location & 0xFF000000) |
| 2134 | body_location = body_location - rom_base_address; |
| 2135 | |
| 2136 | if (efs_location && efs_location > ctx.rom_size) { |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 2137 | fprintf(stderr, "Error: EFS/Directory location outside of ROM.\n\n"); |
| 2138 | return 1; |
| 2139 | } |
Zheng Bao | 9770df1 | 2023-02-14 13:23:35 +0800 | [diff] [blame] | 2140 | if (body_location && body_location > ctx.rom_size) { |
| 2141 | fprintf(stderr, "Error: Body location outside of ROM.\n\n"); |
| 2142 | return 1; |
| 2143 | } |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 2144 | |
Zheng Bao | 99945dc | 2023-01-02 10:55:56 +0800 | [diff] [blame] | 2145 | if (!efs_location && body_location) { |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 2146 | fprintf(stderr, "Error AMDFW body location specified without EFS location.\n"); |
| 2147 | return 1; |
| 2148 | } |
| 2149 | |
Zheng Bao | 99945dc | 2023-01-02 10:55:56 +0800 | [diff] [blame] | 2150 | if (body_location != efs_location && |
| 2151 | body_location < ALIGN(efs_location + sizeof(embedded_firmware), BLOB_ALIGNMENT)) { |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 2152 | fprintf(stderr, "Error: Insufficient space between EFS and Blobs.\n"); |
| 2153 | fprintf(stderr, " Require safe spacing of 256 bytes\n"); |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 2154 | return 1; |
| 2155 | } |
| 2156 | |
Martin Roth | 37305e7 | 2020-04-07 14:16:39 -0600 | [diff] [blame] | 2157 | if (any_location) { |
Zheng Bao | 99945dc | 2023-01-02 10:55:56 +0800 | [diff] [blame] | 2158 | if ((body_location & 0x3f) || (efs_location & 0x3f)) { |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 2159 | fprintf(stderr, "Error: Invalid Directory/EFS location.\n"); |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 2160 | fprintf(stderr, " Valid locations are 64-byte aligned\n"); |
Martin Roth | 37305e7 | 2020-04-07 14:16:39 -0600 | [diff] [blame] | 2161 | return 1; |
| 2162 | } |
| 2163 | } else { |
Zheng Bao | 4e8fb35 | 2022-11-21 21:34:45 +0800 | [diff] [blame] | 2164 | /* efs_location is relative address now. */ |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 2165 | switch (efs_location) { |
Zheng Bao | 92c920b | 2022-12-08 13:56:13 +0800 | [diff] [blame] | 2166 | case 0: |
Zheng Bao | 4e8fb35 | 2022-11-21 21:34:45 +0800 | [diff] [blame] | 2167 | case 0xFA0000: |
| 2168 | case 0xF20000: |
| 2169 | case 0xE20000: |
| 2170 | case 0xC20000: |
| 2171 | case 0x820000: |
| 2172 | case 0x020000: |
| 2173 | break; |
| 2174 | case 0x7A0000: |
| 2175 | case 0x720000: |
| 2176 | case 0x620000: |
| 2177 | case 0x420000: |
| 2178 | /* Special cases for 8M. */ |
| 2179 | if (ctx.rom_size != 0x800000) { |
| 2180 | fprintf(stderr, "Error: Invalid Directory location.\n"); |
| 2181 | fprintf(stderr, "%x is only for 8M image size.", efs_location); |
| 2182 | return 1; |
| 2183 | } |
| 2184 | break; |
| 2185 | case 0x3A0000: |
| 2186 | case 0x320000: |
| 2187 | case 0x220000: |
| 2188 | /* Special cases for 4M. */ |
| 2189 | if (ctx.rom_size != 0x400000) { |
| 2190 | fprintf(stderr, "Error: Invalid Directory location.\n"); |
| 2191 | fprintf(stderr, "%x is only for 4M image size.", efs_location); |
| 2192 | return 1; |
| 2193 | } |
Martin Roth | 37305e7 | 2020-04-07 14:16:39 -0600 | [diff] [blame] | 2194 | break; |
| 2195 | default: |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 2196 | fprintf(stderr, "Error: Invalid Directory location.\n"); |
| 2197 | fprintf(stderr, " Valid locations are 0xFFFA0000, 0xFFF20000,\n"); |
| 2198 | fprintf(stderr, " 0xFFE20000, 0xFFC20000, 0xFF820000, 0xFF020000\n"); |
Zheng Bao | 4e8fb35 | 2022-11-21 21:34:45 +0800 | [diff] [blame] | 2199 | fprintf(stderr, " 0xFA0000, 0xF20000, 0xE20000, 0xC20000,\n"); |
| 2200 | fprintf(stderr, " 0x820000, 0x020000\n"); |
Martin Roth | 37305e7 | 2020-04-07 14:16:39 -0600 | [diff] [blame] | 2201 | return 1; |
| 2202 | } |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 2203 | } |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 2204 | ctx.rom = malloc(ctx.rom_size); |
| 2205 | if (!ctx.rom) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 2206 | fprintf(stderr, "Error: Failed to allocate memory\n"); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 2207 | return 1; |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 2208 | } |
| 2209 | memset(ctx.rom, 0xFF, ctx.rom_size); |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 2210 | |
Zheng Bao | 6095cd1 | 2023-02-21 10:52:47 +0800 | [diff] [blame] | 2211 | romsig_offset = efs_location ? efs_location : AMD_ROMSIG_OFFSET; |
| 2212 | set_current_pointer(&ctx, romsig_offset); |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 2213 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 2214 | amd_romsig = BUFF_OFFSET(ctx, romsig_offset); |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 2215 | amd_romsig->signature = EMBEDDED_FW_SIGNATURE; |
| 2216 | amd_romsig->imc_entry = 0; |
| 2217 | amd_romsig->gec_entry = 0; |
| 2218 | amd_romsig->xhci_entry = 0; |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 2219 | |
Zheng Bao | 4bf6f49 | 2023-01-25 22:37:29 +0800 | [diff] [blame] | 2220 | if (cb_config.soc_id != PLATFORM_UNKNOWN) { |
| 2221 | retval = set_efs_table(cb_config.soc_id, &cb_config, amd_romsig, |
| 2222 | efs_spi_readmode, efs_spi_speed, efs_spi_micron_flag); |
Zheng Bao | 570645d | 2021-11-03 10:25:03 +0800 | [diff] [blame] | 2223 | if (retval) { |
| 2224 | fprintf(stderr, "ERROR: Failed to initialize EFS table!\n"); |
| 2225 | return retval; |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 2226 | } |
| 2227 | } else { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 2228 | fprintf(stderr, "WARNING: No SOC name specified.\n"); |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 2229 | } |
| 2230 | |
Felix Held | 21a8e38 | 2022-03-29 23:10:45 +0200 | [diff] [blame] | 2231 | if (cb_config.need_ish) |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 2232 | ctx.address_mode = AMD_ADDR_REL_TAB; |
Zheng Bao | c3007f3 | 2022-04-03 12:53:51 +0800 | [diff] [blame] | 2233 | else if (cb_config.second_gen) |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 2234 | ctx.address_mode = AMD_ADDR_REL_BIOS; |
Zheng Bao | da83d2c | 2021-06-04 19:03:10 +0800 | [diff] [blame] | 2235 | else |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 2236 | ctx.address_mode = AMD_ADDR_PHYSICAL; |
Zheng Bao | 7c7294f | 2023-01-04 16:38:28 +0800 | [diff] [blame] | 2237 | printf(" AMDFWTOOL Using firmware directory location of address: 0x%08x", |
| 2238 | efs_location); |
| 2239 | if (body_location != efs_location) |
| 2240 | printf(" with a split body at: 0x%08x\n", body_location); |
| 2241 | else |
| 2242 | printf("\n"); |
Zheng Bao | da83d2c | 2021-06-04 19:03:10 +0800 | [diff] [blame] | 2243 | |
Zheng Bao | 6095cd1 | 2023-02-21 10:52:47 +0800 | [diff] [blame] | 2244 | if (efs_location != body_location) |
| 2245 | set_current_pointer(&ctx, body_location); |
| 2246 | else |
| 2247 | set_current_pointer(&ctx, romsig_offset + sizeof(embedded_firmware)); |
| 2248 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 2249 | integrate_firmwares(&ctx, amd_romsig, amd_fw_table); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 2250 | |
Karthikeyan Ramasubramanian | 225b4b3 | 2023-03-08 10:24:50 -0700 | [diff] [blame] | 2251 | if (is_initial_alignment_required(cb_config.soc_id)) { |
| 2252 | /* TODO: Check for older platforms. */ |
| 2253 | adjust_current_pointer(&ctx, 0, 0x10000U); |
| 2254 | } |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 2255 | ctx.current_table = 0; |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 2256 | |
Kangheui Won | 3c164e1 | 2021-12-03 20:25:05 +1100 | [diff] [blame] | 2257 | /* If the tool is invoked with command-line options to keep the signed PSP |
| 2258 | binaries separate, process the signed binaries first. */ |
| 2259 | if (signed_output_file && signed_start_addr) |
| 2260 | process_signed_psp_firmwares(signed_output_file, |
| 2261 | amd_psp_fw_table, |
| 2262 | signed_start_addr, |
Zheng Bao | 4bf6f49 | 2023-01-25 22:37:29 +0800 | [diff] [blame] | 2263 | cb_config.soc_id); |
Kangheui Won | 3c164e1 | 2021-12-03 20:25:05 +1100 | [diff] [blame] | 2264 | |
Zheng Bao | b2ae6a5 | 2022-08-18 15:45:27 +0800 | [diff] [blame] | 2265 | if (cb_config.use_combo) { |
| 2266 | psp_combo_dir = new_combo_dir(&ctx); |
Zheng Bao | 84fb9ea | 2022-08-18 15:54:47 +0800 | [diff] [blame] | 2267 | |
| 2268 | adjust_current_pointer(&ctx, 0, 0x1000U); |
| 2269 | |
| 2270 | bhd_combo_dir = new_combo_dir(&ctx); |
Zheng Bao | b2ae6a5 | 2022-08-18 15:45:27 +0800 | [diff] [blame] | 2271 | } |
| 2272 | |
Zheng Bao | 0e3d18b | 2023-03-07 15:28:57 +0800 | [diff] [blame] | 2273 | combo_index = 0; |
| 2274 | if (config) |
| 2275 | combo_config[0] = config; |
| 2276 | |
Zheng Bao | 4b6aa19 | 2023-03-09 11:28:47 +0800 | [diff] [blame] | 2277 | do { |
Zheng Bao | 3e7008d | 2023-03-15 16:15:13 +0800 | [diff] [blame] | 2278 | if (cb_config.use_combo && debug) |
| 2279 | printf("Processing %dth combo entry\n", combo_index); |
| 2280 | |
Zheng Bao | 4b6aa19 | 2023-03-09 11:28:47 +0800 | [diff] [blame] | 2281 | /* for non-combo image, combo_config[0] == config, and |
| 2282 | * it already is processed. Actually "combo_index > |
| 2283 | * 0" is enough. Put both of them here to make sure |
| 2284 | * and make it clear this will not affect non-combo |
| 2285 | * case. |
| 2286 | */ |
| 2287 | if (cb_config.use_combo && combo_index > 0) { |
Zheng Bao | 8dd34bd | 2023-03-09 21:09:58 +0800 | [diff] [blame] | 2288 | /* Restore the table as clean data. */ |
| 2289 | memcpy(amd_psp_fw_table, ctx.amd_psp_fw_table_clean, |
| 2290 | sizeof(amd_psp_fw_table)); |
| 2291 | memcpy(amd_bios_table, ctx.amd_bios_table_clean, |
| 2292 | sizeof(amd_bios_table)); |
Zheng Bao | 7391722 | 2023-03-15 16:14:03 +0800 | [diff] [blame] | 2293 | assert_fw_entry(combo_index, MAX_COMBO_ENTRIES, &ctx); |
Zheng Bao | 4b6aa19 | 2023-03-09 11:28:47 +0800 | [diff] [blame] | 2294 | open_process_config(combo_config[combo_index], &cb_config, |
Zheng Bao | 994ff52 | 2023-03-09 11:43:55 +0800 | [diff] [blame] | 2295 | debug); |
Zheng Bao | 0e3d18b | 2023-03-07 15:28:57 +0800 | [diff] [blame] | 2296 | |
Zheng Bao | 4b6aa19 | 2023-03-09 11:28:47 +0800 | [diff] [blame] | 2297 | /* In most cases, the address modes are same. */ |
| 2298 | if (cb_config.need_ish) |
| 2299 | ctx.address_mode = AMD_ADDR_REL_TAB; |
| 2300 | else if (cb_config.second_gen) |
| 2301 | ctx.address_mode = AMD_ADDR_REL_BIOS; |
| 2302 | else |
| 2303 | ctx.address_mode = AMD_ADDR_PHYSICAL; |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 2304 | } |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 2305 | |
Zheng Bao | 481661e | 2021-08-20 14:47:46 +0800 | [diff] [blame] | 2306 | if (cb_config.multi_level) { |
Zheng Bao | 4b6aa19 | 2023-03-09 11:28:47 +0800 | [diff] [blame] | 2307 | /* Do 2nd PSP directory followed by 1st */ |
| 2308 | pspdir2 = new_psp_dir(&ctx, cb_config.multi_level); |
| 2309 | integrate_psp_firmwares(&ctx, pspdir2, NULL, NULL, |
| 2310 | amd_psp_fw_table, PSPL2_COOKIE, &cb_config); |
| 2311 | if (cb_config.recovery_ab && !cb_config.recovery_ab_single_copy) { |
| 2312 | /* Create a copy of PSP Directory 2 in the backup slot B. |
| 2313 | Related biosdir2_b copy will be created later. */ |
| 2314 | pspdir2_b = new_psp_dir(&ctx, cb_config.multi_level); |
| 2315 | integrate_psp_firmwares(&ctx, pspdir2_b, NULL, NULL, |
| 2316 | amd_psp_fw_table, PSPL2_COOKIE, &cb_config); |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 2317 | } else { |
Zheng Bao | 4b6aa19 | 2023-03-09 11:28:47 +0800 | [diff] [blame] | 2318 | /* |
| 2319 | * Either the platform is using only |
| 2320 | * one slot or B is same as above |
| 2321 | * directories for A. Skip creating |
| 2322 | * pspdir2_b here to save flash space. |
| 2323 | * Related biosdir2_b will be skipped |
| 2324 | * automatically. |
| 2325 | */ |
| 2326 | pspdir2_b = NULL; /* More explicitly */ |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 2327 | } |
Zheng Bao | 4b6aa19 | 2023-03-09 11:28:47 +0800 | [diff] [blame] | 2328 | pspdir = new_psp_dir(&ctx, cb_config.multi_level); |
| 2329 | integrate_psp_firmwares(&ctx, pspdir, pspdir2, pspdir2_b, |
| 2330 | amd_psp_fw_table, PSP_COOKIE, &cb_config); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 2331 | } else { |
Zheng Bao | 4b6aa19 | 2023-03-09 11:28:47 +0800 | [diff] [blame] | 2332 | /* flat: PSP 1 cookie and no pointer to 2nd table */ |
| 2333 | pspdir = new_psp_dir(&ctx, cb_config.multi_level); |
| 2334 | integrate_psp_firmwares(&ctx, pspdir, NULL, NULL, |
| 2335 | amd_psp_fw_table, PSP_COOKIE, &cb_config); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 2336 | } |
Zheng Bao | 84fb9ea | 2022-08-18 15:54:47 +0800 | [diff] [blame] | 2337 | |
Zheng Bao | 4b6aa19 | 2023-03-09 11:28:47 +0800 | [diff] [blame] | 2338 | if (!cb_config.use_combo) { |
| 2339 | fill_psp_directory_to_efs(amd_romsig, pspdir, &ctx, &cb_config); |
| 2340 | } else { |
| 2341 | fill_psp_directory_to_efs(amd_romsig, psp_combo_dir, &ctx, &cb_config); |
| 2342 | /* 0 -Compare PSP ID, 1 -Compare chip family ID */ |
| 2343 | assert_fw_entry(combo_index, MAX_COMBO_ENTRIES, &ctx); |
| 2344 | psp_combo_dir->entries[combo_index].id_sel = 0; |
| 2345 | psp_combo_dir->entries[combo_index].id = get_psp_id(cb_config.soc_id); |
| 2346 | psp_combo_dir->entries[combo_index].lvl2_addr = |
| 2347 | BUFF_TO_RUN_MODE(ctx, pspdir, AMD_ADDR_REL_BIOS); |
| 2348 | |
| 2349 | fill_dir_header(psp_combo_dir, combo_index + 1, PSP2_COOKIE, &ctx); |
Zheng Bao | 84fb9ea | 2022-08-18 15:54:47 +0800 | [diff] [blame] | 2350 | } |
Zheng Bao | 4b6aa19 | 2023-03-09 11:28:47 +0800 | [diff] [blame] | 2351 | |
| 2352 | if (have_bios_tables(amd_bios_table)) { |
| 2353 | bios_directory_table *biosdir = NULL; |
| 2354 | if (cb_config.multi_level) { |
| 2355 | /* Do 2nd level BIOS directory followed by 1st */ |
| 2356 | bios_directory_table *biosdir2 = NULL; |
| 2357 | bios_directory_table *biosdir2_b = NULL; |
| 2358 | |
| 2359 | biosdir2 = new_bios_dir(&ctx, cb_config.multi_level); |
| 2360 | |
| 2361 | integrate_bios_firmwares(&ctx, biosdir2, NULL, |
| 2362 | amd_bios_table, BHDL2_COOKIE, &cb_config); |
| 2363 | if (cb_config.recovery_ab) { |
| 2364 | if (pspdir2_b != NULL) { |
| 2365 | biosdir2_b = new_bios_dir(&ctx, |
| 2366 | cb_config.multi_level); |
| 2367 | integrate_bios_firmwares(&ctx, biosdir2_b, NULL, |
| 2368 | amd_bios_table, BHDL2_COOKIE, |
| 2369 | &cb_config); |
| 2370 | } |
| 2371 | add_psp_firmware_entry(&ctx, pspdir2, biosdir2, |
| 2372 | AMD_FW_BIOS_TABLE, TABLE_ALIGNMENT); |
| 2373 | if (pspdir2_b != NULL) |
| 2374 | add_psp_firmware_entry(&ctx, pspdir2_b, |
| 2375 | biosdir2_b, AMD_FW_BIOS_TABLE, |
| 2376 | TABLE_ALIGNMENT); |
| 2377 | } else { |
| 2378 | biosdir = new_bios_dir(&ctx, cb_config.multi_level); |
| 2379 | integrate_bios_firmwares(&ctx, biosdir, biosdir2, |
| 2380 | amd_bios_table, BHD_COOKIE, &cb_config); |
| 2381 | } |
| 2382 | } else { |
| 2383 | /* flat: BHD1 cookie and no pointer to 2nd table */ |
| 2384 | biosdir = new_bios_dir(&ctx, cb_config.multi_level); |
| 2385 | integrate_bios_firmwares(&ctx, biosdir, NULL, |
| 2386 | amd_bios_table, BHD_COOKIE, &cb_config); |
| 2387 | } |
| 2388 | if (!cb_config.use_combo) { |
| 2389 | fill_bios_directory_to_efs(amd_romsig, biosdir, |
| 2390 | &ctx, &cb_config); |
| 2391 | } else { |
| 2392 | fill_bios_directory_to_efs(amd_romsig, bhd_combo_dir, |
| 2393 | &ctx, &cb_config); |
| 2394 | assert_fw_entry(combo_index, MAX_COMBO_ENTRIES, &ctx); |
| 2395 | bhd_combo_dir->entries[combo_index].id_sel = 0; |
| 2396 | bhd_combo_dir->entries[combo_index].id = |
| 2397 | get_psp_id(cb_config.soc_id); |
| 2398 | bhd_combo_dir->entries[combo_index].lvl2_addr = |
| 2399 | BUFF_TO_RUN_MODE(ctx, biosdir, AMD_ADDR_REL_BIOS); |
| 2400 | |
| 2401 | fill_dir_header(bhd_combo_dir, combo_index + 1, |
| 2402 | BHD2_COOKIE, &ctx); |
| 2403 | } |
| 2404 | } |
Zheng Bao | 17551ae | 2023-03-11 10:29:56 +0800 | [diff] [blame] | 2405 | } while (cb_config.use_combo && ++combo_index < MAX_COMBO_ENTRIES && |
| 2406 | combo_config[combo_index] != NULL); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 2407 | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 2408 | targetfd = open(output, O_RDWR | O_CREAT | O_TRUNC, 0666); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 2409 | if (targetfd >= 0) { |
Zheng Bao | 69ea83c | 2023-01-22 21:08:18 +0800 | [diff] [blame] | 2410 | uint32_t offset = efs_location; |
| 2411 | uint32_t bytes = efs_location == body_location ? |
| 2412 | ctx.current - offset : sizeof(*amd_romsig); |
| 2413 | uint32_t ret_bytes; |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 2414 | |
Zheng Bao | c25d593 | 2023-03-22 12:51:47 +0800 | [diff] [blame] | 2415 | ret_bytes = write_from_buf_to_file(targetfd, BUFF_OFFSET(ctx, offset), bytes); |
Zheng Bao | 69ea83c | 2023-01-22 21:08:18 +0800 | [diff] [blame] | 2416 | if (bytes != ret_bytes) { |
Zheng Bao | 4739691 | 2020-09-29 17:33:17 +0800 | [diff] [blame] | 2417 | fprintf(stderr, "Error: Writing to file %s failed\n", output); |
| 2418 | retval = 1; |
| 2419 | } |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 2420 | close(targetfd); |
| 2421 | } else { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 2422 | fprintf(stderr, "Error: could not open file: %s\n", output); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 2423 | retval = 1; |
| 2424 | } |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 2425 | |
Zheng Bao | 99945dc | 2023-01-02 10:55:56 +0800 | [diff] [blame] | 2426 | if (efs_location != body_location) { |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 2427 | ssize_t bytes; |
| 2428 | |
Zheng Bao | 69ea83c | 2023-01-22 21:08:18 +0800 | [diff] [blame] | 2429 | bytes = write_body(output, BUFF_OFFSET(ctx, body_location), |
| 2430 | ctx.current - body_location, &ctx); |
| 2431 | if (bytes != ctx.current - body_location) { |
| 2432 | fprintf(stderr, "Error: Writing body\n"); |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 2433 | retval = 1; |
| 2434 | } |
| 2435 | } |
| 2436 | |
Zheng Bao | 7c5ad88 | 2023-02-19 13:02:52 +0800 | [diff] [blame] | 2437 | amdfwtool_cleanup(&ctx); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 2438 | return retval; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 2439 | } |