Patrick Georgi | 7333a11 | 2020-05-08 20:48:04 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 2 | |
| 3 | /* |
| 4 | * ROMSIG At ROMBASE + 0x20000: |
zbao | c3b0b72 | 2016-02-19 13:47:31 +0800 | [diff] [blame] | 5 | * 0 4 8 C |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 6 | * +------------+---------------+----------------+------------+ |
| 7 | * | 0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM | |
| 8 | * +------------+---------------+----------------+------------+ |
zbao | c3b0b72 | 2016-02-19 13:47:31 +0800 | [diff] [blame] | 9 | * | PSPDIR ADDR|PSPDIR ADDR |<-- Field 0x14 could be either |
| 10 | * +------------+---------------+ 2nd PSP directory or PSP COMBO directory |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 11 | * EC ROM should be 64K aligned. |
| 12 | * |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 13 | * PSP directory (Where "PSPDIR ADDR" points) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 14 | * +------------+---------------+----------------+------------+ |
| 15 | * | 'PSP$' | Fletcher | Count | Reserved | |
| 16 | * +------------+---------------+----------------+------------+ |
| 17 | * | 0 | size | Base address | Reserved | Pubkey |
| 18 | * +------------+---------------+----------------+------------+ |
| 19 | * | 1 | size | Base address | Reserved | Bootloader |
| 20 | * +------------+---------------+----------------+------------+ |
| 21 | * | 8 | size | Base address | Reserved | Smu Firmware |
| 22 | * +------------+---------------+----------------+------------+ |
| 23 | * | 3 | size | Base address | Reserved | Recovery Firmware |
| 24 | * +------------+---------------+----------------+------------+ |
| 25 | * | | |
| 26 | * | | |
| 27 | * | Other PSP Firmware | |
| 28 | * | | |
| 29 | * | | |
| 30 | * +------------+---------------+----------------+------------+ |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 31 | * |
zbao | c3b0b72 | 2016-02-19 13:47:31 +0800 | [diff] [blame] | 32 | * PSP Combo directory |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 33 | * +------------+---------------+----------------+------------+ |
zbao | 6e2f3d1 | 2016-02-19 13:34:59 +0800 | [diff] [blame] | 34 | * | 'PSP2' | Fletcher | Count |Look up mode| |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 35 | * +------------+---------------+----------------+------------+ |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 36 | * | R e s e r v e d | |
| 37 | * +------------+---------------+----------------+------------+ |
zbao | 6e2f3d1 | 2016-02-19 13:34:59 +0800 | [diff] [blame] | 38 | * | ID-Sel | PSP ID | PSPDIR ADDR | | 2nd PSP directory |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 39 | * +------------+---------------+----------------+------------+ |
zbao | 6e2f3d1 | 2016-02-19 13:34:59 +0800 | [diff] [blame] | 40 | * | ID-Sel | PSP ID | PSPDIR ADDR | | 3rd PSP directory |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 41 | * +------------+---------------+----------------+------------+ |
| 42 | * | | |
| 43 | * | Other PSP | |
| 44 | * | | |
| 45 | * +------------+---------------+----------------+------------+ |
| 46 | * |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 47 | */ |
| 48 | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 49 | #include <fcntl.h> |
| 50 | #include <errno.h> |
Martin Roth | 37305e7 | 2020-04-07 14:16:39 -0600 | [diff] [blame] | 51 | #include <stdbool.h> |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 52 | #include <stdio.h> |
| 53 | #include <sys/stat.h> |
| 54 | #include <sys/types.h> |
| 55 | #include <unistd.h> |
| 56 | #include <string.h> |
| 57 | #include <stdlib.h> |
| 58 | #include <getopt.h> |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 59 | #include <libgen.h> |
Idwer Vollering | 93df1d9 | 2020-12-30 00:01:59 +0100 | [diff] [blame] | 60 | #include <stdint.h> |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 61 | |
| 62 | #include "amdfwtool.h" |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 63 | |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 64 | #define AMD_ROMSIG_OFFSET 0x20000 |
| 65 | #define MIN_ROM_KB 256 |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 66 | |
Martin Roth | cd15bc8 | 2016-11-08 11:34:02 -0700 | [diff] [blame] | 67 | #define ALIGN(val, by) (((val) + (by) - 1) & ~((by) - 1)) |
Marshall Dawson | 7c1e142 | 2019-04-11 09:44:43 -0600 | [diff] [blame] | 68 | #define _MAX(A, B) (((A) > (B)) ? (A) : (B)) |
| 69 | #define ERASE_ALIGNMENT 0x1000U |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 70 | #define TABLE_ALIGNMENT 0x1000U |
| 71 | #define BLOB_ALIGNMENT 0x100U |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 72 | #define TABLE_ERASE_ALIGNMENT _MAX(TABLE_ALIGNMENT, ERASE_ALIGNMENT) |
Marshall Dawson | 7c1e142 | 2019-04-11 09:44:43 -0600 | [diff] [blame] | 73 | #define BLOB_ERASE_ALIGNMENT _MAX(BLOB_ALIGNMENT, ERASE_ALIGNMENT) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 74 | |
Marshall Dawson | ef79fcc | 2019-04-01 10:16:41 -0600 | [diff] [blame] | 75 | #define DEFAULT_SOFT_FUSE_CHAIN "0x1" |
| 76 | |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 77 | #define EMBEDDED_FW_SIGNATURE 0x55aa55aa |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 78 | #define PSP_COOKIE 0x50535024 /* 'PSP$' */ |
| 79 | #define PSPL2_COOKIE 0x324c5024 /* '2LP$' */ |
| 80 | #define PSP2_COOKIE 0x50535032 /* 'PSP2' */ |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 81 | #define BDT1_COOKIE 0x44484224 /* 'DHB$ */ |
| 82 | #define BDT2_COOKIE 0x324c4224 /* '2LB$ */ |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 83 | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 84 | /* |
Marshall Dawson | 0e02ce8 | 2019-03-04 16:50:37 -0700 | [diff] [blame] | 85 | * Beginning with Family 15h Models 70h-7F, a.k.a Stoney Ridge, the PSP |
| 86 | * can support an optional "combo" implementation. If the PSP sees the |
| 87 | * PSP2 cookie, it interprets the table as a roadmap to additional PSP |
| 88 | * tables. Using this, support for multiple product generations may be |
| 89 | * built into one image. If the PSP$ cookie is found, the table is a |
| 90 | * normal directory table. |
| 91 | * |
| 92 | * Modern generations supporting the combo directories require the |
| 93 | * pointer to be at offset 0x14 of the Embedded Firmware Structure, |
| 94 | * regardless of the type of directory used. The --combo-capable |
| 95 | * argument enforces this placement. |
| 96 | * |
| 97 | * TODO: Future work may require fully implementing the PSP_COMBO feature. |
zbao | c3b0b72 | 2016-02-19 13:47:31 +0800 | [diff] [blame] | 98 | */ |
Marshall Dawson | 0e02ce8 | 2019-03-04 16:50:37 -0700 | [diff] [blame] | 99 | #define PSP_COMBO 0 |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 100 | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 101 | /* |
| 102 | * Creates the OSI Fletcher checksum. See 8473-1, Appendix C, section C.3. |
| 103 | * The checksum field of the passed PDU does not need to be reset to zero. |
| 104 | * |
| 105 | * The "Fletcher Checksum" was proposed in a paper by John G. Fletcher of |
| 106 | * Lawrence Livermore Labs. The Fletcher Checksum was proposed as an |
| 107 | * alternative to cyclical redundancy checks because it provides error- |
| 108 | * detection properties similar to cyclical redundancy checks but at the |
| 109 | * cost of a simple summation technique. Its characteristics were first |
| 110 | * published in IEEE Transactions on Communications in January 1982. One |
| 111 | * version has been adopted by ISO for use in the class-4 transport layer |
| 112 | * of the network protocol. |
| 113 | * |
| 114 | * This program expects: |
| 115 | * stdin: The input file to compute a checksum for. The input file |
| 116 | * not be longer than 256 bytes. |
| 117 | * stdout: Copied from the input file with the Fletcher's Checksum |
| 118 | * inserted 8 bytes after the beginning of the file. |
| 119 | * stderr: Used to print out error messages. |
| 120 | */ |
Marshall Dawson | 8a45a4d | 2019-02-24 07:18:44 -0700 | [diff] [blame] | 121 | static uint32_t fletcher32(const void *data, int length) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 122 | { |
| 123 | uint32_t c0; |
| 124 | uint32_t c1; |
| 125 | uint32_t checksum; |
| 126 | int index; |
Marshall Dawson | 8a45a4d | 2019-02-24 07:18:44 -0700 | [diff] [blame] | 127 | const uint16_t *pptr = data; |
| 128 | |
| 129 | length /= 2; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 130 | |
| 131 | c0 = 0xFFFF; |
| 132 | c1 = 0xFFFF; |
| 133 | |
Marshall Dawson | b85ddc5 | 2019-07-23 07:24:30 -0600 | [diff] [blame] | 134 | while (length) { |
| 135 | index = length >= 359 ? 359 : length; |
| 136 | length -= index; |
| 137 | do { |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 138 | c0 += *(pptr++); |
| 139 | c1 += c0; |
Marshall Dawson | b85ddc5 | 2019-07-23 07:24:30 -0600 | [diff] [blame] | 140 | } while (--index); |
| 141 | c0 = (c0 & 0xFFFF) + (c0 >> 16); |
| 142 | c1 = (c1 & 0xFFFF) + (c1 >> 16); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 143 | } |
| 144 | |
Marshall Dawson | 8a45a4d | 2019-02-24 07:18:44 -0700 | [diff] [blame] | 145 | /* Sums[0,1] mod 64K + overflow */ |
| 146 | c0 = (c0 & 0xFFFF) + (c0 >> 16); |
| 147 | c1 = (c1 & 0xFFFF) + (c1 >> 16); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 148 | checksum = (c1 << 16) | c0; |
| 149 | |
| 150 | return checksum; |
| 151 | } |
| 152 | |
Martin Roth | 8806f7f | 2016-11-08 10:44:18 -0700 | [diff] [blame] | 153 | static void usage(void) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 154 | { |
Martin Roth | 0e94062 | 2016-11-08 10:37:53 -0700 | [diff] [blame] | 155 | printf("amdfwtool: Create AMD Firmware combination\n"); |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 156 | printf("Usage: amdfwtool [options] --flashsize <size> --output <filename>\n"); |
| 157 | printf("--xhci <FILE> Add XHCI blob\n"); |
| 158 | printf("--imc <FILE> Add IMC blob\n"); |
| 159 | printf("--gec <FILE> Add GEC blob\n"); |
Martin Roth | 0e94062 | 2016-11-08 10:37:53 -0700 | [diff] [blame] | 160 | |
| 161 | printf("\nPSP options:\n"); |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 162 | printf("--combo-capable Place PSP directory pointer at Embedded\n"); |
| 163 | printf(" Firmware\n"); |
Marshall Dawson | 67d868d | 2019-02-28 11:43:40 -0700 | [diff] [blame] | 164 | printf(" offset able to support combo directory\n"); |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 165 | printf("--multilevel Generate primary and secondary tables\n"); |
| 166 | printf("--nvram <FILE> Add nvram binary\n"); |
| 167 | printf("--soft-fuse Set soft fuse\n"); |
| 168 | printf("--token-unlock Set token unlock\n"); |
| 169 | printf("--whitelist Set if there is a whitelist\n"); |
| 170 | printf("--use-pspsecureos Set if psp secure OS is needed\n"); |
| 171 | printf("--load-mp2-fw Set if load MP2 firmware\n"); |
| 172 | printf("--load-s0i3 Set if load s0i3 firmware\n"); |
| 173 | printf("--verstage <FILE> Add verstage\n"); |
| 174 | printf("--verstage_sig Add verstage signature\n"); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 175 | printf("\nBIOS options:\n"); |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 176 | printf("--instance <number> Sets instance field for the next BIOS\n"); |
Zheng Bao | 6f0b361 | 2021-04-27 17:19:43 +0800 | [diff] [blame] | 177 | printf(" firmware\n"); |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 178 | printf("--apcb <FILE> Add AGESA PSP customization block\n"); |
| 179 | printf("--apob-base <HEX_VAL> Destination for AGESA PSP output block\n"); |
| 180 | printf("--apob-nv-base <HEX_VAL> Location of S3 resume data\n"); |
| 181 | printf("--apob-nv-size <HEX_VAL> Size of S3 resume data\n"); |
| 182 | printf("--ucode <FILE> Add microcode patch\n"); |
| 183 | printf("--bios-bin <FILE> Add compressed image; auto source address\n"); |
| 184 | printf("--bios-bin-src <HEX_VAL> Address in flash of source if -V not used\n"); |
| 185 | printf("--bios-bin-dest <HEX_VAL> Destination for uncompressed BIOS\n"); |
| 186 | printf("--bios-uncomp-size <HEX> Uncompressed size of BIOS image\n"); |
| 187 | printf("--output <filename> output filename\n"); |
| 188 | printf("--flashsize <HEX_VAL> ROM size in bytes\n"); |
Marshall Dawson | f4b9b41 | 2017-03-17 16:30:51 -0600 | [diff] [blame] | 189 | printf(" size must be larger than %dKB\n", |
Martin Roth | 0e94062 | 2016-11-08 10:37:53 -0700 | [diff] [blame] | 190 | MIN_ROM_KB); |
Marshall Dawson | f4b9b41 | 2017-03-17 16:30:51 -0600 | [diff] [blame] | 191 | printf(" and must a multiple of 1024\n"); |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 192 | printf("--location Location of Directory\n"); |
| 193 | printf("--anywhere Use any 64-byte aligned addr for Directory\n"); |
| 194 | printf("--sharedmem Location of PSP/FW shared memory\n"); |
| 195 | printf("--sharedmem-size Maximum size of the PSP/FW shared memory\n"); |
Zheng Bao | 6f0b361 | 2021-04-27 17:19:43 +0800 | [diff] [blame] | 196 | printf(" area\n"); |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 197 | printf("--soc-name <socname> Specify SOC name. Supported names are\n"); |
Zheng Bao | 6f0b361 | 2021-04-27 17:19:43 +0800 | [diff] [blame] | 198 | printf(" Stoneyridge, Raven, Picasso, Renoir, Cezanne\n"); |
| 199 | printf(" or Lucienne\n"); |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 200 | printf("\nEmbedded Firmware Structure options used by the PSP:\n"); |
| 201 | printf("--spi-speed <HEX_VAL> SPI fast speed to place in EFS Table\n"); |
| 202 | printf(" 0x0 66.66Mhz\n"); |
| 203 | printf(" 0x1 33.33MHz\n"); |
| 204 | printf(" 0x2 22.22MHz\n"); |
| 205 | printf(" 0x3 16.66MHz\n"); |
| 206 | printf(" 0x4 100MHz\n"); |
| 207 | printf(" 0x5 800KHz\n"); |
| 208 | printf("--spi-read-mode <HEX_VAL> SPI read mode to place in EFS Table\n"); |
| 209 | printf(" 0x0 Normal Read (up to 33M)\n"); |
| 210 | printf(" 0x1 Reserved\n"); |
| 211 | printf(" 0x2 Dual IO (1-1-2)\n"); |
| 212 | printf(" 0x3 Quad IO (1-1-4)\n"); |
| 213 | printf(" 0x4 Dual IO (1-2-2)\n"); |
| 214 | printf(" 0x5 Quad IO (1-4-4)\n"); |
| 215 | printf(" 0x6 Normal Read (up to 66M)\n"); |
| 216 | printf(" 0x7 Fast Read\n"); |
| 217 | printf("--spi-micron-flag <HEX_VAL> Micron SPI part support for RV and later SOC\n"); |
| 218 | printf(" 0x0 Micron parts are not used\n"); |
| 219 | printf(" 0x1 Micron parts are always used\n"); |
| 220 | printf(" 0x2 Micron parts optional, this option is only\n"); |
| 221 | printf(" supported with RN/LCN SOC\n"); |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 222 | printf("\nGeneral options:\n"); |
| 223 | printf("-c|--config <config file> Config file\n"); |
| 224 | printf("-d|--debug Print debug message\n"); |
| 225 | printf("-l|--list List out the firmware files\n"); |
| 226 | printf("-h|--help Show this help\n"); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 227 | } |
| 228 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 229 | amd_fw_entry amd_psp_fw_table[] = { |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 230 | { .type = AMD_FW_PSP_PUBKEY, .level = PSP_BOTH }, |
| 231 | { .type = AMD_FW_PSP_BOOTLOADER, .level = PSP_BOTH }, |
| 232 | { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 0, .level = PSP_BOTH }, |
| 233 | { .type = AMD_FW_PSP_RECOVERY, .level = PSP_LVL1 }, |
| 234 | { .type = AMD_FW_PSP_RTM_PUBKEY, .level = PSP_BOTH }, |
| 235 | { .type = AMD_FW_PSP_SECURED_OS, .level = PSP_LVL2 }, |
| 236 | { .type = AMD_FW_PSP_NVRAM, .level = PSP_LVL2 }, |
| 237 | { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 2, .level = PSP_BOTH }, |
| 238 | { .type = AMD_FW_PSP_SECURED_DEBUG, .level = PSP_LVL2 }, |
| 239 | { .type = AMD_FW_PSP_TRUSTLETS, .level = PSP_LVL2 }, |
| 240 | { .type = AMD_FW_PSP_TRUSTLETKEY, .level = PSP_LVL2 }, |
| 241 | { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 2, .level = PSP_BOTH }, |
| 242 | { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH }, |
| 243 | { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH }, |
| 244 | { .type = AMD_FW_PSP_SMU_FIRMWARE2, .level = PSP_BOTH }, |
| 245 | { .type = AMD_FW_PSP_SMUSCS, .level = PSP_BOTH }, |
| 246 | { .type = AMD_PSP_FUSE_CHAIN, .level = PSP_LVL2 }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 247 | { .type = AMD_DEBUG_UNLOCK, .level = PSP_LVL2 }, |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 248 | { .type = AMD_HW_IPCFG, .level = PSP_LVL2 }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 249 | { .type = AMD_WRAPPED_IKEK, .level = PSP_BOTH }, |
| 250 | { .type = AMD_TOKEN_UNLOCK, .level = PSP_BOTH }, |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 251 | { .type = AMD_SEC_GASKET, .subprog = 0, .level = PSP_BOTH }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 252 | { .type = AMD_SEC_GASKET, .subprog = 2, .level = PSP_BOTH }, |
| 253 | { .type = AMD_SEC_GASKET, .subprog = 1, .level = PSP_BOTH }, |
| 254 | { .type = AMD_MP2_FW, .subprog = 2, .level = PSP_LVL2 }, |
| 255 | { .type = AMD_MP2_FW, .subprog = 1, .level = PSP_LVL2 }, |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 256 | { .type = AMD_MP2_FW, .subprog = 0, .level = PSP_LVL2 }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 257 | { .type = AMD_DRIVER_ENTRIES, .level = PSP_LVL2 }, |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 258 | { .type = AMD_FW_KVM_IMAGE, .level = PSP_LVL2}, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 259 | { .type = AMD_S0I3_DRIVER, .level = PSP_LVL2 }, |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 260 | { .type = AMD_VBIOS_BTLOADER, .level = PSP_BOTH }, |
| 261 | { .type = AMD_FW_TOS_SEC_POLICY, .level = PSP_BOTH }, |
| 262 | { .type = AMD_FW_USB_PHY, .level = PSP_LVL2 }, |
| 263 | { .type = AMD_FW_DRTM_TA, .level = PSP_LVL2 }, |
| 264 | { .type = AMD_FW_KEYDB_BL, .level = PSP_BOTH }, |
| 265 | { .type = AMD_FW_KEYDB_TOS, .level = PSP_LVL2 }, |
| 266 | { .type = AMD_FW_DMCU_ERAM, .level = PSP_LVL2 }, |
| 267 | { .type = AMD_FW_DMCU_ISR, .level = PSP_LVL2 }, |
| 268 | { .type = AMD_RPMC_NVRAM, .level = PSP_LVL2 }, |
Zheng Bao | b993cb2 | 2021-02-02 18:48:23 +0800 | [diff] [blame] | 269 | { .type = AMD_FW_PSP_BOOTLOADER_AB, .level = PSP_LVL2 }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 270 | { .type = AMD_ABL0, .level = PSP_BOTH }, |
| 271 | { .type = AMD_ABL1, .level = PSP_BOTH }, |
| 272 | { .type = AMD_ABL2, .level = PSP_BOTH }, |
| 273 | { .type = AMD_ABL3, .level = PSP_BOTH }, |
| 274 | { .type = AMD_ABL4, .level = PSP_BOTH }, |
| 275 | { .type = AMD_ABL5, .level = PSP_BOTH }, |
| 276 | { .type = AMD_ABL6, .level = PSP_BOTH }, |
| 277 | { .type = AMD_ABL7, .level = PSP_BOTH }, |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 278 | { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH }, |
| 279 | { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 280 | { .type = AMD_FW_PSP_WHITELIST, .level = PSP_LVL2 }, |
Martin Roth | d3ce8c8 | 2019-07-13 20:13:07 -0600 | [diff] [blame] | 281 | { .type = AMD_FW_PSP_VERSTAGE, .level = PSP_BOTH }, |
Martin Roth | b1f648f | 2020-09-01 09:36:59 -0600 | [diff] [blame] | 282 | { .type = AMD_FW_VERSTAGE_SIG, .level = PSP_BOTH }, |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 283 | { .type = AMD_FW_INVALID }, |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 284 | }; |
| 285 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 286 | amd_fw_entry amd_fw_table[] = { |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 287 | { .type = AMD_FW_XHCI }, |
| 288 | { .type = AMD_FW_IMC }, |
| 289 | { .type = AMD_FW_GEC }, |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 290 | { .type = AMD_FW_INVALID }, |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 291 | }; |
| 292 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 293 | amd_bios_entry amd_bios_table[] = { |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 294 | { .type = AMD_BIOS_RTM_PUBKEY, .inst = 0, .level = BDT_BOTH }, |
Marshall Dawson | 0581bf6 | 2019-09-25 11:03:53 -0600 | [diff] [blame] | 295 | { .type = AMD_BIOS_APCB, .inst = 0, .level = BDT_BOTH }, |
| 296 | { .type = AMD_BIOS_APCB, .inst = 1, .level = BDT_BOTH }, |
| 297 | { .type = AMD_BIOS_APCB, .inst = 2, .level = BDT_BOTH }, |
| 298 | { .type = AMD_BIOS_APCB, .inst = 3, .level = BDT_BOTH }, |
| 299 | { .type = AMD_BIOS_APCB, .inst = 4, .level = BDT_BOTH }, |
Rob Barnes | 18fd26c | 2020-03-03 10:35:02 -0700 | [diff] [blame] | 300 | { .type = AMD_BIOS_APCB, .inst = 5, .level = BDT_BOTH }, |
| 301 | { .type = AMD_BIOS_APCB, .inst = 6, .level = BDT_BOTH }, |
| 302 | { .type = AMD_BIOS_APCB, .inst = 7, .level = BDT_BOTH }, |
| 303 | { .type = AMD_BIOS_APCB, .inst = 8, .level = BDT_BOTH }, |
| 304 | { .type = AMD_BIOS_APCB, .inst = 9, .level = BDT_BOTH }, |
| 305 | { .type = AMD_BIOS_APCB, .inst = 10, .level = BDT_BOTH }, |
| 306 | { .type = AMD_BIOS_APCB, .inst = 11, .level = BDT_BOTH }, |
| 307 | { .type = AMD_BIOS_APCB, .inst = 12, .level = BDT_BOTH }, |
| 308 | { .type = AMD_BIOS_APCB, .inst = 13, .level = BDT_BOTH }, |
| 309 | { .type = AMD_BIOS_APCB, .inst = 14, .level = BDT_BOTH }, |
| 310 | { .type = AMD_BIOS_APCB, .inst = 15, .level = BDT_BOTH }, |
Marshall Dawson | 2dd3b5c | 2020-01-03 17:57:48 -0700 | [diff] [blame] | 311 | { .type = AMD_BIOS_APCB_BK, .inst = 0, .level = BDT_BOTH }, |
| 312 | { .type = AMD_BIOS_APCB_BK, .inst = 1, .level = BDT_BOTH }, |
| 313 | { .type = AMD_BIOS_APCB_BK, .inst = 2, .level = BDT_BOTH }, |
| 314 | { .type = AMD_BIOS_APCB_BK, .inst = 3, .level = BDT_BOTH }, |
| 315 | { .type = AMD_BIOS_APCB_BK, .inst = 4, .level = BDT_BOTH }, |
Rob Barnes | 18fd26c | 2020-03-03 10:35:02 -0700 | [diff] [blame] | 316 | { .type = AMD_BIOS_APCB_BK, .inst = 5, .level = BDT_BOTH }, |
| 317 | { .type = AMD_BIOS_APCB_BK, .inst = 6, .level = BDT_BOTH }, |
| 318 | { .type = AMD_BIOS_APCB_BK, .inst = 7, .level = BDT_BOTH }, |
| 319 | { .type = AMD_BIOS_APCB_BK, .inst = 8, .level = BDT_BOTH }, |
| 320 | { .type = AMD_BIOS_APCB_BK, .inst = 9, .level = BDT_BOTH }, |
| 321 | { .type = AMD_BIOS_APCB_BK, .inst = 10, .level = BDT_BOTH }, |
| 322 | { .type = AMD_BIOS_APCB_BK, .inst = 11, .level = BDT_BOTH }, |
| 323 | { .type = AMD_BIOS_APCB_BK, .inst = 12, .level = BDT_BOTH }, |
| 324 | { .type = AMD_BIOS_APCB_BK, .inst = 13, .level = BDT_BOTH }, |
| 325 | { .type = AMD_BIOS_APCB_BK, .inst = 14, .level = BDT_BOTH }, |
| 326 | { .type = AMD_BIOS_APCB_BK, .inst = 15, .level = BDT_BOTH }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 327 | { .type = AMD_BIOS_APOB, .level = BDT_BOTH }, |
| 328 | { .type = AMD_BIOS_BIN, |
| 329 | .reset = 1, .copy = 1, .zlib = 1, .level = BDT_BOTH }, |
| 330 | { .type = AMD_BIOS_APOB_NV, .level = BDT_LVL2 }, |
| 331 | { .type = AMD_BIOS_PMUI, .inst = 1, .subpr = 0, .level = BDT_BOTH }, |
| 332 | { .type = AMD_BIOS_PMUD, .inst = 1, .subpr = 0, .level = BDT_BOTH }, |
| 333 | { .type = AMD_BIOS_PMUI, .inst = 4, .subpr = 0, .level = BDT_BOTH }, |
| 334 | { .type = AMD_BIOS_PMUD, .inst = 4, .subpr = 0, .level = BDT_BOTH }, |
| 335 | { .type = AMD_BIOS_PMUI, .inst = 1, .subpr = 1, .level = BDT_BOTH }, |
| 336 | { .type = AMD_BIOS_PMUD, .inst = 1, .subpr = 1, .level = BDT_BOTH }, |
| 337 | { .type = AMD_BIOS_PMUI, .inst = 4, .subpr = 1, .level = BDT_BOTH }, |
| 338 | { .type = AMD_BIOS_PMUD, .inst = 4, .subpr = 1, .level = BDT_BOTH }, |
| 339 | { .type = AMD_BIOS_UCODE, .inst = 0, .level = BDT_LVL2 }, |
| 340 | { .type = AMD_BIOS_UCODE, .inst = 1, .level = BDT_LVL2 }, |
| 341 | { .type = AMD_BIOS_UCODE, .inst = 2, .level = BDT_LVL2 }, |
| 342 | { .type = AMD_BIOS_MP2_CFG, .level = BDT_LVL2 }, |
Martin Roth | 9455474 | 2020-04-14 14:59:36 -0600 | [diff] [blame] | 343 | { .type = AMD_BIOS_PSP_SHARED_MEM, .inst = 0, .level = BDT_BOTH }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 344 | { .type = AMD_BIOS_INVALID }, |
| 345 | }; |
| 346 | |
Marshall Dawson | 13ec029 | 2020-11-19 14:02:29 -0700 | [diff] [blame] | 347 | struct second_gen_efs { /* todo: expand for Server products */ |
| 348 | int gen:1; /* Client products only use bit 0 */ |
| 349 | int reserved:31; |
| 350 | } __attribute__((packed)); |
| 351 | |
| 352 | #define EFS_SECOND_GEN 0 |
| 353 | |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 354 | typedef struct _embedded_firmware { |
| 355 | uint32_t signature; /* 0x55aa55aa */ |
| 356 | uint32_t imc_entry; |
| 357 | uint32_t gec_entry; |
| 358 | uint32_t xhci_entry; |
| 359 | uint32_t psp_entry; |
| 360 | uint32_t comboable; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 361 | uint32_t bios0_entry; /* todo: add way to select correct entry */ |
| 362 | uint32_t bios1_entry; |
Marshall Dawson | 94f2492 | 2019-09-28 08:49:09 -0600 | [diff] [blame] | 363 | uint32_t bios2_entry; |
Marshall Dawson | 13ec029 | 2020-11-19 14:02:29 -0700 | [diff] [blame] | 364 | struct second_gen_efs efs_gen; |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 365 | uint32_t bios3_entry; |
| 366 | uint32_t reserved_2Ch; |
| 367 | uint32_t promontory_fw_ptr; |
| 368 | uint32_t lp_promontory_fw_ptr; |
| 369 | uint32_t reserved_38h; |
| 370 | uint32_t reserved_3Ch; |
| 371 | uint8_t spi_readmode_f15_mod_60_6f; |
| 372 | uint8_t fast_speed_new_f15_mod_60_6f; |
| 373 | uint8_t reserved_42h; |
| 374 | uint8_t spi_readmode_f17_mod_00_2f; |
| 375 | uint8_t spi_fastspeed_f17_mod_00_2f; |
| 376 | uint8_t qpr_dummy_cycle_f17_mod_00_2f; |
| 377 | uint8_t reserved_46h; |
| 378 | uint8_t spi_readmode_f17_mod_30_3f; |
| 379 | uint8_t spi_fastspeed_f17_mod_30_3f; |
| 380 | uint8_t micron_detect_f17_mod_30_3f; |
| 381 | uint8_t reserved_4Ah; |
| 382 | uint8_t reserved_4Bh; |
| 383 | uint32_t reserved_4Ch; |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 384 | } __attribute__((packed, aligned(16))) embedded_firmware; |
| 385 | |
| 386 | typedef struct _psp_directory_header { |
| 387 | uint32_t cookie; |
| 388 | uint32_t checksum; |
| 389 | uint32_t num_entries; |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 390 | uint32_t additional_info; |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 391 | } __attribute__((packed, aligned(16))) psp_directory_header; |
| 392 | |
| 393 | typedef struct _psp_directory_entry { |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 394 | uint8_t type; |
| 395 | uint8_t subprog; |
| 396 | uint16_t rsvd; |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 397 | uint32_t size; |
| 398 | uint64_t addr; /* or a value in some cases */ |
| 399 | } __attribute__((packed)) psp_directory_entry; |
| 400 | |
| 401 | typedef struct _psp_directory_table { |
| 402 | psp_directory_header header; |
| 403 | psp_directory_entry entries[]; |
Martin Roth | a8e31ca | 2021-02-13 21:42:46 -0700 | [diff] [blame] | 404 | } __attribute__((packed, aligned(16))) psp_directory_table; |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 405 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 406 | #define MAX_PSP_ENTRIES 0x1f |
| 407 | |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 408 | typedef struct _psp_combo_header { |
| 409 | uint32_t cookie; |
| 410 | uint32_t checksum; |
| 411 | uint32_t num_entries; |
| 412 | uint32_t lookup; |
| 413 | uint64_t reserved[2]; |
| 414 | } __attribute__((packed, aligned(16))) psp_combo_header; |
| 415 | |
| 416 | typedef struct _psp_combo_entry { |
| 417 | uint32_t id_sel; |
| 418 | uint32_t id; |
| 419 | uint64_t lvl2_addr; |
| 420 | } __attribute__((packed)) psp_combo_entry; |
| 421 | |
| 422 | typedef struct _psp_combo_directory { |
| 423 | psp_combo_header header; |
| 424 | psp_combo_entry entries[]; |
Martin Roth | a8e31ca | 2021-02-13 21:42:46 -0700 | [diff] [blame] | 425 | } __attribute__((packed, aligned(16))) psp_combo_directory; |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 426 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 427 | #define MAX_COMBO_ENTRIES 1 |
| 428 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 429 | typedef struct _bios_directory_hdr { |
| 430 | uint32_t cookie; |
| 431 | uint32_t checksum; |
| 432 | uint32_t num_entries; |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 433 | uint32_t additional_info; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 434 | } __attribute__((packed, aligned(16))) bios_directory_hdr; |
| 435 | |
| 436 | typedef struct _bios_directory_entry { |
| 437 | uint8_t type; |
| 438 | uint8_t region_type; |
| 439 | int reset:1; |
| 440 | int copy:1; |
| 441 | int ro:1; |
| 442 | int compressed:1; |
| 443 | int inst:4; |
| 444 | uint8_t subprog; /* b[7:3] reserved */ |
| 445 | uint32_t size; |
| 446 | uint64_t source; |
| 447 | uint64_t dest; |
| 448 | } __attribute__((packed)) bios_directory_entry; |
| 449 | |
| 450 | typedef struct _bios_directory_table { |
| 451 | bios_directory_hdr header; |
| 452 | bios_directory_entry entries[]; |
| 453 | } bios_directory_table; |
| 454 | |
Martin Roth | 9455474 | 2020-04-14 14:59:36 -0600 | [diff] [blame] | 455 | #define MAX_BIOS_ENTRIES 0x2f |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 456 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 457 | typedef struct _context { |
| 458 | char *rom; /* target buffer, size of flash device */ |
| 459 | uint32_t rom_size; /* size of flash device */ |
| 460 | uint32_t current; /* pointer within flash & proxy buffer */ |
| 461 | } context; |
| 462 | |
| 463 | #define RUN_BASE(ctx) (0xFFFFFFFF - (ctx).rom_size + 1) |
| 464 | #define RUN_OFFSET(ctx, offset) (RUN_BASE(ctx) + (offset)) |
| 465 | #define RUN_CURRENT(ctx) RUN_OFFSET((ctx), (ctx).current) |
| 466 | #define BUFF_OFFSET(ctx, offset) ((void *)((ctx).rom + (offset))) |
| 467 | #define BUFF_CURRENT(ctx) BUFF_OFFSET((ctx), (ctx).current) |
| 468 | #define BUFF_TO_RUN(ctx, ptr) RUN_OFFSET((ctx), ((char *)(ptr) - (ctx).rom)) |
| 469 | #define BUFF_ROOM(ctx) ((ctx).rom_size - (ctx).current) |
| 470 | |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 471 | static void *new_psp_dir(context *ctx, int multi) |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 472 | { |
| 473 | void *ptr; |
| 474 | |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 475 | /* |
| 476 | * Force both onto boundary when multi. Primary table is after |
| 477 | * updatable table, so alignment ensures primary can stay intact |
| 478 | * if secondary is reprogrammed. |
| 479 | */ |
| 480 | if (multi) |
| 481 | ctx->current = ALIGN(ctx->current, TABLE_ERASE_ALIGNMENT); |
| 482 | else |
| 483 | ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT); |
| 484 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 485 | ptr = BUFF_CURRENT(*ctx); |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 486 | ((psp_directory_header *)ptr)->additional_info = ctx->current; |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 487 | ctx->current += sizeof(psp_directory_header) |
| 488 | + MAX_PSP_ENTRIES * sizeof(psp_directory_entry); |
| 489 | return ptr; |
| 490 | } |
| 491 | |
Martin Roth | ec93313 | 2019-07-13 20:03:34 -0600 | [diff] [blame] | 492 | #if PSP_COMBO |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 493 | static void *new_combo_dir(context *ctx) |
| 494 | { |
| 495 | void *ptr; |
| 496 | |
| 497 | ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT); |
| 498 | ptr = BUFF_CURRENT(*ctx); |
| 499 | ctx->current += sizeof(psp_combo_header) |
| 500 | + MAX_COMBO_ENTRIES * sizeof(psp_combo_entry); |
| 501 | return ptr; |
| 502 | } |
Martin Roth | ec93313 | 2019-07-13 20:03:34 -0600 | [diff] [blame] | 503 | #endif |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 504 | |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 505 | static void fill_dir_header(void *directory, uint32_t count, uint32_t cookie, context *ctx) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 506 | { |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 507 | psp_combo_directory *cdir = directory; |
| 508 | psp_directory_table *dir = directory; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 509 | bios_directory_table *bdir = directory; |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 510 | uint32_t table_size = 0; |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 511 | |
| 512 | if (!count) |
| 513 | return; |
| 514 | |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 515 | /* The table size needs to be 0x1000 aligned. So align the end of table. */ |
| 516 | if (ctx != NULL) |
| 517 | ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT); |
| 518 | |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 519 | switch (cookie) { |
| 520 | case PSP2_COOKIE: |
Marshall Dawson | a378c22 | 2019-03-04 16:52:07 -0700 | [diff] [blame] | 521 | /* caller is responsible for lookup mode */ |
Marshall Dawson | a378c22 | 2019-03-04 16:52:07 -0700 | [diff] [blame] | 522 | cdir->header.cookie = cookie; |
| 523 | cdir->header.num_entries = count; |
| 524 | cdir->header.reserved[0] = 0; |
| 525 | cdir->header.reserved[1] = 0; |
| 526 | /* checksum everything that comes after the Checksum field */ |
| 527 | cdir->header.checksum = fletcher32(&cdir->header.num_entries, |
| 528 | count * sizeof(psp_combo_entry) |
| 529 | + sizeof(cdir->header.num_entries) |
| 530 | + sizeof(cdir->header.lookup) |
| 531 | + 2 * sizeof(cdir->header.reserved[0])); |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 532 | break; |
| 533 | case PSP_COOKIE: |
| 534 | case PSPL2_COOKIE: |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 535 | table_size = ctx->current - dir->header.additional_info; |
| 536 | if ((table_size % TABLE_ALIGNMENT) != 0) { |
| 537 | fprintf(stderr, "The PSP table size should be 4K aligned\n"); |
| 538 | exit(1); |
| 539 | } |
Marshall Dawson | a378c22 | 2019-03-04 16:52:07 -0700 | [diff] [blame] | 540 | dir->header.cookie = cookie; |
| 541 | dir->header.num_entries = count; |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 542 | dir->header.additional_info = (table_size / 0x1000) | (1 << 10); |
Marshall Dawson | a378c22 | 2019-03-04 16:52:07 -0700 | [diff] [blame] | 543 | /* checksum everything that comes after the Checksum field */ |
| 544 | dir->header.checksum = fletcher32(&dir->header.num_entries, |
Marshall Dawson | 8a45a4d | 2019-02-24 07:18:44 -0700 | [diff] [blame] | 545 | count * sizeof(psp_directory_entry) |
Marshall Dawson | a378c22 | 2019-03-04 16:52:07 -0700 | [diff] [blame] | 546 | + sizeof(dir->header.num_entries) |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 547 | + sizeof(dir->header.additional_info)); |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 548 | break; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 549 | case BDT1_COOKIE: |
| 550 | case BDT2_COOKIE: |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 551 | table_size = ctx->current - bdir->header.additional_info; |
| 552 | if ((table_size % TABLE_ALIGNMENT) != 0) { |
| 553 | fprintf(stderr, "The BIOS table size should be 4K aligned\n"); |
| 554 | exit(1); |
| 555 | } |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 556 | bdir->header.cookie = cookie; |
| 557 | bdir->header.num_entries = count; |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 558 | bdir->header.additional_info = (table_size / 0x1000) | (1 << 10); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 559 | /* checksum everything that comes after the Checksum field */ |
| 560 | bdir->header.checksum = fletcher32(&bdir->header.num_entries, |
| 561 | count * sizeof(bios_directory_entry) |
| 562 | + sizeof(bdir->header.num_entries) |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 563 | + sizeof(bdir->header.additional_info)); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 564 | break; |
Marshall Dawson | a378c22 | 2019-03-04 16:52:07 -0700 | [diff] [blame] | 565 | } |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 566 | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 567 | } |
| 568 | |
Marshall Dawson | 8e0dca0 | 2019-02-27 18:40:49 -0700 | [diff] [blame] | 569 | static ssize_t copy_blob(void *dest, const char *src_file, size_t room) |
| 570 | { |
| 571 | int fd; |
| 572 | struct stat fd_stat; |
| 573 | ssize_t bytes; |
| 574 | |
| 575 | fd = open(src_file, O_RDONLY); |
| 576 | if (fd < 0) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 577 | fprintf(stderr, "Error opening file: %s: %s\n", |
Eric Peers | af50567 | 2020-03-05 16:04:15 -0700 | [diff] [blame] | 578 | src_file, strerror(errno)); |
Marshall Dawson | 8e0dca0 | 2019-02-27 18:40:49 -0700 | [diff] [blame] | 579 | return -1; |
| 580 | } |
| 581 | |
| 582 | if (fstat(fd, &fd_stat)) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 583 | fprintf(stderr, "fstat error: %s\n", strerror(errno)); |
Jacob Garber | 967f862 | 2019-07-02 10:35:10 -0600 | [diff] [blame] | 584 | close(fd); |
Marshall Dawson | 8e0dca0 | 2019-02-27 18:40:49 -0700 | [diff] [blame] | 585 | return -2; |
| 586 | } |
| 587 | |
Zheng Bao | 6d402ac | 2020-10-01 16:16:30 +0800 | [diff] [blame] | 588 | if ((size_t)fd_stat.st_size > room) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 589 | fprintf(stderr, "Error: %s will not fit. Exiting.\n", src_file); |
Jacob Garber | 967f862 | 2019-07-02 10:35:10 -0600 | [diff] [blame] | 590 | close(fd); |
Marshall Dawson | 8e0dca0 | 2019-02-27 18:40:49 -0700 | [diff] [blame] | 591 | return -3; |
| 592 | } |
| 593 | |
| 594 | bytes = read(fd, dest, (size_t)fd_stat.st_size); |
| 595 | close(fd); |
| 596 | if (bytes != (ssize_t)fd_stat.st_size) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 597 | fprintf(stderr, "Error while reading %s\n", src_file); |
Marshall Dawson | 8e0dca0 | 2019-02-27 18:40:49 -0700 | [diff] [blame] | 598 | return -4; |
| 599 | } |
| 600 | |
| 601 | return bytes; |
| 602 | } |
| 603 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 604 | static void integrate_firmwares(context *ctx, |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 605 | embedded_firmware *romsig, |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 606 | amd_fw_entry *fw_table) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 607 | { |
Richard Spiegel | 137484d | 2018-01-17 10:23:19 -0700 | [diff] [blame] | 608 | ssize_t bytes; |
Zheng Bao | 6d402ac | 2020-10-01 16:16:30 +0800 | [diff] [blame] | 609 | uint32_t i; |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 610 | |
| 611 | ctx->current += sizeof(embedded_firmware); |
| 612 | ctx->current = ALIGN(ctx->current, BLOB_ALIGNMENT); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 613 | |
Martin Roth | cd15bc8 | 2016-11-08 11:34:02 -0700 | [diff] [blame] | 614 | for (i = 0; fw_table[i].type != AMD_FW_INVALID; i++) { |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 615 | if (fw_table[i].filename != NULL) { |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 616 | switch (fw_table[i].type) { |
| 617 | case AMD_FW_IMC: |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 618 | ctx->current = ALIGN(ctx->current, 0x10000U); |
| 619 | romsig->imc_entry = RUN_CURRENT(*ctx); |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 620 | break; |
| 621 | case AMD_FW_GEC: |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 622 | romsig->gec_entry = RUN_CURRENT(*ctx); |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 623 | break; |
| 624 | case AMD_FW_XHCI: |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 625 | romsig->xhci_entry = RUN_CURRENT(*ctx); |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 626 | break; |
| 627 | default: |
| 628 | /* Error */ |
| 629 | break; |
| 630 | } |
| 631 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 632 | bytes = copy_blob(BUFF_CURRENT(*ctx), |
| 633 | fw_table[i].filename, BUFF_ROOM(*ctx)); |
Marshall Dawson | 02bd773 | 2019-03-13 14:43:17 -0600 | [diff] [blame] | 634 | if (bytes < 0) { |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 635 | free(ctx->rom); |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 636 | exit(1); |
| 637 | } |
| 638 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 639 | ctx->current = ALIGN(ctx->current + bytes, |
| 640 | BLOB_ALIGNMENT); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 641 | } |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 642 | } |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 643 | } |
| 644 | |
Zheng Bao | 9e90807 | 2020-10-28 11:39:13 +0800 | [diff] [blame] | 645 | /* For debugging */ |
| 646 | static void dump_psp_firmwares(amd_fw_entry *fw_table) |
| 647 | { |
| 648 | amd_fw_entry *index; |
| 649 | |
| 650 | printf("PSP firmware components:"); |
| 651 | for (index = fw_table; index->type != AMD_FW_INVALID; index++) { |
| 652 | if (index->filename) |
| 653 | printf(" filename=%s\n", index->filename); |
| 654 | } |
| 655 | } |
| 656 | |
| 657 | static void dump_bdt_firmwares(amd_bios_entry *fw_table) |
| 658 | { |
| 659 | amd_bios_entry *index; |
| 660 | |
| 661 | printf("BIOS Directory Table (BDT) components:"); |
| 662 | for (index = fw_table; index->type != AMD_BIOS_INVALID; index++) { |
| 663 | if (index->filename) |
| 664 | printf(" filename=%s\n", index->filename); |
| 665 | } |
| 666 | } |
| 667 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 668 | static void free_psp_firmware_filenames(amd_fw_entry *fw_table) |
| 669 | { |
| 670 | amd_fw_entry *index; |
| 671 | |
| 672 | for (index = fw_table; index->type != AMD_FW_INVALID; index++) { |
| 673 | if (index->filename && |
| 674 | index->type != AMD_FW_VERSTAGE_SIG && |
| 675 | index->type != AMD_FW_PSP_VERSTAGE && |
| 676 | index->type != AMD_FW_PSP_WHITELIST) { |
| 677 | free(index->filename); |
| 678 | } |
| 679 | } |
| 680 | } |
| 681 | |
| 682 | static void free_bdt_firmware_filenames(amd_bios_entry *fw_table) |
| 683 | { |
| 684 | amd_bios_entry *index; |
| 685 | |
| 686 | for (index = fw_table; index->type != AMD_BIOS_INVALID; index++) { |
| 687 | if (index->filename && |
| 688 | index->type != AMD_BIOS_APCB && |
| 689 | index->type != AMD_BIOS_BIN && |
| 690 | index->type != AMD_BIOS_APCB_BK) |
| 691 | free(index->filename); |
| 692 | } |
| 693 | } |
| 694 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 695 | static void integrate_psp_firmwares(context *ctx, |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 696 | psp_directory_table *pspdir, |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 697 | psp_directory_table *pspdir2, |
| 698 | amd_fw_entry *fw_table, |
| 699 | uint32_t cookie) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 700 | { |
Richard Spiegel | 137484d | 2018-01-17 10:23:19 -0700 | [diff] [blame] | 701 | ssize_t bytes; |
Marshall Dawson | c38c0c9 | 2019-02-23 16:41:35 -0700 | [diff] [blame] | 702 | unsigned int i, count; |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 703 | int level; |
| 704 | |
| 705 | /* This function can create a primary table, a secondary table, or a |
| 706 | * flattened table which contains all applicable types. These if-else |
| 707 | * statements infer what the caller intended. If a 2nd-level cookie |
| 708 | * is passed, clearly a 2nd-level table is intended. However, a |
| 709 | * 1st-level cookie may indicate level 1 or flattened. If the caller |
| 710 | * passes a pointer to a 2nd-level table, then assume not flat. |
| 711 | */ |
| 712 | if (cookie == PSPL2_COOKIE) |
| 713 | level = PSP_LVL2; |
| 714 | else if (pspdir2) |
| 715 | level = PSP_LVL1; |
| 716 | else |
| 717 | level = PSP_BOTH; |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 718 | |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 719 | ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 720 | |
Marshall Dawson | c38c0c9 | 2019-02-23 16:41:35 -0700 | [diff] [blame] | 721 | for (i = 0, count = 0; fw_table[i].type != AMD_FW_INVALID; i++) { |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 722 | if (!(fw_table[i].level & level)) |
| 723 | continue; |
| 724 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 725 | if (fw_table[i].type == AMD_TOKEN_UNLOCK) { |
| 726 | if (!fw_table[i].other) |
| 727 | continue; |
| 728 | ctx->current = ALIGN(ctx->current, ERASE_ALIGNMENT); |
| 729 | pspdir->entries[count].type = fw_table[i].type; |
| 730 | pspdir->entries[count].size = 4096; /* TODO: doc? */ |
| 731 | pspdir->entries[count].addr = RUN_CURRENT(*ctx); |
| 732 | pspdir->entries[count].subprog = fw_table[i].subprog; |
| 733 | pspdir->entries[count].rsvd = 0; |
| 734 | ctx->current = ALIGN(ctx->current + 4096, 0x100U); |
| 735 | count++; |
| 736 | } else if (fw_table[i].type == AMD_PSP_FUSE_CHAIN) { |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 737 | pspdir->entries[count].type = fw_table[i].type; |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 738 | pspdir->entries[count].subprog = fw_table[i].subprog; |
| 739 | pspdir->entries[count].rsvd = 0; |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 740 | pspdir->entries[count].size = 0xFFFFFFFF; |
Marshall Dawson | ef79fcc | 2019-04-01 10:16:41 -0600 | [diff] [blame] | 741 | pspdir->entries[count].addr = fw_table[i].other; |
Marshall Dawson | c38c0c9 | 2019-02-23 16:41:35 -0700 | [diff] [blame] | 742 | count++; |
Marshall Dawson | 7c1e142 | 2019-04-11 09:44:43 -0600 | [diff] [blame] | 743 | } else if (fw_table[i].type == AMD_FW_PSP_NVRAM) { |
| 744 | if (fw_table[i].filename == NULL) |
| 745 | continue; |
| 746 | /* TODO: Add a way to reserve for NVRAM without |
| 747 | * requiring a filename. This isn't a feature used |
| 748 | * by coreboot systems, so priority is very low. |
| 749 | */ |
| 750 | ctx->current = ALIGN(ctx->current, ERASE_ALIGNMENT); |
| 751 | bytes = copy_blob(BUFF_CURRENT(*ctx), |
| 752 | fw_table[i].filename, BUFF_ROOM(*ctx)); |
| 753 | if (bytes <= 0) { |
| 754 | free(ctx->rom); |
| 755 | exit(1); |
| 756 | } |
| 757 | |
| 758 | pspdir->entries[count].type = fw_table[i].type; |
| 759 | pspdir->entries[count].subprog = fw_table[i].subprog; |
| 760 | pspdir->entries[count].rsvd = 0; |
| 761 | pspdir->entries[count].size = ALIGN(bytes, |
| 762 | ERASE_ALIGNMENT); |
| 763 | pspdir->entries[count].addr = RUN_CURRENT(*ctx); |
| 764 | |
| 765 | ctx->current = ALIGN(ctx->current + bytes, |
| 766 | BLOB_ERASE_ALIGNMENT); |
| 767 | count++; |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 768 | } else if (fw_table[i].filename != NULL) { |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 769 | bytes = copy_blob(BUFF_CURRENT(*ctx), |
| 770 | fw_table[i].filename, BUFF_ROOM(*ctx)); |
Marshall Dawson | 02bd773 | 2019-03-13 14:43:17 -0600 | [diff] [blame] | 771 | if (bytes < 0) { |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 772 | free(ctx->rom); |
Marshall Dawson | 8e0dca0 | 2019-02-27 18:40:49 -0700 | [diff] [blame] | 773 | exit(1); |
| 774 | } |
| 775 | |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 776 | pspdir->entries[count].type = fw_table[i].type; |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 777 | pspdir->entries[count].subprog = fw_table[i].subprog; |
| 778 | pspdir->entries[count].rsvd = 0; |
Marshall Dawson | 8e0dca0 | 2019-02-27 18:40:49 -0700 | [diff] [blame] | 779 | pspdir->entries[count].size = (uint32_t)bytes; |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 780 | pspdir->entries[count].addr = RUN_CURRENT(*ctx); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 781 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 782 | ctx->current = ALIGN(ctx->current + bytes, |
| 783 | BLOB_ALIGNMENT); |
Marshall Dawson | c38c0c9 | 2019-02-23 16:41:35 -0700 | [diff] [blame] | 784 | count++; |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 785 | } else { |
| 786 | /* This APU doesn't have this firmware. */ |
| 787 | } |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 788 | } |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 789 | |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 790 | if (pspdir2) { |
| 791 | pspdir->entries[count].type = AMD_FW_L2_PTR; |
| 792 | pspdir->entries[count].subprog = 0; |
| 793 | pspdir->entries[count].rsvd = 0; |
| 794 | pspdir->entries[count].size = sizeof(pspdir2->header) |
| 795 | + pspdir2->header.num_entries |
| 796 | * sizeof(psp_directory_entry); |
| 797 | |
| 798 | pspdir->entries[count].addr = BUFF_TO_RUN(*ctx, pspdir2); |
| 799 | count++; |
| 800 | } |
| 801 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 802 | if (count > MAX_PSP_ENTRIES) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 803 | fprintf(stderr, "Error: PSP entries exceed max allowed items\n"); |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 804 | free(ctx->rom); |
| 805 | exit(1); |
| 806 | } |
| 807 | |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 808 | fill_dir_header(pspdir, count, cookie, ctx); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 809 | } |
| 810 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 811 | static void *new_bios_dir(context *ctx, int multi) |
| 812 | { |
| 813 | void *ptr; |
| 814 | |
| 815 | /* |
| 816 | * Force both onto boundary when multi. Primary table is after |
| 817 | * updatable table, so alignment ensures primary can stay intact |
| 818 | * if secondary is reprogrammed. |
| 819 | */ |
| 820 | if (multi) |
| 821 | ctx->current = ALIGN(ctx->current, TABLE_ERASE_ALIGNMENT); |
| 822 | else |
| 823 | ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT); |
| 824 | ptr = BUFF_CURRENT(*ctx); |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 825 | ((bios_directory_hdr *) ptr)->additional_info = ctx->current; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 826 | ctx->current += sizeof(bios_directory_hdr) |
| 827 | + MAX_BIOS_ENTRIES * sizeof(bios_directory_entry); |
| 828 | return ptr; |
| 829 | } |
| 830 | |
| 831 | static int locate_bdt2_bios(bios_directory_table *level2, |
| 832 | uint64_t *source, uint32_t *size) |
| 833 | { |
Zheng Bao | 6d402ac | 2020-10-01 16:16:30 +0800 | [diff] [blame] | 834 | uint32_t i; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 835 | |
| 836 | *source = 0; |
| 837 | *size = 0; |
| 838 | if (!level2) |
| 839 | return 0; |
| 840 | |
| 841 | for (i = 0 ; i < level2->header.num_entries ; i++) { |
| 842 | if (level2->entries[i].type == AMD_BIOS_BIN) { |
| 843 | *source = level2->entries[i].source; |
| 844 | *size = level2->entries[i].size; |
| 845 | return 1; |
| 846 | } |
| 847 | } |
| 848 | return 0; |
| 849 | } |
| 850 | |
| 851 | static int have_bios_tables(amd_bios_entry *table) |
| 852 | { |
| 853 | int i; |
| 854 | |
| 855 | for (i = 0 ; table[i].type != AMD_BIOS_INVALID; i++) { |
| 856 | if (table[i].level & BDT_LVL1 && table[i].filename) |
| 857 | return 1; |
| 858 | } |
| 859 | return 0; |
| 860 | } |
| 861 | |
Marshall Dawson | c4a8c48 | 2020-01-21 17:17:59 -0700 | [diff] [blame] | 862 | static int find_bios_entry(amd_bios_type type) |
| 863 | { |
| 864 | int i; |
| 865 | |
| 866 | for (i = 0; amd_bios_table[i].type != AMD_BIOS_INVALID; i++) { |
| 867 | if (amd_bios_table[i].type == type) |
| 868 | return i; |
| 869 | } |
| 870 | return -1; |
| 871 | } |
| 872 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 873 | static void integrate_bios_firmwares(context *ctx, |
| 874 | bios_directory_table *biosdir, |
| 875 | bios_directory_table *biosdir2, |
| 876 | amd_bios_entry *fw_table, |
| 877 | uint32_t cookie) |
| 878 | { |
| 879 | ssize_t bytes; |
Martin Roth | ec93313 | 2019-07-13 20:03:34 -0600 | [diff] [blame] | 880 | unsigned int i, count; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 881 | int level; |
Marshall Dawson | c4a8c48 | 2020-01-21 17:17:59 -0700 | [diff] [blame] | 882 | int apob_idx; |
Martin Roth | eca423b | 2020-09-01 10:54:11 -0600 | [diff] [blame] | 883 | uint32_t size; |
| 884 | uint64_t source; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 885 | |
| 886 | /* This function can create a primary table, a secondary table, or a |
| 887 | * flattened table which contains all applicable types. These if-else |
| 888 | * statements infer what the caller intended. If a 2nd-level cookie |
| 889 | * is passed, clearly a 2nd-level table is intended. However, a |
| 890 | * 1st-level cookie may indicate level 1 or flattened. If the caller |
| 891 | * passes a pointer to a 2nd-level table, then assume not flat. |
| 892 | */ |
| 893 | if (cookie == BDT2_COOKIE) |
| 894 | level = BDT_LVL2; |
| 895 | else if (biosdir2) |
| 896 | level = BDT_LVL1; |
| 897 | else |
| 898 | level = BDT_BOTH; |
| 899 | |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 900 | ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 901 | |
| 902 | for (i = 0, count = 0; fw_table[i].type != AMD_BIOS_INVALID; i++) { |
| 903 | if (!(fw_table[i].level & level)) |
| 904 | continue; |
| 905 | if (fw_table[i].filename == NULL && ( |
| 906 | fw_table[i].type != AMD_BIOS_APOB && |
| 907 | fw_table[i].type != AMD_BIOS_APOB_NV && |
| 908 | fw_table[i].type != AMD_BIOS_L2_PTR && |
Martin Roth | 9455474 | 2020-04-14 14:59:36 -0600 | [diff] [blame] | 909 | fw_table[i].type != AMD_BIOS_BIN && |
| 910 | fw_table[i].type != AMD_BIOS_PSP_SHARED_MEM)) |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 911 | continue; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 912 | |
| 913 | /* BIOS Directory items may have additional requirements */ |
| 914 | |
Martin Roth | 48dd9fe | 2020-07-29 16:32:25 -0600 | [diff] [blame] | 915 | /* Check APOB_NV requirements */ |
| 916 | if (fw_table[i].type == AMD_BIOS_APOB_NV) { |
| 917 | if (!fw_table[i].size && !fw_table[i].src) |
| 918 | continue; /* APOB_NV not used */ |
| 919 | if (fw_table[i].src && !fw_table[i].size) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 920 | fprintf(stderr, "Error: APOB NV address provided, but no size\n"); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 921 | free(ctx->rom); |
| 922 | exit(1); |
| 923 | } |
Martin Roth | 48dd9fe | 2020-07-29 16:32:25 -0600 | [diff] [blame] | 924 | /* If the APOB isn't used, APOB_NV isn't used either */ |
Marshall Dawson | c4a8c48 | 2020-01-21 17:17:59 -0700 | [diff] [blame] | 925 | apob_idx = find_bios_entry(AMD_BIOS_APOB); |
Martin Roth | 48dd9fe | 2020-07-29 16:32:25 -0600 | [diff] [blame] | 926 | if (apob_idx < 0 || !fw_table[apob_idx].dest) |
| 927 | continue; /* APOV NV not supported */ |
Marshall Dawson | c4a8c48 | 2020-01-21 17:17:59 -0700 | [diff] [blame] | 928 | } |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 929 | |
| 930 | /* APOB_DATA needs destination */ |
| 931 | if (fw_table[i].type == AMD_BIOS_APOB && !fw_table[i].dest) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 932 | fprintf(stderr, "Error: APOB destination not provided\n"); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 933 | free(ctx->rom); |
| 934 | exit(1); |
| 935 | } |
| 936 | |
| 937 | /* BIOS binary must have destination and uncompressed size. If |
| 938 | * no filename given, then user must provide a source address. |
| 939 | */ |
| 940 | if (fw_table[i].type == AMD_BIOS_BIN) { |
| 941 | if (!fw_table[i].dest || !fw_table[i].size) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 942 | fprintf(stderr, "Error: BIOS binary destination and uncompressed size are required\n"); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 943 | free(ctx->rom); |
| 944 | exit(1); |
| 945 | } |
| 946 | if (!fw_table[i].filename && !fw_table[i].src) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 947 | fprintf(stderr, "Error: BIOS binary assumed outside amdfw.rom but no source address given\n"); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 948 | free(ctx->rom); |
| 949 | exit(1); |
| 950 | } |
| 951 | } |
| 952 | |
Martin Roth | 9455474 | 2020-04-14 14:59:36 -0600 | [diff] [blame] | 953 | /* PSP_SHARED_MEM needs a destination and size */ |
| 954 | if (fw_table[i].type == AMD_BIOS_PSP_SHARED_MEM && |
| 955 | (!fw_table[i].dest || !fw_table[i].size)) |
| 956 | continue; |
| 957 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 958 | biosdir->entries[count].type = fw_table[i].type; |
| 959 | biosdir->entries[count].region_type = fw_table[i].region_type; |
| 960 | biosdir->entries[count].dest = fw_table[i].dest ? |
| 961 | fw_table[i].dest : (uint64_t)-1; |
| 962 | biosdir->entries[count].reset = fw_table[i].reset; |
| 963 | biosdir->entries[count].copy = fw_table[i].copy; |
| 964 | biosdir->entries[count].ro = fw_table[i].ro; |
| 965 | biosdir->entries[count].compressed = fw_table[i].zlib; |
| 966 | biosdir->entries[count].inst = fw_table[i].inst; |
| 967 | biosdir->entries[count].subprog = fw_table[i].subpr; |
| 968 | |
| 969 | switch (fw_table[i].type) { |
| 970 | case AMD_BIOS_APOB: |
| 971 | biosdir->entries[count].size = fw_table[i].size; |
| 972 | biosdir->entries[count].source = fw_table[i].src; |
| 973 | break; |
| 974 | case AMD_BIOS_APOB_NV: |
| 975 | if (fw_table[i].src) { |
| 976 | /* If source is given, use that and its size */ |
| 977 | biosdir->entries[count].source = fw_table[i].src; |
| 978 | biosdir->entries[count].size = fw_table[i].size; |
| 979 | } else { |
| 980 | /* Else reserve size bytes within amdfw.rom */ |
| 981 | ctx->current = ALIGN(ctx->current, ERASE_ALIGNMENT); |
| 982 | biosdir->entries[count].source = RUN_CURRENT(*ctx); |
| 983 | biosdir->entries[count].size = ALIGN( |
| 984 | fw_table[i].size, ERASE_ALIGNMENT); |
| 985 | memset(BUFF_CURRENT(*ctx), 0xff, |
| 986 | biosdir->entries[count].size); |
| 987 | ctx->current = ctx->current |
| 988 | + biosdir->entries[count].size; |
| 989 | } |
| 990 | break; |
| 991 | case AMD_BIOS_BIN: |
| 992 | /* Don't make a 2nd copy, point to the same one */ |
Martin Roth | eca423b | 2020-09-01 10:54:11 -0600 | [diff] [blame] | 993 | if (level == BDT_LVL1 && locate_bdt2_bios(biosdir2, &source, &size)) { |
| 994 | biosdir->entries[count].source = source; |
| 995 | biosdir->entries[count].size = size; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 996 | break; |
Martin Roth | eca423b | 2020-09-01 10:54:11 -0600 | [diff] [blame] | 997 | } |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 998 | |
| 999 | /* level 2, or level 1 and no copy found in level 2 */ |
| 1000 | biosdir->entries[count].source = fw_table[i].src; |
| 1001 | biosdir->entries[count].dest = fw_table[i].dest; |
| 1002 | biosdir->entries[count].size = fw_table[i].size; |
| 1003 | |
| 1004 | if (!fw_table[i].filename) |
| 1005 | break; |
| 1006 | |
| 1007 | bytes = copy_blob(BUFF_CURRENT(*ctx), |
| 1008 | fw_table[i].filename, BUFF_ROOM(*ctx)); |
| 1009 | if (bytes <= 0) { |
| 1010 | free(ctx->rom); |
| 1011 | exit(1); |
| 1012 | } |
| 1013 | |
| 1014 | biosdir->entries[count].source = RUN_CURRENT(*ctx); |
| 1015 | |
| 1016 | ctx->current = ALIGN(ctx->current + bytes, 0x100U); |
| 1017 | break; |
Martin Roth | 9455474 | 2020-04-14 14:59:36 -0600 | [diff] [blame] | 1018 | case AMD_BIOS_PSP_SHARED_MEM: |
| 1019 | biosdir->entries[count].dest = fw_table[i].dest; |
| 1020 | biosdir->entries[count].size = fw_table[i].size; |
| 1021 | break; |
| 1022 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1023 | default: /* everything else is copied from input */ |
| 1024 | if (fw_table[i].type == AMD_BIOS_APCB || |
| 1025 | fw_table[i].type == AMD_BIOS_APCB_BK) |
| 1026 | ctx->current = ALIGN( |
| 1027 | ctx->current, ERASE_ALIGNMENT); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1028 | bytes = copy_blob(BUFF_CURRENT(*ctx), |
| 1029 | fw_table[i].filename, BUFF_ROOM(*ctx)); |
| 1030 | if (bytes <= 0) { |
| 1031 | free(ctx->rom); |
| 1032 | exit(1); |
| 1033 | } |
| 1034 | |
| 1035 | biosdir->entries[count].size = (uint32_t)bytes; |
| 1036 | biosdir->entries[count].source = RUN_CURRENT(*ctx); |
| 1037 | |
| 1038 | ctx->current = ALIGN(ctx->current + bytes, 0x100U); |
| 1039 | break; |
| 1040 | } |
| 1041 | |
| 1042 | count++; |
| 1043 | } |
| 1044 | |
| 1045 | if (biosdir2) { |
| 1046 | biosdir->entries[count].type = AMD_BIOS_L2_PTR; |
Zheng Bao | e8e6043 | 2021-05-24 16:11:12 +0800 | [diff] [blame^] | 1047 | biosdir->entries[count].region_type = 0; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1048 | biosdir->entries[count].size = |
| 1049 | + MAX_BIOS_ENTRIES |
| 1050 | * sizeof(bios_directory_entry); |
| 1051 | biosdir->entries[count].source = |
| 1052 | BUFF_TO_RUN(*ctx, biosdir2); |
| 1053 | biosdir->entries[count].subprog = 0; |
| 1054 | biosdir->entries[count].inst = 0; |
| 1055 | biosdir->entries[count].copy = 0; |
| 1056 | biosdir->entries[count].compressed = 0; |
| 1057 | biosdir->entries[count].dest = -1; |
| 1058 | biosdir->entries[count].reset = 0; |
| 1059 | biosdir->entries[count].ro = 0; |
| 1060 | count++; |
| 1061 | } |
| 1062 | |
| 1063 | if (count > MAX_BIOS_ENTRIES) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1064 | fprintf(stderr, "Error: BIOS entries (%d) exceeds max allowed items " |
Rob Barnes | 18fd26c | 2020-03-03 10:35:02 -0700 | [diff] [blame] | 1065 | "(%d)\n", count, MAX_BIOS_ENTRIES); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1066 | free(ctx->rom); |
| 1067 | exit(1); |
| 1068 | } |
| 1069 | |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 1070 | fill_dir_header(biosdir, count, cookie, ctx); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1071 | } |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1072 | |
| 1073 | enum { |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1074 | AMDFW_OPT_CONFIG = 'c', |
| 1075 | AMDFW_OPT_DEBUG = 'd', |
| 1076 | AMDFW_OPT_HELP = 'h', |
| 1077 | AMDFW_OPT_LIST_DEPEND = 'l', |
| 1078 | |
| 1079 | AMDFW_OPT_XHCI = 128, |
| 1080 | AMDFW_OPT_IMC, |
| 1081 | AMDFW_OPT_GEC, |
| 1082 | AMDFW_OPT_COMBO, |
| 1083 | AMDFW_OPT_MULTILEVEL, |
| 1084 | AMDFW_OPT_NVRAM, |
| 1085 | |
| 1086 | AMDFW_OPT_FUSE, |
| 1087 | AMDFW_OPT_UNLOCK, |
| 1088 | AMDFW_OPT_WHITELIST, |
| 1089 | AMDFW_OPT_USE_PSPSECUREOS, |
| 1090 | AMDFW_OPT_LOAD_MP2FW, |
| 1091 | AMDFW_OPT_LOAD_S0I3, |
| 1092 | AMDFW_OPT_VERSTAGE, |
| 1093 | AMDFW_OPT_VERSTAGE_SIG, |
| 1094 | |
| 1095 | AMDFW_OPT_INSTANCE, |
| 1096 | AMDFW_OPT_APCB, |
| 1097 | AMDFW_OPT_APOBBASE, |
| 1098 | AMDFW_OPT_BIOSBIN, |
| 1099 | AMDFW_OPT_BIOSBIN_SOURCE, |
| 1100 | AMDFW_OPT_BIOSBIN_DEST, |
| 1101 | AMDFW_OPT_BIOS_UNCOMP_SIZE, |
| 1102 | AMDFW_OPT_UCODE, |
| 1103 | AMDFW_OPT_APOB_NVBASE, |
| 1104 | AMDFW_OPT_APOB_NVSIZE, |
| 1105 | |
| 1106 | AMDFW_OPT_OUTPUT, |
| 1107 | AMDFW_OPT_FLASHSIZE, |
| 1108 | AMDFW_OPT_LOCATION, |
| 1109 | AMDFW_OPT_ANYWHERE, |
| 1110 | AMDFW_OPT_SHAREDMEM, |
| 1111 | AMDFW_OPT_SHAREDMEM_SIZE, |
| 1112 | AMDFW_OPT_SOC_NAME, |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1113 | /* begin after ASCII characters */ |
| 1114 | LONGOPT_SPI_READ_MODE = 256, |
| 1115 | LONGOPT_SPI_SPEED = 257, |
| 1116 | LONGOPT_SPI_MICRON_FLAG = 258, |
| 1117 | }; |
| 1118 | |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1119 | static char const optstring[] = {AMDFW_OPT_CONFIG, ':', |
| 1120 | AMDFW_OPT_DEBUG, AMDFW_OPT_HELP, AMDFW_OPT_LIST_DEPEND |
| 1121 | }; |
Marc Jones | 90099b6 | 2016-09-20 21:05:45 -0600 | [diff] [blame] | 1122 | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1123 | static struct option long_options[] = { |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1124 | {"xhci", required_argument, 0, AMDFW_OPT_XHCI }, |
| 1125 | {"imc", required_argument, 0, AMDFW_OPT_IMC }, |
| 1126 | {"gec", required_argument, 0, AMDFW_OPT_GEC }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1127 | /* PSP Directory Table items */ |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1128 | {"combo-capable", no_argument, 0, AMDFW_OPT_COMBO }, |
| 1129 | {"multilevel", no_argument, 0, AMDFW_OPT_MULTILEVEL }, |
| 1130 | {"nvram", required_argument, 0, AMDFW_OPT_NVRAM }, |
| 1131 | {"soft-fuse", required_argument, 0, AMDFW_OPT_FUSE }, |
| 1132 | {"token-unlock", no_argument, 0, AMDFW_OPT_UNLOCK }, |
| 1133 | {"whitelist", required_argument, 0, AMDFW_OPT_WHITELIST }, |
| 1134 | {"use-pspsecureos", no_argument, 0, AMDFW_OPT_USE_PSPSECUREOS }, |
| 1135 | {"load-mp2-fw", no_argument, 0, AMDFW_OPT_LOAD_MP2FW }, |
| 1136 | {"load-s0i3", no_argument, 0, AMDFW_OPT_LOAD_S0I3 }, |
| 1137 | {"verstage", required_argument, 0, AMDFW_OPT_VERSTAGE }, |
| 1138 | {"verstage_sig", required_argument, 0, AMDFW_OPT_VERSTAGE_SIG }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1139 | /* BIOS Directory Table items */ |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1140 | {"instance", required_argument, 0, AMDFW_OPT_INSTANCE }, |
| 1141 | {"apcb", required_argument, 0, AMDFW_OPT_APCB }, |
| 1142 | {"apob-base", required_argument, 0, AMDFW_OPT_APOBBASE }, |
| 1143 | {"bios-bin", required_argument, 0, AMDFW_OPT_BIOSBIN }, |
| 1144 | {"bios-bin-src", required_argument, 0, AMDFW_OPT_BIOSBIN_SOURCE }, |
| 1145 | {"bios-bin-dest", required_argument, 0, AMDFW_OPT_BIOSBIN_DEST }, |
| 1146 | {"bios-uncomp-size", required_argument, 0, AMDFW_OPT_BIOS_UNCOMP_SIZE }, |
| 1147 | {"ucode", required_argument, 0, AMDFW_OPT_UCODE }, |
| 1148 | {"apob-nv-base", required_argument, 0, AMDFW_OPT_APOB_NVBASE }, |
| 1149 | {"apob-nv-size", required_argument, 0, AMDFW_OPT_APOB_NVSIZE }, |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1150 | /* Embedded Firmware Structure items*/ |
| 1151 | {"spi-read-mode", required_argument, 0, LONGOPT_SPI_READ_MODE }, |
| 1152 | {"spi-speed", required_argument, 0, LONGOPT_SPI_SPEED }, |
| 1153 | {"spi-micron-flag", required_argument, 0, LONGOPT_SPI_MICRON_FLAG }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1154 | /* other */ |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1155 | {"output", required_argument, 0, AMDFW_OPT_OUTPUT }, |
| 1156 | {"flashsize", required_argument, 0, AMDFW_OPT_FLASHSIZE }, |
| 1157 | {"location", required_argument, 0, AMDFW_OPT_LOCATION }, |
| 1158 | {"anywhere", no_argument, 0, AMDFW_OPT_ANYWHERE }, |
| 1159 | {"sharedmem", required_argument, 0, AMDFW_OPT_SHAREDMEM }, |
| 1160 | {"sharedmem-size", required_argument, 0, AMDFW_OPT_SHAREDMEM_SIZE }, |
| 1161 | {"soc-name", required_argument, 0, AMDFW_OPT_SOC_NAME }, |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1162 | |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1163 | {"config", required_argument, 0, AMDFW_OPT_CONFIG }, |
| 1164 | {"debug", no_argument, 0, AMDFW_OPT_DEBUG }, |
| 1165 | {"help", no_argument, 0, AMDFW_OPT_HELP }, |
| 1166 | {"list", no_argument, 0, AMDFW_OPT_LIST_DEPEND }, |
Marshall Dawson | f4b9b41 | 2017-03-17 16:30:51 -0600 | [diff] [blame] | 1167 | {NULL, 0, 0, 0 } |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1168 | }; |
| 1169 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1170 | void register_fw_fuse(char *str) |
Marshall Dawson | ef79fcc | 2019-04-01 10:16:41 -0600 | [diff] [blame] | 1171 | { |
Zheng Bao | 6d402ac | 2020-10-01 16:16:30 +0800 | [diff] [blame] | 1172 | uint32_t i; |
Marshall Dawson | ef79fcc | 2019-04-01 10:16:41 -0600 | [diff] [blame] | 1173 | |
| 1174 | for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) { |
| 1175 | if (amd_psp_fw_table[i].type != AMD_PSP_FUSE_CHAIN) |
| 1176 | continue; |
| 1177 | |
| 1178 | amd_psp_fw_table[i].other = strtoull(str, NULL, 16); |
| 1179 | return; |
| 1180 | } |
| 1181 | } |
| 1182 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1183 | static void register_fw_token_unlock(void) |
| 1184 | { |
Zheng Bao | 6d402ac | 2020-10-01 16:16:30 +0800 | [diff] [blame] | 1185 | uint32_t i; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1186 | |
| 1187 | for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) { |
| 1188 | if (amd_psp_fw_table[i].type != AMD_TOKEN_UNLOCK) |
| 1189 | continue; |
| 1190 | |
| 1191 | amd_psp_fw_table[i].other = 1; |
| 1192 | return; |
| 1193 | } |
| 1194 | } |
| 1195 | |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1196 | static void register_fw_filename(amd_fw_type type, uint8_t sub, char filename[]) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1197 | { |
Martin Roth | 8806f7f | 2016-11-08 10:44:18 -0700 | [diff] [blame] | 1198 | unsigned int i; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1199 | |
Martin Roth | cd15bc8 | 2016-11-08 11:34:02 -0700 | [diff] [blame] | 1200 | for (i = 0; i < sizeof(amd_fw_table) / sizeof(amd_fw_entry); i++) { |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1201 | if (amd_fw_table[i].type == type) { |
| 1202 | amd_fw_table[i].filename = filename; |
| 1203 | return; |
| 1204 | } |
| 1205 | } |
| 1206 | |
Marshall Dawson | 0e02ce8 | 2019-03-04 16:50:37 -0700 | [diff] [blame] | 1207 | for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) { |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1208 | if (amd_psp_fw_table[i].type != type) |
| 1209 | continue; |
| 1210 | |
| 1211 | if (amd_psp_fw_table[i].subprog == sub) { |
Marshall Dawson | 0e02ce8 | 2019-03-04 16:50:37 -0700 | [diff] [blame] | 1212 | amd_psp_fw_table[i].filename = filename; |
| 1213 | return; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1214 | } |
| 1215 | } |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1216 | } |
| 1217 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1218 | static void register_bdt_data(amd_bios_type type, int sub, int ins, char name[]) |
| 1219 | { |
Zheng Bao | 6d402ac | 2020-10-01 16:16:30 +0800 | [diff] [blame] | 1220 | uint32_t i; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1221 | |
| 1222 | for (i = 0; i < sizeof(amd_bios_table) / sizeof(amd_bios_entry); i++) { |
| 1223 | if (amd_bios_table[i].type == type |
| 1224 | && amd_bios_table[i].inst == ins |
| 1225 | && amd_bios_table[i].subpr == sub) { |
| 1226 | amd_bios_table[i].filename = name; |
| 1227 | return; |
| 1228 | } |
| 1229 | } |
| 1230 | } |
| 1231 | |
Martin Roth | ec93313 | 2019-07-13 20:03:34 -0600 | [diff] [blame] | 1232 | static void register_fw_addr(amd_bios_type type, char *src_str, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1233 | char *dst_str, char *size_str) |
| 1234 | { |
Zheng Bao | 6d402ac | 2020-10-01 16:16:30 +0800 | [diff] [blame] | 1235 | uint32_t i; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1236 | for (i = 0; i < sizeof(amd_bios_table) / sizeof(amd_bios_entry); i++) { |
| 1237 | if (amd_bios_table[i].type != type) |
| 1238 | continue; |
| 1239 | |
| 1240 | if (src_str) |
| 1241 | amd_bios_table[i].src = strtoull(src_str, NULL, 16); |
| 1242 | if (dst_str) |
| 1243 | amd_bios_table[i].dest = strtoull(dst_str, NULL, 16); |
| 1244 | if (size_str) |
| 1245 | amd_bios_table[i].size = strtoul(size_str, NULL, 16); |
| 1246 | |
| 1247 | return; |
| 1248 | } |
| 1249 | } |
| 1250 | |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1251 | enum platform { |
| 1252 | PLATFORM_UNKNOWN, |
| 1253 | PLATFORM_STONEYRIDGE, |
| 1254 | PLATFORM_RAVEN, |
| 1255 | PLATFORM_PICASSO, |
| 1256 | PLATFORM_RENOIR, |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 1257 | PLATFORM_CEZANNE, |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1258 | PLATFORM_LUCIENNE, |
| 1259 | }; |
| 1260 | |
| 1261 | static int set_efs_table(uint8_t soc_id, embedded_firmware *amd_romsig, |
| 1262 | uint8_t efs_spi_readmode, uint8_t efs_spi_speed, |
| 1263 | uint8_t efs_spi_micron_flag) |
| 1264 | { |
| 1265 | if ((efs_spi_readmode == 0xFF) || (efs_spi_speed == 0xFF)) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1266 | fprintf(stderr, "Error: EFS read mode and SPI speed must be set\n"); |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1267 | return 1; |
| 1268 | } |
| 1269 | switch (soc_id) { |
| 1270 | case PLATFORM_STONEYRIDGE: |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1271 | amd_romsig->spi_readmode_f15_mod_60_6f = efs_spi_readmode; |
| 1272 | amd_romsig->fast_speed_new_f15_mod_60_6f = efs_spi_speed; |
| 1273 | break; |
| 1274 | case PLATFORM_RAVEN: |
| 1275 | case PLATFORM_PICASSO: |
Marshall Dawson | 13ec029 | 2020-11-19 14:02:29 -0700 | [diff] [blame] | 1276 | /* amd_romsig->efs_gen introduced after RAVEN/PICASSO. |
| 1277 | * Leave as 0xffffffff for first gen */ |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1278 | amd_romsig->spi_readmode_f17_mod_00_2f = efs_spi_readmode; |
| 1279 | amd_romsig->spi_fastspeed_f17_mod_00_2f = efs_spi_speed; |
| 1280 | switch (efs_spi_micron_flag) { |
| 1281 | case 0: |
| 1282 | amd_romsig->qpr_dummy_cycle_f17_mod_00_2f = 0xff; |
| 1283 | break; |
| 1284 | case 1: |
| 1285 | amd_romsig->qpr_dummy_cycle_f17_mod_00_2f = 0xa; |
| 1286 | break; |
| 1287 | default: |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1288 | fprintf(stderr, "Error: EFS Micron flag must be correctly set.\n\n"); |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1289 | return 1; |
| 1290 | } |
| 1291 | break; |
| 1292 | case PLATFORM_RENOIR: |
| 1293 | case PLATFORM_LUCIENNE: |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 1294 | case PLATFORM_CEZANNE: |
Marshall Dawson | 13ec029 | 2020-11-19 14:02:29 -0700 | [diff] [blame] | 1295 | amd_romsig->efs_gen.gen = EFS_SECOND_GEN; |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1296 | amd_romsig->spi_readmode_f17_mod_30_3f = efs_spi_readmode; |
| 1297 | amd_romsig->spi_fastspeed_f17_mod_30_3f = efs_spi_speed; |
| 1298 | switch (efs_spi_micron_flag) { |
| 1299 | case 0: |
| 1300 | amd_romsig->micron_detect_f17_mod_30_3f = 0xff; |
| 1301 | break; |
| 1302 | case 1: |
| 1303 | amd_romsig->micron_detect_f17_mod_30_3f = 0xaa; |
| 1304 | break; |
| 1305 | case 2: |
| 1306 | amd_romsig->micron_detect_f17_mod_30_3f = 0x55; |
| 1307 | break; |
| 1308 | default: |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1309 | fprintf(stderr, "Error: EFS Micron flag must be correctly set.\n\n"); |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1310 | return 1; |
| 1311 | } |
| 1312 | break; |
| 1313 | case PLATFORM_UNKNOWN: |
| 1314 | default: |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1315 | fprintf(stderr, "Error: Invalid SOC name.\n\n"); |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1316 | return 1; |
| 1317 | } |
| 1318 | return 0; |
| 1319 | } |
| 1320 | |
| 1321 | static int identify_platform(char *soc_name) |
| 1322 | { |
| 1323 | if (!strcasecmp(soc_name, "Stoneyridge")) |
| 1324 | return PLATFORM_STONEYRIDGE; |
| 1325 | else if (!strcasecmp(soc_name, "Raven")) |
| 1326 | return PLATFORM_RAVEN; |
| 1327 | else if (!strcasecmp(soc_name, "Picasso")) |
| 1328 | return PLATFORM_PICASSO; |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 1329 | else if (!strcasecmp(soc_name, "Cezanne")) |
| 1330 | return PLATFORM_CEZANNE; |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1331 | else if (!strcasecmp(soc_name, "Renoir")) |
| 1332 | return PLATFORM_RENOIR; |
| 1333 | else if (!strcasecmp(soc_name, "Lucienne")) |
| 1334 | return PLATFORM_LUCIENNE; |
| 1335 | else |
| 1336 | return PLATFORM_UNKNOWN; |
| 1337 | |
| 1338 | } |
| 1339 | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1340 | int main(int argc, char **argv) |
| 1341 | { |
Marshall Dawson | 0e02ce8 | 2019-03-04 16:50:37 -0700 | [diff] [blame] | 1342 | int c; |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 1343 | int retval = 0; |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 1344 | char *tmp; |
Martin Roth | 8806f7f | 2016-11-08 10:44:18 -0700 | [diff] [blame] | 1345 | char *rom = NULL; |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 1346 | embedded_firmware *amd_romsig; |
| 1347 | psp_directory_table *pspdir; |
Marshall Dawson | 67d868d | 2019-02-28 11:43:40 -0700 | [diff] [blame] | 1348 | int comboable = 0; |
Marshall Dawson | ef79fcc | 2019-04-01 10:16:41 -0600 | [diff] [blame] | 1349 | int fuse_defined = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1350 | int targetfd; |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1351 | char *output = NULL, *config = NULL; |
| 1352 | FILE *config_handle; |
Zheng Bao | 9c8ce3e | 2020-09-28 10:36:29 +0800 | [diff] [blame] | 1353 | context ctx = { 0 }; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1354 | /* Values cleared after each firmware or parameter, regardless if N/A */ |
| 1355 | uint8_t sub = 0, instance = 0; |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 1356 | uint32_t dir_location = 0; |
Martin Roth | 37305e7 | 2020-04-07 14:16:39 -0600 | [diff] [blame] | 1357 | bool any_location = 0; |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 1358 | uint32_t romsig_offset; |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 1359 | uint32_t rom_base_address; |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1360 | uint8_t soc_id = PLATFORM_UNKNOWN; |
| 1361 | uint8_t efs_spi_readmode = 0xff; |
| 1362 | uint8_t efs_spi_speed = 0xff; |
| 1363 | uint8_t efs_spi_micron_flag = 0xff; |
| 1364 | |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 1365 | int multi = 0; |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1366 | amd_cb_config cb_config; |
Zheng Bao | 9e90807 | 2020-10-28 11:39:13 +0800 | [diff] [blame] | 1367 | int debug = 0; |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1368 | int list_deps = 0; |
| 1369 | |
| 1370 | cb_config.have_whitelist = 0; |
| 1371 | cb_config.unlock_secure = 0; |
| 1372 | cb_config.use_secureos = 0; |
| 1373 | cb_config.load_mp2_fw = 0; |
| 1374 | cb_config.s0i3 = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1375 | |
| 1376 | while (1) { |
| 1377 | int optindex = 0; |
| 1378 | |
| 1379 | c = getopt_long(argc, argv, optstring, long_options, &optindex); |
| 1380 | |
| 1381 | if (c == -1) |
| 1382 | break; |
| 1383 | |
| 1384 | switch (c) { |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1385 | case AMDFW_OPT_XHCI: |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1386 | register_fw_filename(AMD_FW_XHCI, sub, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1387 | sub = instance = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1388 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1389 | case AMDFW_OPT_IMC: |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1390 | register_fw_filename(AMD_FW_IMC, sub, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1391 | sub = instance = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1392 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1393 | case AMDFW_OPT_GEC: |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1394 | register_fw_filename(AMD_FW_GEC, sub, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1395 | sub = instance = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1396 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1397 | case AMDFW_OPT_COMBO: |
Marshall Dawson | 67d868d | 2019-02-28 11:43:40 -0700 | [diff] [blame] | 1398 | comboable = 1; |
| 1399 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1400 | case AMDFW_OPT_MULTILEVEL: |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 1401 | multi = 1; |
| 1402 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1403 | case AMDFW_OPT_UNLOCK: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1404 | register_fw_token_unlock(); |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1405 | cb_config.unlock_secure = 1; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1406 | sub = instance = 0; |
| 1407 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1408 | case AMDFW_OPT_USE_PSPSECUREOS: |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1409 | cb_config.use_secureos = 1; |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1410 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1411 | case AMDFW_OPT_INSTANCE: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1412 | instance = strtoul(optarg, &tmp, 16); |
| 1413 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1414 | case AMDFW_OPT_LOAD_MP2FW: |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1415 | cb_config.load_mp2_fw = 1; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1416 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1417 | case AMDFW_OPT_NVRAM: |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1418 | register_fw_filename(AMD_FW_PSP_NVRAM, sub, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1419 | sub = instance = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1420 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1421 | case AMDFW_OPT_FUSE: |
Marshall Dawson | ef79fcc | 2019-04-01 10:16:41 -0600 | [diff] [blame] | 1422 | register_fw_fuse(optarg); |
| 1423 | fuse_defined = 1; |
| 1424 | sub = 0; |
| 1425 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1426 | case AMDFW_OPT_APCB: |
Zheng Bao | 5caca94 | 2020-12-04 16:39:38 +0800 | [diff] [blame] | 1427 | if ((instance & 0xF0) == 0) |
| 1428 | register_bdt_data(AMD_BIOS_APCB, sub, instance & 0xF, optarg); |
| 1429 | else |
| 1430 | register_bdt_data(AMD_BIOS_APCB_BK, sub, |
| 1431 | instance & 0xF, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1432 | sub = instance = 0; |
| 1433 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1434 | case AMDFW_OPT_APOBBASE: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1435 | /* APOB destination */ |
| 1436 | register_fw_addr(AMD_BIOS_APOB, 0, optarg, 0); |
| 1437 | sub = instance = 0; |
| 1438 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1439 | case AMDFW_OPT_APOB_NVBASE: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1440 | /* APOB NV source */ |
| 1441 | register_fw_addr(AMD_BIOS_APOB_NV, optarg, 0, 0); |
| 1442 | sub = instance = 0; |
| 1443 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1444 | case AMDFW_OPT_APOB_NVSIZE: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1445 | /* APOB NV size */ |
| 1446 | register_fw_addr(AMD_BIOS_APOB_NV, 0, 0, optarg); |
| 1447 | sub = instance = 0; |
| 1448 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1449 | case AMDFW_OPT_BIOSBIN: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1450 | register_bdt_data(AMD_BIOS_BIN, sub, instance, optarg); |
| 1451 | sub = instance = 0; |
| 1452 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1453 | case AMDFW_OPT_BIOSBIN_SOURCE: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1454 | /* BIOS source */ |
| 1455 | register_fw_addr(AMD_BIOS_BIN, optarg, 0, 0); |
| 1456 | sub = instance = 0; |
| 1457 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1458 | case AMDFW_OPT_BIOSBIN_DEST: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1459 | /* BIOS destination */ |
| 1460 | register_fw_addr(AMD_BIOS_BIN, 0, optarg, 0); |
| 1461 | sub = instance = 0; |
| 1462 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1463 | case AMDFW_OPT_BIOS_UNCOMP_SIZE: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1464 | /* BIOS destination size */ |
| 1465 | register_fw_addr(AMD_BIOS_BIN, 0, 0, optarg); |
| 1466 | sub = instance = 0; |
| 1467 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1468 | case AMDFW_OPT_UCODE: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1469 | register_bdt_data(AMD_BIOS_UCODE, sub, |
| 1470 | instance, optarg); |
| 1471 | sub = instance = 0; |
| 1472 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1473 | case AMDFW_OPT_LOAD_S0I3: |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1474 | cb_config.s0i3 = 1; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1475 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1476 | case AMDFW_OPT_WHITELIST: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1477 | register_fw_filename(AMD_FW_PSP_WHITELIST, sub, optarg); |
| 1478 | sub = instance = 0; |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1479 | cb_config.have_whitelist = 1; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1480 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1481 | case AMDFW_OPT_VERSTAGE: |
Martin Roth | d3ce8c8 | 2019-07-13 20:13:07 -0600 | [diff] [blame] | 1482 | register_fw_filename(AMD_FW_PSP_VERSTAGE, sub, optarg); |
| 1483 | sub = instance = 0; |
| 1484 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1485 | case AMDFW_OPT_VERSTAGE_SIG: |
Martin Roth | b1f648f | 2020-09-01 09:36:59 -0600 | [diff] [blame] | 1486 | register_fw_filename(AMD_FW_VERSTAGE_SIG, sub, optarg); |
| 1487 | sub = instance = 0; |
| 1488 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1489 | case AMDFW_OPT_SOC_NAME: |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1490 | soc_id = identify_platform(optarg); |
| 1491 | if (soc_id == PLATFORM_UNKNOWN) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1492 | fprintf(stderr, "Error: Invalid SOC name specified\n\n"); |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1493 | retval = 1; |
| 1494 | } |
| 1495 | sub = instance = 0; |
| 1496 | break; |
| 1497 | case LONGOPT_SPI_READ_MODE: |
| 1498 | efs_spi_readmode = strtoull(optarg, NULL, 16); |
| 1499 | sub = instance = 0; |
| 1500 | break; |
| 1501 | case LONGOPT_SPI_SPEED: |
| 1502 | efs_spi_speed = strtoull(optarg, NULL, 16); |
| 1503 | sub = instance = 0; |
| 1504 | break; |
| 1505 | case LONGOPT_SPI_MICRON_FLAG: |
| 1506 | efs_spi_micron_flag = strtoull(optarg, NULL, 16); |
| 1507 | sub = instance = 0; |
| 1508 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1509 | case AMDFW_OPT_OUTPUT: |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1510 | output = optarg; |
| 1511 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1512 | case AMDFW_OPT_FLASHSIZE: |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1513 | ctx.rom_size = (uint32_t)strtoul(optarg, &tmp, 16); |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 1514 | if (*tmp != '\0') { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1515 | fprintf(stderr, "Error: ROM size specified" |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 1516 | " incorrectly (%s)\n\n", optarg); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 1517 | retval = 1; |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 1518 | } |
| 1519 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1520 | case AMDFW_OPT_LOCATION: |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 1521 | dir_location = (uint32_t)strtoul(optarg, &tmp, 16); |
| 1522 | if (*tmp != '\0') { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1523 | fprintf(stderr, "Error: Directory Location specified" |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 1524 | " incorrectly (%s)\n\n", optarg); |
| 1525 | retval = 1; |
| 1526 | } |
| 1527 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1528 | case AMDFW_OPT_ANYWHERE: |
Martin Roth | 37305e7 | 2020-04-07 14:16:39 -0600 | [diff] [blame] | 1529 | any_location = 1; |
| 1530 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1531 | case AMDFW_OPT_SHAREDMEM: |
Martin Roth | 9455474 | 2020-04-14 14:59:36 -0600 | [diff] [blame] | 1532 | /* shared memory destination */ |
| 1533 | register_fw_addr(AMD_BIOS_PSP_SHARED_MEM, 0, optarg, 0); |
| 1534 | sub = instance = 0; |
| 1535 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1536 | case AMDFW_OPT_SHAREDMEM_SIZE: |
Martin Roth | 9455474 | 2020-04-14 14:59:36 -0600 | [diff] [blame] | 1537 | /* shared memory size */ |
| 1538 | register_fw_addr(AMD_BIOS_PSP_SHARED_MEM, NULL, NULL, optarg); |
| 1539 | sub = instance = 0; |
| 1540 | break; |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 1541 | |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1542 | case AMDFW_OPT_CONFIG: |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1543 | config = optarg; |
| 1544 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1545 | case AMDFW_OPT_DEBUG: |
Zheng Bao | 9e90807 | 2020-10-28 11:39:13 +0800 | [diff] [blame] | 1546 | debug = 1; |
| 1547 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1548 | case AMDFW_OPT_HELP: |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1549 | usage(); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 1550 | return 0; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1551 | case AMDFW_OPT_LIST_DEPEND: |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1552 | list_deps = 1; |
| 1553 | break; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1554 | default: |
| 1555 | break; |
| 1556 | } |
| 1557 | } |
| 1558 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1559 | if (config) { |
| 1560 | config_handle = fopen(config, "r"); |
| 1561 | if (config_handle == NULL) { |
| 1562 | fprintf(stderr, "Can not open file %s for reading: %s\n", |
| 1563 | config, strerror(errno)); |
| 1564 | exit(1); |
| 1565 | } |
| 1566 | if (process_config(config_handle, &cb_config, list_deps) == 0) { |
| 1567 | fprintf(stderr, "Configuration file %s parsing error\n", config); |
| 1568 | fclose(config_handle); |
| 1569 | exit(1); |
| 1570 | } |
| 1571 | fclose(config_handle); |
| 1572 | } |
Zheng Bao | 9e90807 | 2020-10-28 11:39:13 +0800 | [diff] [blame] | 1573 | /* For debug. */ |
| 1574 | if (debug) { |
| 1575 | dump_psp_firmwares(amd_psp_fw_table); |
| 1576 | dump_bdt_firmwares(amd_bios_table); |
| 1577 | } |
| 1578 | |
Marshall Dawson | ef79fcc | 2019-04-01 10:16:41 -0600 | [diff] [blame] | 1579 | if (!fuse_defined) |
| 1580 | register_fw_fuse(DEFAULT_SOFT_FUSE_CHAIN); |
| 1581 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1582 | if (!output && !list_deps) { |
| 1583 | fprintf(stderr, "Error: Output value is not specified.\n\n"); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 1584 | retval = 1; |
| 1585 | } |
| 1586 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1587 | if ((ctx.rom_size % 1024 != 0) && !list_deps) { |
| 1588 | fprintf(stderr, "Error: ROM Size (%d bytes) should be a multiple of" |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1589 | " 1024 bytes.\n\n", ctx.rom_size); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 1590 | retval = 1; |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 1591 | } |
| 1592 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1593 | if ((ctx.rom_size < MIN_ROM_KB * 1024) && !list_deps) { |
| 1594 | fprintf(stderr, "Error: ROM Size (%dKB) must be at least %dKB.\n\n", |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1595 | ctx.rom_size / 1024, MIN_ROM_KB); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 1596 | retval = 1; |
| 1597 | } |
| 1598 | |
| 1599 | if (retval) { |
| 1600 | usage(); |
| 1601 | return retval; |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 1602 | } |
| 1603 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1604 | if (list_deps) { |
| 1605 | return retval; |
| 1606 | } |
| 1607 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1608 | printf(" AMDFWTOOL Using ROM size of %dKB\n", ctx.rom_size / 1024); |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 1609 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1610 | rom_base_address = 0xFFFFFFFF - ctx.rom_size + 1; |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 1611 | if (dir_location && (dir_location < rom_base_address)) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1612 | fprintf(stderr, "Error: Directory location outside of ROM.\n\n"); |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 1613 | return 1; |
| 1614 | } |
| 1615 | |
Martin Roth | 37305e7 | 2020-04-07 14:16:39 -0600 | [diff] [blame] | 1616 | if (any_location) { |
| 1617 | if (dir_location & 0x3f) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1618 | fprintf(stderr, "Error: Invalid Directory location.\n"); |
| 1619 | fprintf(stderr, " Valid locations are 64-byte aligned\n"); |
Martin Roth | 37305e7 | 2020-04-07 14:16:39 -0600 | [diff] [blame] | 1620 | return 1; |
| 1621 | } |
| 1622 | } else { |
| 1623 | switch (dir_location) { |
| 1624 | case 0: /* Fall through */ |
| 1625 | case 0xFFFA0000: /* Fall through */ |
| 1626 | case 0xFFF20000: /* Fall through */ |
| 1627 | case 0xFFE20000: /* Fall through */ |
| 1628 | case 0xFFC20000: /* Fall through */ |
| 1629 | case 0xFF820000: /* Fall through */ |
| 1630 | case 0xFF020000: /* Fall through */ |
| 1631 | break; |
| 1632 | default: |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1633 | fprintf(stderr, "Error: Invalid Directory location.\n"); |
| 1634 | fprintf(stderr, " Valid locations are 0xFFFA0000, 0xFFF20000,\n"); |
| 1635 | fprintf(stderr, " 0xFFE20000, 0xFFC20000, 0xFF820000, 0xFF020000\n"); |
Martin Roth | 37305e7 | 2020-04-07 14:16:39 -0600 | [diff] [blame] | 1636 | return 1; |
| 1637 | } |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 1638 | } |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1639 | ctx.rom = malloc(ctx.rom_size); |
| 1640 | if (!ctx.rom) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1641 | fprintf(stderr, "Error: Failed to allocate memory\n"); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 1642 | return 1; |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1643 | } |
| 1644 | memset(ctx.rom, 0xFF, ctx.rom_size); |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 1645 | |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 1646 | if (dir_location) |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1647 | romsig_offset = ctx.current = dir_location - rom_base_address; |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 1648 | else |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1649 | romsig_offset = ctx.current = AMD_ROMSIG_OFFSET; |
| 1650 | printf(" AMDFWTOOL Using firmware directory location of 0x%08x\n", |
| 1651 | RUN_CURRENT(ctx)); |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 1652 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1653 | amd_romsig = BUFF_OFFSET(ctx, romsig_offset); |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 1654 | amd_romsig->signature = EMBEDDED_FW_SIGNATURE; |
| 1655 | amd_romsig->imc_entry = 0; |
| 1656 | amd_romsig->gec_entry = 0; |
| 1657 | amd_romsig->xhci_entry = 0; |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 1658 | |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1659 | if (soc_id != PLATFORM_UNKNOWN) { |
| 1660 | retval = set_efs_table(soc_id, amd_romsig, efs_spi_readmode, |
| 1661 | efs_spi_speed, efs_spi_micron_flag); |
| 1662 | if (retval) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1663 | fprintf(stderr, "ERROR: Failed to initialize EFS table!\n"); |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1664 | return retval; |
| 1665 | } |
| 1666 | } else { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1667 | fprintf(stderr, "WARNING: No SOC name specified.\n"); |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1668 | } |
| 1669 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1670 | integrate_firmwares(&ctx, amd_romsig, amd_fw_table); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1671 | |
Patrick Georgi | 900a254 | 2020-02-17 16:52:40 +0100 | [diff] [blame] | 1672 | ctx.current = ALIGN(ctx.current, 0x10000U); /* TODO: is it necessary? */ |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1673 | |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 1674 | if (multi) { |
| 1675 | /* Do 2nd PSP directory followed by 1st */ |
| 1676 | psp_directory_table *pspdir2 = new_psp_dir(&ctx, multi); |
| 1677 | integrate_psp_firmwares(&ctx, pspdir2, 0, |
| 1678 | amd_psp_fw_table, PSPL2_COOKIE); |
| 1679 | |
| 1680 | pspdir = new_psp_dir(&ctx, multi); |
| 1681 | integrate_psp_firmwares(&ctx, pspdir, pspdir2, |
| 1682 | amd_psp_fw_table, PSP_COOKIE); |
| 1683 | } else { |
| 1684 | /* flat: PSP 1 cookie and no pointer to 2nd table */ |
| 1685 | pspdir = new_psp_dir(&ctx, multi); |
| 1686 | integrate_psp_firmwares(&ctx, pspdir, 0, |
| 1687 | amd_psp_fw_table, PSP_COOKIE); |
| 1688 | } |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1689 | |
Marshall Dawson | 0e02ce8 | 2019-03-04 16:50:37 -0700 | [diff] [blame] | 1690 | if (comboable) |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1691 | amd_romsig->comboable = BUFF_TO_RUN(ctx, pspdir); |
Marshall Dawson | 67d868d | 2019-02-28 11:43:40 -0700 | [diff] [blame] | 1692 | else |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1693 | amd_romsig->psp_entry = BUFF_TO_RUN(ctx, pspdir); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1694 | |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 1695 | #if PSP_COMBO |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1696 | psp_combo_directory *combo_dir = new_combo_dir(&ctx); |
| 1697 | amd_romsig->comboable = BUFF_TO_RUN(ctx, combo_dir); |
Marshall Dawson | 0e02ce8 | 2019-03-04 16:50:37 -0700 | [diff] [blame] | 1698 | /* 0 -Compare PSP ID, 1 -Compare chip family ID */ |
| 1699 | combo_dir->entries[0].id_sel = 0; |
| 1700 | /* TODO: PSP ID. Documentation is needed. */ |
| 1701 | combo_dir->entries[0].id = 0x10220B00; |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1702 | combo_dir->entries[0].lvl2_addr = BUFF_TO_RUN(ctx, pspdir); |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 1703 | |
Marshall Dawson | 0e02ce8 | 2019-03-04 16:50:37 -0700 | [diff] [blame] | 1704 | combo_dir->header.lookup = 1; |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 1705 | fill_dir_header(combo_dir, 1, PSP2_COOKIE, NULL); |
Marshall Dawson | 0e02ce8 | 2019-03-04 16:50:37 -0700 | [diff] [blame] | 1706 | #endif |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 1707 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1708 | if (have_bios_tables(amd_bios_table)) { |
| 1709 | bios_directory_table *biosdir; |
| 1710 | if (multi) { |
| 1711 | /* Do 2nd level BIOS directory followed by 1st */ |
| 1712 | bios_directory_table *biosdir2 = |
| 1713 | new_bios_dir(&ctx, multi); |
| 1714 | integrate_bios_firmwares(&ctx, biosdir2, 0, |
| 1715 | amd_bios_table, BDT2_COOKIE); |
| 1716 | |
| 1717 | biosdir = new_bios_dir(&ctx, multi); |
| 1718 | integrate_bios_firmwares(&ctx, biosdir, biosdir2, |
| 1719 | amd_bios_table, BDT1_COOKIE); |
| 1720 | } else { |
| 1721 | /* flat: BDT1 cookie and no pointer to 2nd table */ |
| 1722 | biosdir = new_bios_dir(&ctx, multi); |
| 1723 | integrate_bios_firmwares(&ctx, biosdir, 0, |
| 1724 | amd_bios_table, BDT1_COOKIE); |
| 1725 | } |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 1726 | switch (soc_id) { |
| 1727 | case PLATFORM_RENOIR: |
| 1728 | case PLATFORM_LUCIENNE: |
| 1729 | case PLATFORM_CEZANNE: |
| 1730 | amd_romsig->bios3_entry = BUFF_TO_RUN(ctx, biosdir); |
| 1731 | break; |
| 1732 | case PLATFORM_STONEYRIDGE: |
| 1733 | case PLATFORM_RAVEN: |
| 1734 | case PLATFORM_PICASSO: |
| 1735 | default: |
| 1736 | amd_romsig->bios1_entry = BUFF_TO_RUN(ctx, biosdir); |
| 1737 | break; |
| 1738 | } |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1739 | } |
| 1740 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1741 | /* Free the filename. */ |
| 1742 | free_psp_firmware_filenames(amd_psp_fw_table); |
| 1743 | free_bdt_firmware_filenames(amd_bios_table); |
| 1744 | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1745 | targetfd = open(output, O_RDWR | O_CREAT | O_TRUNC, 0666); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 1746 | if (targetfd >= 0) { |
Zheng Bao | 4739691 | 2020-09-29 17:33:17 +0800 | [diff] [blame] | 1747 | ssize_t bytes; |
| 1748 | bytes = write(targetfd, amd_romsig, ctx.current - romsig_offset); |
| 1749 | if (bytes != ctx.current - romsig_offset) { |
| 1750 | fprintf(stderr, "Error: Writing to file %s failed\n", output); |
| 1751 | retval = 1; |
| 1752 | } |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 1753 | close(targetfd); |
| 1754 | } else { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1755 | fprintf(stderr, "Error: could not open file: %s\n", output); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 1756 | retval = 1; |
| 1757 | } |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1758 | |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 1759 | free(rom); |
| 1760 | return retval; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1761 | } |