commit | da83d2c97fe414a3b2fbf6f55b61da5f1533f819 | [log] [tgz] |
---|---|---|
author | Zheng Bao <fishbaozi@gmail.com> | Fri Jun 04 19:03:10 2021 +0800 |
committer | Felix Held <felix-coreboot@felixheld.de> | Tue Dec 14 16:15:52 2021 +0000 |
tree | 23c84739941a1ba8f484b846ffa37ba95a28b4b7 | |
parent | d85cee8310698d88a7e1072563be242045138917 [diff] |
amdfwtool: Use relative address for EFS gen2 The second generation EFS (offset 0x24[0]=0) uses "binary relative" offsets and not "x86 physical MMIO address" like gen1. The field additional_info in table header can tell if the absolute or relative address is used. Chips like Cezanne can run in both cases, so no problem comes up so far. The related change in psp_verstage has been uploaded. https://review.coreboot.org/c/coreboot/+/58316 The relative mode is the mode 1 of four address modes. The absolute mode is the mode 0. Later we will implement mode 2. Not sure if mode 3 is needed. It needs to be simple to work with psp_verstage change to make SOC Cezanne work quickly. This patch is defacto a subset of https://review.coreboot.org/c/coreboot/+/59308 which implements the framework of address mode and covers mode 0,1,2. Some hardcode value like 29 can be removed in 59308. BUG=b:188754219 Test=Majolica (Cezanne) Change-Id: I7701c7819f03586d4ecab3d744056c8c902b630f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you're feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.