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review.coreboot.org / coreboot / 61aee5f4b1d596a0cb007e666df13094abed6d10 / . / src / include / cpu / x86 / mtrr.h
blob: 6ab6bec01504686803db1b0f6d5eeab2de9c7407 [file] [log] [blame]
Eric Biedermanc84c1902004-10-14 20:13:01 +0000[diff] [blame]1#ifndef CPU_X86_MTRR_H
2#define CPU_X86_MTRR_H
3
4
5/* These are the region types */
6#define MTRR_TYPE_UNCACHEABLE 0
7#define MTRR_TYPE_WRCOMB 1
8/*#define MTRR_TYPE_ 2*/
9/*#define MTRR_TYPE_ 3*/
10#define MTRR_TYPE_WRTHROUGH 4
11#define MTRR_TYPE_WRPROT 5
12#define MTRR_TYPE_WRBACK 6
13#define MTRR_NUM_TYPES 7
14
15#define MTRRcap_MSR 0x0fe
16#define MTRRdefType_MSR 0x2ff
17
Uwe Hermann66d16872010-10-01 07:27:51 +0000[diff] [blame]18#define MTRRdefTypeEn (1 << 11)
19#define MTRRdefTypeFixEn (1 << 10)
20
Eric Biedermanc84c1902004-10-14 20:13:01 +0000[diff] [blame]21#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
22#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
23
Kevin O'Connor5bb9fd62011-01-19 06:32:35 +0000[diff] [blame]24#define MTRRphysMaskValid (1 << 11)
25
Eric Biedermanc84c1902004-10-14 20:13:01 +0000[diff] [blame]26#define NUM_FIXED_RANGES 88
27#define MTRRfix64K_00000_MSR 0x250
28#define MTRRfix16K_80000_MSR 0x258
29#define MTRRfix16K_A0000_MSR 0x259
30#define MTRRfix4K_C0000_MSR 0x268
31#define MTRRfix4K_C8000_MSR 0x269
32#define MTRRfix4K_D0000_MSR 0x26a
33#define MTRRfix4K_D8000_MSR 0x26b
34#define MTRRfix4K_E0000_MSR 0x26c
35#define MTRRfix4K_E8000_MSR 0x26d
36#define MTRRfix4K_F0000_MSR 0x26e
37#define MTRRfix4K_F8000_MSR 0x26f
38
Stefan Reinauer61aee5f2011-04-10 04:15:23 +0000[diff] [blame^]39#if !defined (__ASSEMBLER__) && !defined(__PRE_RAM__)
Maciej Pijankaea921852009-10-27 14:29:29 +0000[diff] [blame]40#include <device/device.h>
Maciej Pijankaea921852009-10-27 14:29:29 +0000[diff] [blame]41void enable_fixed_mtrr(void);
Scott Duplichanf3cce2f2010-11-13 19:07:59 +0000[diff] [blame]42void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb);
Yinghai Lu13f1c2a2005-07-08 02:49:49 +0000[diff] [blame]43void x86_setup_mtrrs(unsigned address_bits);
Eric Biedermanc84c1902004-10-14 20:13:01 +0000[diff] [blame]44int x86_mtrr_check(void);
Maciej Pijankaea921852009-10-27 14:29:29 +0000[diff] [blame]45void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res);
46void x86_setup_fixed_mtrrs(void);
Stefan Reinauer35b6bbb2010-03-28 21:26:54 +0000[diff] [blame]47#endif
Eric Biedermanc84c1902004-10-14 20:13:01 +0000[diff] [blame]48
Stefan Reinauer8f2c6162010-04-06 21:50:21 +0000[diff] [blame]49/* Validate CONFIG_XIP_ROM_SIZE and CONFIG_XIP_ROM_BASE */
50#if defined(CONFIG_XIP_ROM_SIZE) && !defined(CONFIG_XIP_ROM_BASE)
51# error "CONFIG_XIP_ROM_SIZE without CONFIG_XIP_ROM_BASE"
52#endif
53#if defined(CONFIG_XIP_ROM_BASE) && !defined(CONFIG_XIP_ROM_SIZE)
54# error "CONFIG_XIP_ROM_BASE without CONFIG_XIP_ROM_SIZE"
55#endif
56#if !defined(CONFIG_RAMTOP)
57# error "CONFIG_RAMTOP not defined"
58#endif
59
60#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0)
61# error "CONFIG_XIP_ROM_SIZE is not a power of 2"
62#endif
63#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_BASE % CONFIG_XIP_ROM_SIZE) != 0)
64# error "CONFIG_XIP_ROM_BASE is not a multiple of CONFIG_XIP_ROM_SIZE"
65#endif
66
67#if (CONFIG_RAMTOP & (CONFIG_RAMTOP -1)) != 0
68# error "CONFIG_RAMTOP must be a power of 2"
69#endif
70
71
Stefan Reinauer61aee5f2011-04-10 04:15:23 +0000[diff] [blame^]72#if !defined (__ASSEMBLER__)
Stefan Reinauer8f2c6162010-04-06 21:50:21 +0000[diff] [blame]73#if defined(CONFIG_XIP_ROM_SIZE)
74# if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
75 extern unsigned long AUTO_XIP_ROM_BASE;
76# define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
77# else
78# define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
79# endif
80#endif
81
82#endif
Eric Biedermanc84c1902004-10-14 20:13:01 +0000[diff] [blame]83
84#endif /* CPU_X86_MTRR_H */