Angel Pons | 60ec365 | 2020-04-03 01:22:13 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 3 | |
| 4 | #include <stdint.h> |
Aaron Durbin | c7633f4 | 2013-06-13 17:29:36 -0700 | [diff] [blame] | 5 | #include <stddef.h> |
Kyösti Mälkki | cd7a70f | 2019-08-17 20:51:08 +0300 | [diff] [blame] | 6 | #include <arch/romstage.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 7 | #include <cpu/intel/haswell/haswell.h> |
| 8 | #include <northbridge/intel/haswell/haswell.h> |
| 9 | #include <northbridge/intel/haswell/raminit.h> |
| 10 | #include <southbridge/intel/lynxpoint/pch.h> |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 11 | #include "gpio.h" |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 12 | |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 13 | const struct rcba_config_instruction rcba_config[] = { |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 14 | /* |
| 15 | * GFX INTA -> PIRQA (MSI) |
| 16 | * D28IP_P1IP WLAN INTA -> PIRQB |
| 17 | * D28IP_P4IP ETH0 INTB -> PIRQC |
| 18 | * D29IP_E1P EHCI1 INTA -> PIRQD |
| 19 | * D26IP_E2P EHCI2 INTA -> PIRQE |
| 20 | * D31IP_SIP SATA INTA -> PIRQF (MSI) |
| 21 | * D31IP_SMIP SMBUS INTB -> PIRQG |
| 22 | * D31IP_TTIP THRT INTC -> PIRQH |
| 23 | * D27IP_ZIP HDA INTA -> PIRQG (MSI) |
| 24 | */ |
| 25 | |
| 26 | /* Device interrupt pin register (board specific) */ |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 27 | RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | |
| 28 | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), |
| 29 | RCBA_SET_REG_32(D30IP, (NOINT << D30IP_PIP)), |
| 30 | RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), |
| 31 | RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | |
| 32 | (INTB << D28IP_P4IP)), |
| 33 | RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), |
| 34 | RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), |
| 35 | RCBA_SET_REG_32(D25IP, (NOINT << D25IP_LIP)), |
| 36 | RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 37 | |
| 38 | /* Device interrupt route registers */ |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 39 | RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQF, PIRQG, PIRQH, PIRQA)), |
| 40 | RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG)), |
| 41 | RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE)), |
| 42 | RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQH, PIRQA, PIRQB)), |
| 43 | RCBA_SET_REG_32(D26IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), |
| 44 | RCBA_SET_REG_32(D25IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), |
| 45 | RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 46 | |
| 47 | /* Disable unused devices (board specific) */ |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 48 | RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 49 | |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 50 | RCBA_END_CONFIG, |
| 51 | }; |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 52 | |
Kyösti Mälkki | 157b189 | 2019-08-16 14:02:25 +0300 | [diff] [blame] | 53 | void mainboard_romstage_entry(void) |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 54 | { |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 55 | struct pei_data pei_data = { |
Edward O'Callaghan | c686c95 | 2014-05-24 02:07:18 +1000 | [diff] [blame] | 56 | .pei_version = PEI_VERSION, |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 57 | .mchbar = (uintptr_t)DEFAULT_MCHBAR, |
| 58 | .dmibar = (uintptr_t)DEFAULT_DMIBAR, |
Edward O'Callaghan | c686c95 | 2014-05-24 02:07:18 +1000 | [diff] [blame] | 59 | .epbar = DEFAULT_EPBAR, |
Kyösti Mälkki | 503d324 | 2019-03-05 07:54:28 +0200 | [diff] [blame] | 60 | .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, |
Edward O'Callaghan | c686c95 | 2014-05-24 02:07:18 +1000 | [diff] [blame] | 61 | .smbusbar = SMBUS_IO_BASE, |
| 62 | .wdbbar = 0x4000000, |
| 63 | .wdbsize = 0x1000, |
| 64 | .hpet_address = HPET_ADDR, |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 65 | .rcba = (uintptr_t)DEFAULT_RCBA, |
Edward O'Callaghan | c686c95 | 2014-05-24 02:07:18 +1000 | [diff] [blame] | 66 | .pmbase = DEFAULT_PMBASE, |
| 67 | .gpiobase = DEFAULT_GPIOBASE, |
| 68 | .temp_mmio_base = 0xfed08000, |
| 69 | .system_type = 0, // 0 Mobile, 1 Desktop/Server |
| 70 | .tseg_size = CONFIG_SMM_TSEG_SIZE, |
| 71 | .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, |
| 72 | .ec_present = 0, |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 73 | // 0 = leave channel enabled |
| 74 | // 1 = disable dimm 0 on channel |
| 75 | // 2 = disable dimm 1 on channel |
| 76 | // 3 = disable dimm 0+1 on channel |
Edward O'Callaghan | c686c95 | 2014-05-24 02:07:18 +1000 | [diff] [blame] | 77 | .dimm_channel0_disabled = 0, |
| 78 | .dimm_channel1_disabled = 0, |
| 79 | .max_ddr3_freq = 1600, |
| 80 | .usb2_ports = { |
Duncan Laurie | bcfcfa4 | 2013-06-03 10:41:12 -0700 | [diff] [blame] | 81 | /* Length, Enable, OCn#, Location */ |
| 82 | { 0x0040, 1, 0, /* P0: Back USB3 port (OC0) */ |
| 83 | USB_PORT_BACK_PANEL }, |
| 84 | { 0x0040, 1, 0, /* P1: Back USB3 port (OC0) */ |
| 85 | USB_PORT_BACK_PANEL }, |
| 86 | { 0x0040, 1, 1, /* P2: Flex Port on bottom (OC1) */ |
| 87 | USB_PORT_FLEX }, |
| 88 | { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: Dock connector */ |
| 89 | USB_PORT_DOCK }, |
| 90 | { 0x0040, 1, USB_OC_PIN_SKIP, /* P4: Mini PCIE */ |
| 91 | USB_PORT_MINI_PCIE }, |
| 92 | { 0x0040, 1, 1, /* P5: USB eSATA header (OC1) */ |
| 93 | USB_PORT_FLEX }, |
| 94 | { 0x0040, 1, 3, /* P6: Front Header J8H2 (OC3) */ |
| 95 | USB_PORT_FRONT_PANEL }, |
| 96 | { 0x0040, 1, 3, /* P7: Front Header J8H2 (OC3) */ |
| 97 | USB_PORT_FRONT_PANEL }, |
| 98 | { 0x0040, 1, 4, /* P8: USB/LAN Jack (OC4) */ |
| 99 | USB_PORT_FRONT_PANEL }, |
| 100 | { 0x0040, 1, 4, /* P9: USB/LAN Jack (OC4) */ |
| 101 | USB_PORT_FRONT_PANEL }, |
| 102 | { 0x0040, 1, 5, /* P10: Front Header J7H3 (OC5) */ |
| 103 | USB_PORT_FRONT_PANEL }, |
| 104 | { 0x0040, 1, 5, /* P11: Front Header J7H3 (OC5) */ |
| 105 | USB_PORT_FRONT_PANEL }, |
| 106 | { 0x0040, 1, 6, /* P12: USB/DP Jack (OC6) */ |
| 107 | USB_PORT_FRONT_PANEL }, |
| 108 | { 0x0040, 1, 6, /* P13: USB/DP Jack (OC6) */ |
| 109 | USB_PORT_FRONT_PANEL }, |
Aaron Durbin | b1c25e7 | 2013-05-23 15:57:46 -0500 | [diff] [blame] | 110 | }, |
Edward O'Callaghan | c686c95 | 2014-05-24 02:07:18 +1000 | [diff] [blame] | 111 | .usb3_ports = { |
Aaron Durbin | b1c25e7 | 2013-05-23 15:57:46 -0500 | [diff] [blame] | 112 | /* Enable, OCn# */ |
| 113 | { 1, 0 }, /* P1; */ |
| 114 | { 1, 0 }, /* P2; */ |
| 115 | { 1, 0 }, /* P3; */ |
| 116 | { 1, 0 }, /* P4; */ |
| 117 | { 1, 0 }, /* P6; */ |
| 118 | { 1, 0 }, /* P6; */ |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 119 | }, |
| 120 | }; |
| 121 | |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 122 | struct romstage_params romstage_params = { |
| 123 | .pei_data = &pei_data, |
| 124 | .gpio_map = &mainboard_gpio_map, |
| 125 | .rcba_config = &rcba_config[0], |
Aaron Durbin | c7633f4 | 2013-06-13 17:29:36 -0700 | [diff] [blame] | 126 | .copy_spd = NULL, |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 127 | }; |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 128 | |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 129 | /* Call into the real romstage main with this board's attributes. */ |
| 130 | romstage_common(&romstage_params); |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 131 | } |