Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <stdint.h> |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 22 | #include <console/console.h> |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 23 | #include "cpu/intel/haswell/haswell.h" |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 24 | #include "northbridge/intel/haswell/haswell.h" |
| 25 | #include "northbridge/intel/haswell/raminit.h" |
| 26 | #include "southbridge/intel/lynxpoint/pch.h" |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 27 | #include "gpio.h" |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 28 | |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 29 | const struct rcba_config_instruction rcba_config[] = { |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 30 | /* |
| 31 | * GFX INTA -> PIRQA (MSI) |
| 32 | * D28IP_P1IP WLAN INTA -> PIRQB |
| 33 | * D28IP_P4IP ETH0 INTB -> PIRQC |
| 34 | * D29IP_E1P EHCI1 INTA -> PIRQD |
| 35 | * D26IP_E2P EHCI2 INTA -> PIRQE |
| 36 | * D31IP_SIP SATA INTA -> PIRQF (MSI) |
| 37 | * D31IP_SMIP SMBUS INTB -> PIRQG |
| 38 | * D31IP_TTIP THRT INTC -> PIRQH |
| 39 | * D27IP_ZIP HDA INTA -> PIRQG (MSI) |
| 40 | */ |
| 41 | |
| 42 | /* Device interrupt pin register (board specific) */ |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 43 | RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | |
| 44 | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), |
| 45 | RCBA_SET_REG_32(D30IP, (NOINT << D30IP_PIP)), |
| 46 | RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), |
| 47 | RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | |
| 48 | (INTB << D28IP_P4IP)), |
| 49 | RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), |
| 50 | RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), |
| 51 | RCBA_SET_REG_32(D25IP, (NOINT << D25IP_LIP)), |
| 52 | RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 53 | |
| 54 | /* Device interrupt route registers */ |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 55 | RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQF, PIRQG, PIRQH, PIRQA)), |
| 56 | RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG)), |
| 57 | RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE)), |
| 58 | RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQH, PIRQA, PIRQB)), |
| 59 | RCBA_SET_REG_32(D26IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), |
| 60 | RCBA_SET_REG_32(D25IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), |
| 61 | RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 62 | |
| 63 | /* Disable unused devices (board specific) */ |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 64 | RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 65 | |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 66 | RCBA_END_CONFIG, |
| 67 | }; |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 68 | |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 69 | void mainboard_romstage_entry(unsigned long bist) |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 70 | { |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 71 | struct pei_data pei_data = { |
| 72 | pei_version: PEI_VERSION, |
| 73 | mchbar: DEFAULT_MCHBAR, |
| 74 | dmibar: DEFAULT_DMIBAR, |
| 75 | epbar: DEFAULT_EPBAR, |
Aaron Durbin | f72ad02 | 2012-11-02 09:19:43 -0500 | [diff] [blame] | 76 | pciexbar: DEFAULT_PCIEXBAR, |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 77 | smbusbar: SMBUS_IO_BASE, |
| 78 | wdbbar: 0x4000000, |
| 79 | wdbsize: 0x1000, |
| 80 | hpet_address: HPET_ADDR, |
| 81 | rcba: DEFAULT_RCBA, |
| 82 | pmbase: DEFAULT_PMBASE, |
| 83 | gpiobase: DEFAULT_GPIOBASE, |
Aaron Durbin | 8256a9b | 2012-11-29 17:18:53 -0600 | [diff] [blame] | 84 | temp_mmio_base: 0xfed08000, |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 85 | system_type: 0, // 0 Mobile, 1 Desktop/Server |
| 86 | tseg_size: CONFIG_SMM_TSEG_SIZE, |
Aaron Durbin | 68724fd | 2012-12-07 09:47:16 -0600 | [diff] [blame] | 87 | spd_addresses: { 0xa0, 0xa2, 0xa4, 0xa6 }, |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 88 | ec_present: 0, |
| 89 | // 0 = leave channel enabled |
| 90 | // 1 = disable dimm 0 on channel |
| 91 | // 2 = disable dimm 1 on channel |
| 92 | // 3 = disable dimm 0+1 on channel |
Aaron Durbin | 68724fd | 2012-12-07 09:47:16 -0600 | [diff] [blame] | 93 | dimm_channel0_disabled: 0, |
| 94 | dimm_channel1_disabled: 0, |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 95 | max_ddr3_freq: 1600, |
Aaron Durbin | b1c25e7 | 2013-05-23 15:57:46 -0500 | [diff] [blame^] | 96 | usb2_ports: { |
| 97 | /* Length, Enable, OCn# */ |
| 98 | { 0x0040, 1, 0 }, /* P0: Back USB3 port (OC0) */ |
| 99 | { 0x0040, 1, 0 }, /* P1: Back USB3 port (OC0) */ |
| 100 | { 0x0040, 1, 1 }, /* P2: Flex Port on bottom (OC1) */ |
| 101 | { 0x0040, 1, USB_OC_PIN_SKIP }, /* P3: Dock connector */ |
| 102 | { 0x0040, 1, USB_OC_PIN_SKIP }, /* P4: Mini PCIE */ |
| 103 | { 0x0040, 1, 1 }, /* P5: USB eSATA header (OC1) */ |
| 104 | { 0x0040, 1, 3 }, /* P6: Front Header J8H2 (OC3) */ |
| 105 | { 0x0040, 1, 3 }, /* P7: Front Header J8H2 (OC3) */ |
| 106 | { 0x0040, 1, 4 }, /* P8: USB/LAN Jack (OC4) */ |
| 107 | { 0x0040, 1, 4 }, /* P9: USB/LAN Jack (OC4) */ |
| 108 | { 0x0040, 1, 5 }, /* P10: Front Header J7H3 (OC5) */ |
| 109 | { 0x0040, 1, 5 }, /* P11: Front Header J7H3 (OC5) */ |
| 110 | { 0x0040, 1, 6 }, /* P12: USB/DP Jack (OC6) */ |
| 111 | { 0x0040, 1, 6 }, /* P13: USB/DP Jack (OC6) */ |
| 112 | }, |
| 113 | usb3_ports: { |
| 114 | /* Enable, OCn# */ |
| 115 | { 1, 0 }, /* P1; */ |
| 116 | { 1, 0 }, /* P2; */ |
| 117 | { 1, 0 }, /* P3; */ |
| 118 | { 1, 0 }, /* P4; */ |
| 119 | { 1, 0 }, /* P6; */ |
| 120 | { 1, 0 }, /* P6; */ |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 121 | }, |
| 122 | }; |
| 123 | |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 124 | struct romstage_params romstage_params = { |
| 125 | .pei_data = &pei_data, |
| 126 | .gpio_map = &mainboard_gpio_map, |
| 127 | .rcba_config = &rcba_config[0], |
| 128 | .bist = bist, |
| 129 | }; |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 130 | |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 131 | /* Call into the real romstage main with this board's attributes. */ |
| 132 | romstage_common(&romstage_params); |
Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 133 | } |