blob: a6adecfcf56347527bf5d1cba1a547a9844440ad [file] [log] [blame]
David Wub95ebf92022-06-06 16:41:31 +08001fw_config
2 field AUDIO 0 2
3 option AUDIO_UNKNOWN 0
4 option NAU88L25B_I2S 1
5 end
David Wu44cc1b92022-10-20 13:33:20 +08006 field BJ_POWER 3 4
7 option BJ_POWER_150W 0
8 option BJ_POWER_230W 1
9 option BJ_POWER_65W 2
10 option BJ_POWER_135W 3
11 end
David Wu72d71812023-07-06 16:59:57 +080012 field MB_USBC 6 7
13 option TC_USB4 0
14 option TC_USB3 1
15 end
David Wu690de6a2023-09-12 23:18:59 +080016 field USB_HUB 32
17 option HUB_ABSENT 0
18 option HUB_PRESENT 1
19 end
David Wub95ebf92022-06-06 16:41:31 +080020end
21
David Wub844e6d2022-05-21 17:02:10 +080022chip soc/intel/alderlake
David Wu0c4ba1b2023-06-02 10:27:39 +080023 register "domain_vr_config[VR_DOMAIN_IA]" = "{
24 .enable_fast_vmode = 1,
25 }"
26
Derek Huang3d2df352022-10-21 10:39:36 +000027 register "sagv" = "SaGv_Enabled"
28
David Wudf721bd0c2022-07-25 11:09:19 +080029 register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port 1
30 register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2 Port 2
31 register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2 Port 4
32
33 register "usb3_ports[0]" = "{
34 .enable = 1,
35 .ocpin = OC_SKIP,
36 .tx_de_emp = 0x2B,
37 .tx_downscale_amp = 0x00,
38 }" # Type-A port A0
39 register "usb3_ports[1]" = "{
40 .enable = 1,
41 .ocpin = OC_SKIP,
42 .tx_de_emp = 0x2B,
43 .tx_downscale_amp = 0x00,
44 }" # Type-A port A1
45
David Wu7524c8d2022-06-02 17:21:00 +080046 register "serial_io_gspi_mode" = "{
47 [PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
48 [PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
49 }"
David Wub844e6d2022-05-21 17:02:10 +080050
David Wuf2df9492022-07-05 17:44:56 +080051 register "ddi_ports_config" = "{
52 [DDI_PORT_A] = DDI_ENABLE_HPD,
53 [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
54 [DDI_PORT_1] = DDI_ENABLE_HPD,
55 [DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
56 }"
57
David Wuf7311322023-07-28 11:08:56 +080058 register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{
59 .tdp_pl1_override = 15,
60 .tdp_pl2_override = 55,
61 .tdp_pl4 = 100,
62 }"
63
David Wu7524c8d2022-06-02 17:21:00 +080064 device domain 0 on
65 device ref dtt on
66 chip drivers/intel/dptf
67 ## sensor information
68 register "options.tsr[0].desc" = ""DRAM""
69 register "options.tsr[1].desc" = ""Charger""
David Wub844e6d2022-05-21 17:02:10 +080070
David Wu7524c8d2022-06-02 17:21:00 +080071 # TODO: below values are initial reference values only
72 ## Active Policy
73 register "policies.active" = "{
74 [0] = {
75 .target = DPTF_CPU,
76 .thresholds = {
77 TEMP_PCT(85, 90),
78 TEMP_PCT(80, 80),
79 TEMP_PCT(75, 70),
80 }
81 }
82 }"
83
84 ## Passive Policy
85 register "policies.passive" = "{
86 [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
87 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000),
88 [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000),
89 }"
90
91 ## Critical Policy
92 register "policies.critical" = "{
93 [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
94 [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
95 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
96 }"
97
98 register "controls.power_limits" = "{
99 .pl1 = {
100 .min_power = 3000,
101 .max_power = 15000,
102 .time_window_min = 28 * MSECS_PER_SEC,
103 .time_window_max = 32 * MSECS_PER_SEC,
104 .granularity = 200,
105 },
106 .pl2 = {
107 .min_power = 55000,
108 .max_power = 55000,
109 .time_window_min = 28 * MSECS_PER_SEC,
110 .time_window_max = 32 * MSECS_PER_SEC,
111 .granularity = 1000,
112 }
113 }"
114
115 ## Charger Performance Control (Control, mA)
116 register "controls.charger_perf" = "{
117 [0] = { 255, 1700 },
118 [1] = { 24, 1500 },
119 [2] = { 16, 1000 },
120 [3] = { 8, 500 }
121 }"
122
123 ## Fan Performance Control (Percent, Speed, Noise, Power)
124 register "controls.fan_perf" = "{
125 [0] = { 90, 6700, 220, 2200, },
126 [1] = { 80, 5800, 180, 1800, },
127 [2] = { 70, 5000, 145, 1450, },
128 [3] = { 60, 4900, 115, 1150, },
129 [4] = { 50, 3838, 90, 900, },
130 [5] = { 40, 2904, 55, 550, },
131 [6] = { 30, 2337, 30, 300, },
132 [7] = { 20, 1608, 15, 150, },
133 [8] = { 10, 800, 10, 100, },
134 [9] = { 0, 0, 0, 50, }
135 }"
136
137 ## Fan options
138 register "options.fan.fine_grained_control" = "1"
139 register "options.fan.step_size" = "2"
140
141 device generic 0 alias dptf_policy on end
142 end
143 end
144 device ref pcie4_0 on
145 # Enable CPU PCIE RP 1 using CLK 0
146 register "cpu_pcie_rp[CPU_RP(1)]" = "{
147 .clk_req = 0,
148 .clk_src = 0,
149 .flags = PCIE_RP_LTR | PCIE_RP_AER,
150 }"
151 end
David Wu72d71812023-07-06 16:59:57 +0800152 device ref tbt_pcie_rp0 on
153 probe MB_USBC TC_USB4
154 end
155 device ref tbt_pcie_rp1 on
156 probe MB_USBC TC_USB4
157 end
158 device ref tbt_pcie_rp2 on
159 probe MB_USBC TC_USB4
160 end
David Wu7524c8d2022-06-02 17:21:00 +0800161 device ref tcss_dma0 on
David Wu72d71812023-07-06 16:59:57 +0800162 probe MB_USBC TC_USB4
David Wu7524c8d2022-06-02 17:21:00 +0800163 chip drivers/intel/usb4/retimer
164 register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
165 use tcss_usb3_port1 as dfp[0].typec_port
166 device generic 0 on end
167 end
168 end
169 device ref cnvi_wifi on
170 chip drivers/wifi/generic
171 register "wake" = "GPE0_PME_B0"
172 device generic 0 on end
173 end
174 end
175 device ref i2c0 on
176 chip drivers/i2c/nau8825
177 register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A23)"
178 register "jkdet_enable" = "1"
179 register "jkdet_pull_enable" = "0"
180 register "jkdet_pull_up" = "0"
181 register "jkdet_polarity" = "1" # ActiveLow
182 register "vref_impedance" = "2" # 125kOhm
183 register "micbias_voltage" = "6" # 2.754
184 register "sar_threshold_num" = "4"
185 register "sar_threshold[0]" = "0x0C"
186 register "sar_threshold[1]" = "0x1C"
187 register "sar_threshold[2]" = "0x38"
188 register "sar_threshold[3]" = "0x60"
189 register "sar_hysteresis" = "1"
190 register "sar_voltage" = "6"
191 register "sar_compare_time" = "0" # 500ns
192 register "sar_sampling_time" = "0" # 2us
193 register "short_key_debounce" = "2" # 100ms
194 register "jack_insert_debounce" = "7" # 512ms
195 register "jack_eject_debounce" = "7" # 512ms
David Wub95ebf92022-06-06 16:41:31 +0800196 device i2c 1a on
197 probe AUDIO NAU88L25B_I2S
198 end
David Wu7524c8d2022-06-02 17:21:00 +0800199 end
200 end
201 device ref pcie_rp7 on
202 chip drivers/net
203 register "wake" = "GPE0_DW0_07"
204 register "led_feature" = "0xe0"
David Wu8a584832023-08-23 11:12:22 +0800205 register "customized_leds" = "0x05af"
David Wu7524c8d2022-06-02 17:21:00 +0800206 register "customized_led0" = "0x23f"
207 register "customized_led2" = "0x028"
208 register "enable_aspm_l1_2" = "1"
Kapil Porwal39f50422022-11-26 02:38:38 +0530209 register "add_acpi_dma_property" = "true"
Matt DeVillier5b4bbe52023-11-19 16:22:21 -0600210 device pci 00.0 on end
David Wu7524c8d2022-06-02 17:21:00 +0800211 end
David Wu8a584832023-08-23 11:12:22 +0800212 end # RTL8125 and RTL8111K Ethernet NIC
David Wu7524c8d2022-06-02 17:21:00 +0800213 device ref pcie_rp8 on
214 chip soc/intel/common/block/pcie/rtd3
215 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
216 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)"
217 register "srcclk_pin" = "3"
218 device generic 0 on end
219 end
220 end #PCIE8 SD card
221 device ref gspi1 off end
222 device ref pch_espi on
223 chip ec/google/chromeec
224 use conn0 as mux_conn[0]
225 device pnp 0c09.0 on end
226 end
227 end
228 device ref pmc hidden
229 chip drivers/intel/pmc_mux
230 device generic 0 on
231 chip drivers/intel/pmc_mux/conn
232 use usb2_port1 as usb2_port
233 use tcss_usb3_port1 as usb3_port
234 device generic 0 alias conn0 on end
235 end
236 end
237 end
238 end
239 device ref tcss_xhci on
240 chip drivers/usb/acpi
241 device ref tcss_root_hub on
242 chip drivers/usb/acpi
243 register "desc" = ""USB3 Type-C Port C0 (MLB)""
244 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
David Wu05d135e2022-06-30 13:33:40 +0800245 register "use_custom_pld" = "true"
246 register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 1))"
David Wu7524c8d2022-06-02 17:21:00 +0800247 device ref tcss_usb3_port1 on end
248 end
249 end
250 end
251 end
252 device ref xhci on
253 chip drivers/usb/acpi
254 device ref xhci_root_hub on
255 chip drivers/usb/acpi
256 register "desc" = ""USB2 Type-C Port C0 (MLB)""
257 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
David Wu05d135e2022-06-30 13:33:40 +0800258 register "use_custom_pld" = "true"
259 register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 1))"
David Wu7524c8d2022-06-02 17:21:00 +0800260 device ref usb2_port1 on end
261 end
262 chip drivers/usb/acpi
263 register "desc" = ""USB2 Type-A Port A3 (MLB)""
264 register "type" = "UPC_TYPE_A"
David Wu05d135e2022-06-30 13:33:40 +0800265 register "use_custom_pld" = "true"
266 register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(5, 1))"
David Wu7524c8d2022-06-02 17:21:00 +0800267 device ref usb2_port6 on end
268 end
269 chip drivers/usb/acpi
270 register "desc" = ""USB2 Type-A Port A2 (MLB)""
271 register "type" = "UPC_TYPE_A"
David Wu05d135e2022-06-30 13:33:40 +0800272 register "use_custom_pld" = "true"
273 register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(6, 1))"
David Wu7524c8d2022-06-02 17:21:00 +0800274 device ref usb2_port7 on end
275 end
276 chip drivers/usb/acpi
277 register "desc" = ""USB2 Type-A Port A1 (MLB)""
278 register "type" = "UPC_TYPE_A"
David Wu05d135e2022-06-30 13:33:40 +0800279 register "use_custom_pld" = "true"
280 register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(4, 1))"
David Wu7524c8d2022-06-02 17:21:00 +0800281 device ref usb2_port8 on end
282 end
283 chip drivers/usb/acpi
284 register "desc" = ""USB2 Type-A Port A0 (MLB)""
285 register "type" = "UPC_TYPE_A"
David Wu05d135e2022-06-30 13:33:40 +0800286 register "use_custom_pld" = "true"
287 register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))"
David Wu690de6a2023-09-12 23:18:59 +0800288 device ref usb2_port9 on
289 probe USB_HUB HUB_ABSENT
290 end
291 end
292 chip drivers/usb/acpi
293 register "desc" = ""USB2 Hub for Type-A Port A0/A4/A5 (MLB)""
294 register "type" = "UPC_TYPE_INTERNAL"
295 device ref usb2_port9 on
296 probe USB_HUB HUB_PRESENT
297 end
David Wu7524c8d2022-06-02 17:21:00 +0800298 end
299 chip drivers/usb/acpi
300 register "desc" = ""USB2 Bluetooth""
301 register "type" = "UPC_TYPE_INTERNAL"
302 register "reset_gpio" =
303 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
304 device ref usb2_port10 on end
305 end
306 chip drivers/usb/acpi
307 register "desc" = ""USB3 Type-A Port A0 (MLB)""
308 register "type" = "UPC_TYPE_USB3_A"
David Wu05d135e2022-06-30 13:33:40 +0800309 register "use_custom_pld" = "true"
310 register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))"
David Wu690de6a2023-09-12 23:18:59 +0800311 device ref usb3_port1 on
312 probe USB_HUB HUB_ABSENT
313 end
314 end
315 chip drivers/usb/acpi
316 register "desc" = ""USB3 Hub for Type-A Port A0/A4/A5 (MLB)""
317 register "type" = "UPC_TYPE_INTERNAL"
318 device ref usb3_port1 on
319 probe USB_HUB HUB_PRESENT
320 end
David Wu7524c8d2022-06-02 17:21:00 +0800321 end
322 chip drivers/usb/acpi
323 register "desc" = ""USB3 Type-A Port A1 (MLB)""
324 register "type" = "UPC_TYPE_USB3_A"
David Wu05d135e2022-06-30 13:33:40 +0800325 register "use_custom_pld" = "true"
326 register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(4, 1))"
David Wu7524c8d2022-06-02 17:21:00 +0800327 device ref usb3_port2 on end
328 end
329 chip drivers/usb/acpi
330 register "desc" = ""USB3 Type-A Port A2 (MLB)""
331 register "type" = "UPC_TYPE_USB3_A"
David Wu05d135e2022-06-30 13:33:40 +0800332 register "use_custom_pld" = "true"
333 register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(6, 1))"
David Wu7524c8d2022-06-02 17:21:00 +0800334 device ref usb3_port3 on end
335 end
336 chip drivers/usb/acpi
337 register "desc" = ""USB3 Type-A Port A3 (MLB)""
338 register "type" = "UPC_TYPE_USB3_A"
David Wu05d135e2022-06-30 13:33:40 +0800339 register "use_custom_pld" = "true"
340 register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(5, 1))"
David Wu7524c8d2022-06-02 17:21:00 +0800341 device ref usb3_port4 on end
342 end
343 end
344 end
345 end
346 end
David Wub844e6d2022-05-21 17:02:10 +0800347end